Line data Source code
1 : /* SPDX-License-Identifier: GPL-2.0 */
2 : #ifndef DRIVERS_PCI_H
3 : #define DRIVERS_PCI_H
4 :
5 : #include <linux/pci.h>
6 :
7 : /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 : #define MAX_NR_DEVFNS 256
9 :
10 : #define PCI_FIND_CAP_TTL 48
11 :
12 : #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13 :
14 : #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
15 :
16 : extern const unsigned char pcie_link_speed[];
17 : extern bool pci_early_dump;
18 :
19 : bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
20 : bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
21 : bool pcie_cap_has_rtctl(const struct pci_dev *dev);
22 :
23 : /* Functions internal to the PCI core code */
24 :
25 : int pci_create_sysfs_dev_files(struct pci_dev *pdev);
26 : void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
27 : void pci_cleanup_rom(struct pci_dev *dev);
28 : #ifdef CONFIG_DMI
29 : extern const struct attribute_group pci_dev_smbios_attr_group;
30 : #endif
31 :
32 : enum pci_mmap_api {
33 : PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
34 : PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
35 : };
36 : int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
37 : enum pci_mmap_api mmap_api);
38 :
39 : bool pci_reset_supported(struct pci_dev *dev);
40 : void pci_init_reset_methods(struct pci_dev *dev);
41 : int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
42 : int pci_bus_error_reset(struct pci_dev *dev);
43 :
44 : struct pci_cap_saved_data {
45 : u16 cap_nr;
46 : bool cap_extended;
47 : unsigned int size;
48 : u32 data[];
49 : };
50 :
51 : struct pci_cap_saved_state {
52 : struct hlist_node next;
53 : struct pci_cap_saved_data cap;
54 : };
55 :
56 : void pci_allocate_cap_save_buffers(struct pci_dev *dev);
57 : void pci_free_cap_save_buffers(struct pci_dev *dev);
58 : int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
59 : int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
60 : u16 cap, unsigned int size);
61 : struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
62 : struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
63 : u16 cap);
64 :
65 : #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
66 : #define PCI_PM_D3HOT_WAIT 10 /* msec */
67 : #define PCI_PM_D3COLD_WAIT 100 /* msec */
68 :
69 : void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
70 : void pci_refresh_power_state(struct pci_dev *dev);
71 : int pci_power_up(struct pci_dev *dev);
72 : void pci_disable_enabled_device(struct pci_dev *dev);
73 : int pci_finish_runtime_suspend(struct pci_dev *dev);
74 : void pcie_clear_device_status(struct pci_dev *dev);
75 : void pcie_clear_root_pme_status(struct pci_dev *dev);
76 : bool pci_check_pme_status(struct pci_dev *dev);
77 : void pci_pme_wakeup_bus(struct pci_bus *bus);
78 : int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
79 : void pci_pme_restore(struct pci_dev *dev);
80 : bool pci_dev_need_resume(struct pci_dev *dev);
81 : void pci_dev_adjust_pme(struct pci_dev *dev);
82 : void pci_dev_complete_resume(struct pci_dev *pci_dev);
83 : void pci_config_pm_runtime_get(struct pci_dev *dev);
84 : void pci_config_pm_runtime_put(struct pci_dev *dev);
85 : void pci_pm_init(struct pci_dev *dev);
86 : void pci_ea_init(struct pci_dev *dev);
87 : void pci_msi_init(struct pci_dev *dev);
88 : void pci_msix_init(struct pci_dev *dev);
89 : bool pci_bridge_d3_possible(struct pci_dev *dev);
90 : void pci_bridge_d3_update(struct pci_dev *dev);
91 : void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
92 : int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
93 :
94 : static inline void pci_wakeup_event(struct pci_dev *dev)
95 : {
96 : /* Wait 100 ms before the system can be put into a sleep state. */
97 0 : pm_wakeup_event(&dev->dev, 100);
98 : }
99 :
100 : static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
101 : {
102 : return !!(pci_dev->subordinate);
103 : }
104 :
105 : static inline bool pci_power_manageable(struct pci_dev *pci_dev)
106 : {
107 : /*
108 : * Currently we allow normal PCI devices and PCI bridges transition
109 : * into D3 if their bridge_d3 is set.
110 : */
111 0 : return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
112 : }
113 :
114 : static inline bool pcie_downstream_port(const struct pci_dev *dev)
115 : {
116 0 : int type = pci_pcie_type(dev);
117 :
118 0 : return type == PCI_EXP_TYPE_ROOT_PORT ||
119 0 : type == PCI_EXP_TYPE_DOWNSTREAM ||
120 : type == PCI_EXP_TYPE_PCIE_BRIDGE;
121 : }
122 :
123 : void pci_vpd_init(struct pci_dev *dev);
124 : void pci_vpd_release(struct pci_dev *dev);
125 : extern const struct attribute_group pci_dev_vpd_attr_group;
126 :
127 : /* PCI Virtual Channel */
128 : int pci_save_vc_state(struct pci_dev *dev);
129 : void pci_restore_vc_state(struct pci_dev *dev);
130 : void pci_allocate_vc_save_buffers(struct pci_dev *dev);
131 :
132 : /* PCI /proc functions */
133 : #ifdef CONFIG_PROC_FS
134 : int pci_proc_attach_device(struct pci_dev *dev);
135 : int pci_proc_detach_device(struct pci_dev *dev);
136 : int pci_proc_detach_bus(struct pci_bus *bus);
137 : #else
138 : static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
139 : static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
140 : static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
141 : #endif
142 :
143 : /* Functions for PCI Hotplug drivers to use */
144 : int pci_hp_add_bridge(struct pci_dev *dev);
145 :
146 : #ifdef HAVE_PCI_LEGACY
147 : void pci_create_legacy_files(struct pci_bus *bus);
148 : void pci_remove_legacy_files(struct pci_bus *bus);
149 : #else
150 : static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
151 : static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
152 : #endif
153 :
154 : /* Lock for read/write access to pci device and bus lists */
155 : extern struct rw_semaphore pci_bus_sem;
156 : extern struct mutex pci_slot_mutex;
157 :
158 : extern raw_spinlock_t pci_lock;
159 :
160 : extern unsigned int pci_pm_d3hot_delay;
161 :
162 : #ifdef CONFIG_PCI_MSI
163 : void pci_no_msi(void);
164 : #else
165 : static inline void pci_no_msi(void) { }
166 : #endif
167 :
168 : void pci_realloc_get_opt(char *);
169 :
170 : static inline int pci_no_d1d2(struct pci_dev *dev)
171 : {
172 0 : unsigned int parent_dstates = 0;
173 :
174 0 : if (dev->bus->self)
175 0 : parent_dstates = dev->bus->self->no_d1d2;
176 0 : return (dev->no_d1d2 || parent_dstates);
177 :
178 : }
179 : extern const struct attribute_group *pci_dev_groups[];
180 : extern const struct attribute_group *pcibus_groups[];
181 : extern const struct device_type pci_dev_type;
182 : extern const struct attribute_group *pci_bus_groups[];
183 :
184 : extern unsigned long pci_hotplug_io_size;
185 : extern unsigned long pci_hotplug_mmio_size;
186 : extern unsigned long pci_hotplug_mmio_pref_size;
187 : extern unsigned long pci_hotplug_bus_size;
188 :
189 : /**
190 : * pci_match_one_device - Tell if a PCI device structure has a matching
191 : * PCI device id structure
192 : * @id: single PCI device id structure to match
193 : * @dev: the PCI device structure to match against
194 : *
195 : * Returns the matching pci_device_id structure or %NULL if there is no match.
196 : */
197 : static inline const struct pci_device_id *
198 0 : pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
199 : {
200 0 : if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
201 0 : (id->device == PCI_ANY_ID || id->device == dev->device) &&
202 0 : (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
203 0 : (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
204 0 : !((id->class ^ dev->class) & id->class_mask))
205 : return id;
206 0 : return NULL;
207 : }
208 :
209 : /* PCI slot sysfs helper code */
210 : #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
211 :
212 : extern struct kset *pci_slots_kset;
213 :
214 : struct pci_slot_attribute {
215 : struct attribute attr;
216 : ssize_t (*show)(struct pci_slot *, char *);
217 : ssize_t (*store)(struct pci_slot *, const char *, size_t);
218 : };
219 : #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
220 :
221 : enum pci_bar_type {
222 : pci_bar_unknown, /* Standard PCI BAR probe */
223 : pci_bar_io, /* An I/O port BAR */
224 : pci_bar_mem32, /* A 32-bit memory BAR */
225 : pci_bar_mem64, /* A 64-bit memory BAR */
226 : };
227 :
228 : struct device *pci_get_host_bridge_device(struct pci_dev *dev);
229 : void pci_put_host_bridge_device(struct device *dev);
230 :
231 : int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
232 : bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
233 : int crs_timeout);
234 : bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
235 : int crs_timeout);
236 : int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
237 :
238 : int pci_setup_device(struct pci_dev *dev);
239 : int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
240 : struct resource *res, unsigned int reg);
241 : void pci_configure_ari(struct pci_dev *dev);
242 : void __pci_bus_size_bridges(struct pci_bus *bus,
243 : struct list_head *realloc_head);
244 : void __pci_bus_assign_resources(const struct pci_bus *bus,
245 : struct list_head *realloc_head,
246 : struct list_head *fail_head);
247 : bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
248 :
249 : void pci_reassigndev_resource_alignment(struct pci_dev *dev);
250 : void pci_disable_bridge_window(struct pci_dev *dev);
251 : struct pci_bus *pci_bus_get(struct pci_bus *bus);
252 : void pci_bus_put(struct pci_bus *bus);
253 :
254 : /* PCIe link information from Link Capabilities 2 */
255 : #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
256 : ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
257 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
258 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
259 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
260 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
261 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
262 : PCI_SPEED_UNKNOWN)
263 :
264 : /* PCIe speed to Mb/s reduced by encoding overhead */
265 : #define PCIE_SPEED2MBS_ENC(speed) \
266 : ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
267 : (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
268 : (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
269 : (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
270 : (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
271 : (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
272 : 0)
273 :
274 : const char *pci_speed_string(enum pci_bus_speed speed);
275 : enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
276 : enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
277 : u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
278 : enum pcie_link_width *width);
279 : void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
280 : void pcie_report_downtraining(struct pci_dev *dev);
281 : void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
282 :
283 : /* Single Root I/O Virtualization */
284 : struct pci_sriov {
285 : int pos; /* Capability position */
286 : int nres; /* Number of resources */
287 : u32 cap; /* SR-IOV Capabilities */
288 : u16 ctrl; /* SR-IOV Control */
289 : u16 total_VFs; /* Total VFs associated with the PF */
290 : u16 initial_VFs; /* Initial VFs associated with the PF */
291 : u16 num_VFs; /* Number of VFs available */
292 : u16 offset; /* First VF Routing ID offset */
293 : u16 stride; /* Following VF stride */
294 : u16 vf_device; /* VF device ID */
295 : u32 pgsz; /* Page size for BAR alignment */
296 : u8 link; /* Function Dependency Link */
297 : u8 max_VF_buses; /* Max buses consumed by VFs */
298 : u16 driver_max_VFs; /* Max num VFs driver supports */
299 : struct pci_dev *dev; /* Lowest numbered PF */
300 : struct pci_dev *self; /* This PF */
301 : u32 class; /* VF device */
302 : u8 hdr_type; /* VF header type */
303 : u16 subsystem_vendor; /* VF subsystem vendor */
304 : u16 subsystem_device; /* VF subsystem device */
305 : resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
306 : bool drivers_autoprobe; /* Auto probing of VFs by driver */
307 : };
308 :
309 : #ifdef CONFIG_PCI_DOE
310 : void pci_doe_init(struct pci_dev *pdev);
311 : void pci_doe_destroy(struct pci_dev *pdev);
312 : void pci_doe_disconnected(struct pci_dev *pdev);
313 : #else
314 : static inline void pci_doe_init(struct pci_dev *pdev) { }
315 : static inline void pci_doe_destroy(struct pci_dev *pdev) { }
316 : static inline void pci_doe_disconnected(struct pci_dev *pdev) { }
317 : #endif
318 :
319 : /**
320 : * pci_dev_set_io_state - Set the new error state if possible.
321 : *
322 : * @dev: PCI device to set new error_state
323 : * @new: the state we want dev to be in
324 : *
325 : * If the device is experiencing perm_failure, it has to remain in that state.
326 : * Any other transition is allowed.
327 : *
328 : * Returns true if state has been changed to the requested state.
329 : */
330 : static inline bool pci_dev_set_io_state(struct pci_dev *dev,
331 : pci_channel_state_t new)
332 : {
333 : pci_channel_state_t old;
334 :
335 : switch (new) {
336 : case pci_channel_io_perm_failure:
337 : xchg(&dev->error_state, pci_channel_io_perm_failure);
338 : return true;
339 : case pci_channel_io_frozen:
340 : old = cmpxchg(&dev->error_state, pci_channel_io_normal,
341 : pci_channel_io_frozen);
342 : return old != pci_channel_io_perm_failure;
343 : case pci_channel_io_normal:
344 : old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
345 : pci_channel_io_normal);
346 : return old != pci_channel_io_perm_failure;
347 : default:
348 : return false;
349 : }
350 : }
351 :
352 : static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
353 : {
354 : pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
355 : pci_doe_disconnected(dev);
356 :
357 : return 0;
358 : }
359 :
360 : static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
361 : {
362 : return dev->error_state == pci_channel_io_perm_failure;
363 : }
364 :
365 : /* pci_dev priv_flags */
366 : #define PCI_DEV_ADDED 0
367 : #define PCI_DPC_RECOVERED 1
368 : #define PCI_DPC_RECOVERING 2
369 :
370 : static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
371 : {
372 0 : assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
373 : }
374 :
375 : static inline bool pci_dev_is_added(const struct pci_dev *dev)
376 : {
377 0 : return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
378 : }
379 :
380 : #ifdef CONFIG_PCIEAER
381 : #include <linux/aer.h>
382 :
383 : #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
384 :
385 : struct aer_err_info {
386 : struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
387 : int error_dev_num;
388 :
389 : unsigned int id:16;
390 :
391 : unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
392 : unsigned int __pad1:5;
393 : unsigned int multi_error_valid:1;
394 :
395 : unsigned int first_error:5;
396 : unsigned int __pad2:2;
397 : unsigned int tlp_header_valid:1;
398 :
399 : unsigned int status; /* COR/UNCOR Error Status */
400 : unsigned int mask; /* COR/UNCOR Error Mask */
401 : struct aer_header_log_regs tlp; /* TLP Header */
402 : };
403 :
404 : int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
405 : void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
406 : #endif /* CONFIG_PCIEAER */
407 :
408 : #ifdef CONFIG_PCIEPORTBUS
409 : /* Cached RCEC Endpoint Association */
410 : struct rcec_ea {
411 : u8 nextbusn;
412 : u8 lastbusn;
413 : u32 bitmap;
414 : };
415 : #endif
416 :
417 : #ifdef CONFIG_PCIE_DPC
418 : void pci_save_dpc_state(struct pci_dev *dev);
419 : void pci_restore_dpc_state(struct pci_dev *dev);
420 : void pci_dpc_init(struct pci_dev *pdev);
421 : void dpc_process_error(struct pci_dev *pdev);
422 : pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
423 : bool pci_dpc_recovered(struct pci_dev *pdev);
424 : #else
425 : static inline void pci_save_dpc_state(struct pci_dev *dev) {}
426 : static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
427 : static inline void pci_dpc_init(struct pci_dev *pdev) {}
428 : static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
429 : #endif
430 :
431 : #ifdef CONFIG_PCIEPORTBUS
432 : void pci_rcec_init(struct pci_dev *dev);
433 : void pci_rcec_exit(struct pci_dev *dev);
434 : void pcie_link_rcec(struct pci_dev *rcec);
435 : void pcie_walk_rcec(struct pci_dev *rcec,
436 : int (*cb)(struct pci_dev *, void *),
437 : void *userdata);
438 : #else
439 : static inline void pci_rcec_init(struct pci_dev *dev) {}
440 : static inline void pci_rcec_exit(struct pci_dev *dev) {}
441 : static inline void pcie_link_rcec(struct pci_dev *rcec) {}
442 : static inline void pcie_walk_rcec(struct pci_dev *rcec,
443 : int (*cb)(struct pci_dev *, void *),
444 : void *userdata) {}
445 : #endif
446 :
447 : #ifdef CONFIG_PCI_ATS
448 : /* Address Translation Service */
449 : void pci_ats_init(struct pci_dev *dev);
450 : void pci_restore_ats_state(struct pci_dev *dev);
451 : #else
452 : static inline void pci_ats_init(struct pci_dev *d) { }
453 : static inline void pci_restore_ats_state(struct pci_dev *dev) { }
454 : #endif /* CONFIG_PCI_ATS */
455 :
456 : #ifdef CONFIG_PCI_PRI
457 : void pci_pri_init(struct pci_dev *dev);
458 : void pci_restore_pri_state(struct pci_dev *pdev);
459 : #else
460 : static inline void pci_pri_init(struct pci_dev *dev) { }
461 : static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
462 : #endif
463 :
464 : #ifdef CONFIG_PCI_PASID
465 : void pci_pasid_init(struct pci_dev *dev);
466 : void pci_restore_pasid_state(struct pci_dev *pdev);
467 : #else
468 : static inline void pci_pasid_init(struct pci_dev *dev) { }
469 : static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
470 : #endif
471 :
472 : #ifdef CONFIG_PCI_IOV
473 : int pci_iov_init(struct pci_dev *dev);
474 : void pci_iov_release(struct pci_dev *dev);
475 : void pci_iov_remove(struct pci_dev *dev);
476 : void pci_iov_update_resource(struct pci_dev *dev, int resno);
477 : resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
478 : void pci_restore_iov_state(struct pci_dev *dev);
479 : int pci_iov_bus_range(struct pci_bus *bus);
480 : extern const struct attribute_group sriov_pf_dev_attr_group;
481 : extern const struct attribute_group sriov_vf_dev_attr_group;
482 : #else
483 : static inline int pci_iov_init(struct pci_dev *dev)
484 : {
485 : return -ENODEV;
486 : }
487 : static inline void pci_iov_release(struct pci_dev *dev)
488 :
489 : {
490 : }
491 : static inline void pci_iov_remove(struct pci_dev *dev)
492 : {
493 : }
494 : static inline void pci_restore_iov_state(struct pci_dev *dev)
495 : {
496 : }
497 : static inline int pci_iov_bus_range(struct pci_bus *bus)
498 : {
499 : return 0;
500 : }
501 :
502 : #endif /* CONFIG_PCI_IOV */
503 :
504 : #ifdef CONFIG_PCIE_PTM
505 : void pci_ptm_init(struct pci_dev *dev);
506 : void pci_save_ptm_state(struct pci_dev *dev);
507 : void pci_restore_ptm_state(struct pci_dev *dev);
508 : void pci_suspend_ptm(struct pci_dev *dev);
509 : void pci_resume_ptm(struct pci_dev *dev);
510 : #else
511 : static inline void pci_ptm_init(struct pci_dev *dev) { }
512 : static inline void pci_save_ptm_state(struct pci_dev *dev) { }
513 : static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
514 : static inline void pci_suspend_ptm(struct pci_dev *dev) { }
515 : static inline void pci_resume_ptm(struct pci_dev *dev) { }
516 : #endif
517 :
518 : unsigned long pci_cardbus_resource_alignment(struct resource *);
519 :
520 0 : static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
521 : struct resource *res)
522 : {
523 : #ifdef CONFIG_PCI_IOV
524 : int resno = res - dev->resource;
525 :
526 : if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
527 : return pci_sriov_resource_alignment(dev, resno);
528 : #endif
529 0 : if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
530 0 : return pci_cardbus_resource_alignment(res);
531 0 : return resource_alignment(res);
532 : }
533 :
534 : void pci_acs_init(struct pci_dev *dev);
535 : #ifdef CONFIG_PCI_QUIRKS
536 : int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
537 : int pci_dev_specific_enable_acs(struct pci_dev *dev);
538 : int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
539 : bool pcie_failed_link_retrain(struct pci_dev *dev);
540 : #else
541 : static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
542 : u16 acs_flags)
543 : {
544 : return -ENOTTY;
545 : }
546 : static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
547 : {
548 : return -ENOTTY;
549 : }
550 : static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
551 : {
552 : return -ENOTTY;
553 : }
554 : static inline bool pcie_failed_link_retrain(struct pci_dev *dev)
555 : {
556 : return false;
557 : }
558 : #endif
559 :
560 : /* PCI error reporting and recovery */
561 : pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
562 : pci_channel_state_t state,
563 : pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
564 :
565 : bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
566 : int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
567 : #ifdef CONFIG_PCIEASPM
568 : void pcie_aspm_init_link_state(struct pci_dev *pdev);
569 : void pcie_aspm_exit_link_state(struct pci_dev *pdev);
570 : void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
571 : #else
572 : static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
573 : static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
574 : static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
575 : #endif
576 :
577 : #ifdef CONFIG_PCIE_ECRC
578 : void pcie_set_ecrc_checking(struct pci_dev *dev);
579 : void pcie_ecrc_get_policy(char *str);
580 : #else
581 : static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
582 : static inline void pcie_ecrc_get_policy(char *str) { }
583 : #endif
584 :
585 : struct pci_dev_reset_methods {
586 : u16 vendor;
587 : u16 device;
588 : int (*reset)(struct pci_dev *dev, bool probe);
589 : };
590 :
591 : struct pci_reset_fn_method {
592 : int (*reset_fn)(struct pci_dev *pdev, bool probe);
593 : char *name;
594 : };
595 :
596 : #ifdef CONFIG_PCI_QUIRKS
597 : int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
598 : #else
599 : static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
600 : {
601 : return -ENOTTY;
602 : }
603 : #endif
604 :
605 : #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
606 : int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
607 : struct resource *res);
608 : #else
609 : static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
610 : u16 segment, struct resource *res)
611 : {
612 : return -ENODEV;
613 : }
614 : #endif
615 :
616 : int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
617 : int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
618 : static inline u64 pci_rebar_size_to_bytes(int size)
619 : {
620 0 : return 1ULL << (size + 20);
621 : }
622 :
623 : struct device_node;
624 :
625 : #ifdef CONFIG_OF
626 : int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
627 : int of_get_pci_domain_nr(struct device_node *node);
628 : int of_pci_get_max_link_speed(struct device_node *node);
629 : u32 of_pci_get_slot_power_limit(struct device_node *node,
630 : u8 *slot_power_limit_value,
631 : u8 *slot_power_limit_scale);
632 : int pci_set_of_node(struct pci_dev *dev);
633 : void pci_release_of_node(struct pci_dev *dev);
634 : void pci_set_bus_of_node(struct pci_bus *bus);
635 : void pci_release_bus_of_node(struct pci_bus *bus);
636 :
637 : int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
638 :
639 : #else
640 : static inline int
641 : of_pci_parse_bus_range(struct device_node *node, struct resource *res)
642 : {
643 : return -EINVAL;
644 : }
645 :
646 : static inline int
647 : of_get_pci_domain_nr(struct device_node *node)
648 : {
649 : return -1;
650 : }
651 :
652 : static inline int
653 : of_pci_get_max_link_speed(struct device_node *node)
654 : {
655 : return -EINVAL;
656 : }
657 :
658 : static inline u32
659 : of_pci_get_slot_power_limit(struct device_node *node,
660 : u8 *slot_power_limit_value,
661 : u8 *slot_power_limit_scale)
662 : {
663 : if (slot_power_limit_value)
664 : *slot_power_limit_value = 0;
665 : if (slot_power_limit_scale)
666 : *slot_power_limit_scale = 0;
667 : return 0;
668 : }
669 :
670 : static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
671 : static inline void pci_release_of_node(struct pci_dev *dev) { }
672 : static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
673 : static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
674 :
675 : static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
676 : {
677 : return 0;
678 : }
679 :
680 : #endif /* CONFIG_OF */
681 :
682 : #ifdef CONFIG_PCIEAER
683 : void pci_no_aer(void);
684 : void pci_aer_init(struct pci_dev *dev);
685 : void pci_aer_exit(struct pci_dev *dev);
686 : extern const struct attribute_group aer_stats_attr_group;
687 : void pci_aer_clear_fatal_status(struct pci_dev *dev);
688 : int pci_aer_clear_status(struct pci_dev *dev);
689 : int pci_aer_raw_clear_status(struct pci_dev *dev);
690 : void pci_save_aer_state(struct pci_dev *dev);
691 : void pci_restore_aer_state(struct pci_dev *dev);
692 : #else
693 : static inline void pci_no_aer(void) { }
694 : static inline void pci_aer_init(struct pci_dev *d) { }
695 : static inline void pci_aer_exit(struct pci_dev *d) { }
696 : static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
697 : static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
698 : static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
699 : static inline void pci_save_aer_state(struct pci_dev *dev) { }
700 : static inline void pci_restore_aer_state(struct pci_dev *dev) { }
701 : #endif
702 :
703 : #ifdef CONFIG_ACPI
704 : int pci_acpi_program_hp_params(struct pci_dev *dev);
705 : extern const struct attribute_group pci_dev_acpi_attr_group;
706 : void pci_set_acpi_fwnode(struct pci_dev *dev);
707 : int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
708 : bool acpi_pci_power_manageable(struct pci_dev *dev);
709 : bool acpi_pci_bridge_d3(struct pci_dev *dev);
710 : int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
711 : pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
712 : void acpi_pci_refresh_power_state(struct pci_dev *dev);
713 : int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
714 : bool acpi_pci_need_resume(struct pci_dev *dev);
715 : pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
716 : #else
717 0 : static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
718 : {
719 0 : return -ENOTTY;
720 : }
721 : static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {}
722 : static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
723 : {
724 : return -ENODEV;
725 : }
726 : static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
727 : {
728 : return false;
729 : }
730 : static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
731 : {
732 : return false;
733 : }
734 : static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
735 : {
736 : return -ENODEV;
737 : }
738 : static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
739 : {
740 : return PCI_UNKNOWN;
741 : }
742 : static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) {}
743 : static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
744 : {
745 : return -ENODEV;
746 : }
747 : static inline bool acpi_pci_need_resume(struct pci_dev *dev)
748 : {
749 : return false;
750 : }
751 : static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
752 : {
753 : return PCI_POWER_ERROR;
754 : }
755 : #endif
756 :
757 : #ifdef CONFIG_PCIEASPM
758 : extern const struct attribute_group aspm_ctrl_attr_group;
759 : #endif
760 :
761 : extern const struct attribute_group pci_dev_reset_method_attr_group;
762 :
763 : #ifdef CONFIG_X86_INTEL_MID
764 : bool pci_use_mid_pm(void);
765 : int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
766 : pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
767 : #else
768 : static inline bool pci_use_mid_pm(void)
769 : {
770 : return false;
771 : }
772 : static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
773 : {
774 : return -ENODEV;
775 : }
776 : static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
777 : {
778 : return PCI_UNKNOWN;
779 : }
780 : #endif
781 :
782 : /*
783 : * Config Address for PCI Configuration Mechanism #1
784 : *
785 : * See PCI Local Bus Specification, Revision 3.0,
786 : * Section 3.2.2.3.2, Figure 3-2, p. 50.
787 : */
788 :
789 : #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
790 : #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
791 : #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
792 :
793 : #define PCI_CONF1_BUS_MASK 0xff
794 : #define PCI_CONF1_DEV_MASK 0x1f
795 : #define PCI_CONF1_FUNC_MASK 0x7
796 : #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
797 :
798 : #define PCI_CONF1_ENABLE BIT(31)
799 : #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
800 : #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
801 : #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
802 : #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
803 :
804 : #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
805 : (PCI_CONF1_ENABLE | \
806 : PCI_CONF1_BUS(bus) | \
807 : PCI_CONF1_DEV(dev) | \
808 : PCI_CONF1_FUNC(func) | \
809 : PCI_CONF1_REG(reg))
810 :
811 : /*
812 : * Extension of PCI Config Address for accessing extended PCIe registers
813 : *
814 : * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
815 : * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
816 : * are used for specifying additional 4 high bits of PCI Express register.
817 : */
818 :
819 : #define PCI_CONF1_EXT_REG_SHIFT 16
820 : #define PCI_CONF1_EXT_REG_MASK 0xf00
821 : #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
822 :
823 : #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
824 : (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
825 : PCI_CONF1_EXT_REG(reg))
826 :
827 : #endif /* DRIVERS_PCI_H */
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