Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0
2 : /*
3 : * Enable PCIe link L0s/L1 state and Clock Power Management
4 : *
5 : * Copyright (C) 2007 Intel
6 : * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 : * Copyright (C) Shaohua Li (shaohua.li@intel.com)
8 : */
9 :
10 : #include <linux/kernel.h>
11 : #include <linux/math.h>
12 : #include <linux/module.h>
13 : #include <linux/moduleparam.h>
14 : #include <linux/pci.h>
15 : #include <linux/pci_regs.h>
16 : #include <linux/errno.h>
17 : #include <linux/pm.h>
18 : #include <linux/init.h>
19 : #include <linux/slab.h>
20 : #include <linux/jiffies.h>
21 : #include <linux/delay.h>
22 : #include "../pci.h"
23 :
24 : #ifdef MODULE_PARAM_PREFIX
25 : #undef MODULE_PARAM_PREFIX
26 : #endif
27 : #define MODULE_PARAM_PREFIX "pcie_aspm."
28 :
29 : /* Note: those are not register definitions */
30 : #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31 : #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32 : #define ASPM_STATE_L1 (4) /* L1 state */
33 : #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
34 : #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
35 : #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
36 : #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
37 : #define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
38 : #define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
39 : #define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
40 : ASPM_STATE_L1_2_MASK)
41 : #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
42 : #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
43 : ASPM_STATE_L1SS)
44 :
45 : struct pcie_link_state {
46 : struct pci_dev *pdev; /* Upstream component of the Link */
47 : struct pci_dev *downstream; /* Downstream component, function 0 */
48 : struct pcie_link_state *root; /* pointer to the root port link */
49 : struct pcie_link_state *parent; /* pointer to the parent Link state */
50 : struct list_head sibling; /* node in link_list */
51 :
52 : /* ASPM state */
53 : u32 aspm_support:7; /* Supported ASPM state */
54 : u32 aspm_enabled:7; /* Enabled ASPM state */
55 : u32 aspm_capable:7; /* Capable ASPM state with latency */
56 : u32 aspm_default:7; /* Default ASPM state by BIOS */
57 : u32 aspm_disable:7; /* Disabled ASPM state */
58 :
59 : /* Clock PM state */
60 : u32 clkpm_capable:1; /* Clock PM capable? */
61 : u32 clkpm_enabled:1; /* Current Clock PM state */
62 : u32 clkpm_default:1; /* Default Clock PM state by BIOS */
63 : u32 clkpm_disable:1; /* Clock PM disabled */
64 : };
65 :
66 : static int aspm_disabled, aspm_force;
67 : static bool aspm_support_enabled = true;
68 : static DEFINE_MUTEX(aspm_lock);
69 : static LIST_HEAD(link_list);
70 :
71 : #define POLICY_DEFAULT 0 /* BIOS default setting */
72 : #define POLICY_PERFORMANCE 1 /* high performance */
73 : #define POLICY_POWERSAVE 2 /* high power saving */
74 : #define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
75 :
76 : #ifdef CONFIG_PCIEASPM_PERFORMANCE
77 : static int aspm_policy = POLICY_PERFORMANCE;
78 : #elif defined CONFIG_PCIEASPM_POWERSAVE
79 : static int aspm_policy = POLICY_POWERSAVE;
80 : #elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
81 : static int aspm_policy = POLICY_POWER_SUPERSAVE;
82 : #else
83 : static int aspm_policy;
84 : #endif
85 :
86 : static const char *policy_str[] = {
87 : [POLICY_DEFAULT] = "default",
88 : [POLICY_PERFORMANCE] = "performance",
89 : [POLICY_POWERSAVE] = "powersave",
90 : [POLICY_POWER_SUPERSAVE] = "powersupersave"
91 : };
92 :
93 : /*
94 : * The L1 PM substate capability is only implemented in function 0 in a
95 : * multi function device.
96 : */
97 : static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
98 : {
99 : struct pci_dev *child;
100 :
101 0 : list_for_each_entry(child, &linkbus->devices, bus_list)
102 0 : if (PCI_FUNC(child->devfn) == 0)
103 : return child;
104 : return NULL;
105 : }
106 :
107 : static int policy_to_aspm_state(struct pcie_link_state *link)
108 : {
109 0 : switch (aspm_policy) {
110 : case POLICY_PERFORMANCE:
111 : /* Disable ASPM and Clock PM */
112 : return 0;
113 : case POLICY_POWERSAVE:
114 : /* Enable ASPM L0s/L1 */
115 : return (ASPM_STATE_L0S | ASPM_STATE_L1);
116 : case POLICY_POWER_SUPERSAVE:
117 : /* Enable Everything */
118 : return ASPM_STATE_ALL;
119 : case POLICY_DEFAULT:
120 0 : return link->aspm_default;
121 : }
122 : return 0;
123 : }
124 :
125 : static int policy_to_clkpm_state(struct pcie_link_state *link)
126 : {
127 0 : switch (aspm_policy) {
128 : case POLICY_PERFORMANCE:
129 : /* Disable ASPM and Clock PM */
130 : return 0;
131 : case POLICY_POWERSAVE:
132 : case POLICY_POWER_SUPERSAVE:
133 : /* Enable Clock PM */
134 : return 1;
135 : case POLICY_DEFAULT:
136 0 : return link->clkpm_default;
137 : }
138 : return 0;
139 : }
140 :
141 0 : static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
142 : {
143 : struct pci_dev *child;
144 0 : struct pci_bus *linkbus = link->pdev->subordinate;
145 0 : u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
146 :
147 0 : list_for_each_entry(child, &linkbus->devices, bus_list)
148 0 : pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
149 : PCI_EXP_LNKCTL_CLKREQ_EN,
150 : val);
151 0 : link->clkpm_enabled = !!enable;
152 0 : }
153 :
154 : static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
155 : {
156 : /*
157 : * Don't enable Clock PM if the link is not Clock PM capable
158 : * or Clock PM is disabled
159 : */
160 0 : if (!link->clkpm_capable || link->clkpm_disable)
161 0 : enable = 0;
162 : /* Need nothing if the specified equals to current state */
163 0 : if (link->clkpm_enabled == enable)
164 : return;
165 0 : pcie_set_clkpm_nocheck(link, enable);
166 : }
167 :
168 0 : static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
169 : {
170 0 : int capable = 1, enabled = 1;
171 : u32 reg32;
172 : u16 reg16;
173 : struct pci_dev *child;
174 0 : struct pci_bus *linkbus = link->pdev->subordinate;
175 :
176 : /* All functions should have the same cap and state, take the worst */
177 0 : list_for_each_entry(child, &linkbus->devices, bus_list) {
178 0 : pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
179 0 : if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
180 : capable = 0;
181 : enabled = 0;
182 : break;
183 : }
184 0 : pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
185 0 : if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
186 0 : enabled = 0;
187 : }
188 0 : link->clkpm_enabled = enabled;
189 0 : link->clkpm_default = enabled;
190 0 : link->clkpm_capable = capable;
191 0 : link->clkpm_disable = blacklist ? 1 : 0;
192 0 : }
193 :
194 : /*
195 : * pcie_aspm_configure_common_clock: check if the 2 ends of a link
196 : * could use common clock. If they are, configure them to use the
197 : * common clock. That will reduce the ASPM state exit latency.
198 : */
199 0 : static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
200 : {
201 0 : int same_clock = 1;
202 : u16 reg16, parent_reg, child_reg[8];
203 0 : struct pci_dev *child, *parent = link->pdev;
204 0 : struct pci_bus *linkbus = parent->subordinate;
205 : /*
206 : * All functions of a slot should have the same Slot Clock
207 : * Configuration, so just check one function
208 : */
209 0 : child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
210 0 : BUG_ON(!pci_is_pcie(child));
211 :
212 : /* Check downstream component if bit Slot Clock Configuration is 1 */
213 0 : pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
214 0 : if (!(reg16 & PCI_EXP_LNKSTA_SLC))
215 0 : same_clock = 0;
216 :
217 : /* Check upstream component if bit Slot Clock Configuration is 1 */
218 0 : pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
219 0 : if (!(reg16 & PCI_EXP_LNKSTA_SLC))
220 0 : same_clock = 0;
221 :
222 : /* Port might be already in common clock mode */
223 0 : pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
224 0 : if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
225 0 : bool consistent = true;
226 :
227 0 : list_for_each_entry(child, &linkbus->devices, bus_list) {
228 0 : pcie_capability_read_word(child, PCI_EXP_LNKCTL,
229 : ®16);
230 0 : if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
231 : consistent = false;
232 : break;
233 : }
234 : }
235 0 : if (consistent)
236 0 : return;
237 0 : pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n");
238 : }
239 :
240 : /* Configure downstream component, all functions */
241 0 : list_for_each_entry(child, &linkbus->devices, bus_list) {
242 0 : pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
243 0 : child_reg[PCI_FUNC(child->devfn)] = reg16;
244 0 : if (same_clock)
245 0 : reg16 |= PCI_EXP_LNKCTL_CCC;
246 : else
247 0 : reg16 &= ~PCI_EXP_LNKCTL_CCC;
248 0 : pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
249 : }
250 :
251 : /* Configure upstream component */
252 0 : pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
253 0 : parent_reg = reg16;
254 0 : if (same_clock)
255 0 : reg16 |= PCI_EXP_LNKCTL_CCC;
256 : else
257 0 : reg16 &= ~PCI_EXP_LNKCTL_CCC;
258 0 : pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
259 :
260 0 : if (pcie_retrain_link(link->pdev, true)) {
261 :
262 : /* Training failed. Restore common clock configurations */
263 0 : pci_err(parent, "ASPM: Could not configure common clock\n");
264 0 : list_for_each_entry(child, &linkbus->devices, bus_list)
265 0 : pcie_capability_write_word(child, PCI_EXP_LNKCTL,
266 0 : child_reg[PCI_FUNC(child->devfn)]);
267 0 : pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
268 : }
269 : }
270 :
271 : /* Convert L0s latency encoding to ns */
272 : static u32 calc_l0s_latency(u32 lnkcap)
273 : {
274 0 : u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
275 :
276 0 : if (encoding == 0x7)
277 : return (5 * 1000); /* > 4us */
278 0 : return (64 << encoding);
279 : }
280 :
281 : /* Convert L0s acceptable latency encoding to ns */
282 : static u32 calc_l0s_acceptable(u32 encoding)
283 : {
284 0 : if (encoding == 0x7)
285 : return -1U;
286 0 : return (64 << encoding);
287 : }
288 :
289 : /* Convert L1 latency encoding to ns */
290 : static u32 calc_l1_latency(u32 lnkcap)
291 : {
292 0 : u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
293 :
294 0 : if (encoding == 0x7)
295 : return (65 * 1000); /* > 64us */
296 0 : return (1000 << encoding);
297 : }
298 :
299 : /* Convert L1 acceptable latency encoding to ns */
300 : static u32 calc_l1_acceptable(u32 encoding)
301 : {
302 0 : if (encoding == 0x7)
303 : return -1U;
304 0 : return (1000 << encoding);
305 : }
306 :
307 : /* Convert L1SS T_pwr encoding to usec */
308 0 : static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val)
309 : {
310 0 : switch (scale) {
311 : case 0:
312 0 : return val * 2;
313 : case 1:
314 0 : return val * 10;
315 : case 2:
316 0 : return val * 100;
317 : }
318 0 : pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
319 0 : return 0;
320 : }
321 :
322 : /*
323 : * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1
324 : * register. Ports enter L1.2 when the most recent LTR value is greater
325 : * than or equal to LTR_L1.2_THRESHOLD, so we round up to make sure we
326 : * don't enter L1.2 too aggressively.
327 : *
328 : * See PCIe r6.0, sec 5.5.1, 6.18, 7.8.3.3.
329 : */
330 0 : static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
331 : {
332 0 : u64 threshold_ns = (u64) threshold_us * 1000;
333 :
334 : /*
335 : * LTR_L1.2_THRESHOLD_Value ("value") is a 10-bit field with max
336 : * value of 0x3ff.
337 : */
338 0 : if (threshold_ns <= 0x3ff * 1) {
339 0 : *scale = 0; /* Value times 1ns */
340 0 : *value = threshold_ns;
341 0 : } else if (threshold_ns <= 0x3ff * 32) {
342 0 : *scale = 1; /* Value times 32ns */
343 0 : *value = roundup(threshold_ns, 32) / 32;
344 0 : } else if (threshold_ns <= 0x3ff * 1024) {
345 0 : *scale = 2; /* Value times 1024ns */
346 0 : *value = roundup(threshold_ns, 1024) / 1024;
347 0 : } else if (threshold_ns <= 0x3ff * 32768) {
348 0 : *scale = 3; /* Value times 32768ns */
349 0 : *value = roundup(threshold_ns, 32768) / 32768;
350 0 : } else if (threshold_ns <= 0x3ff * 1048576) {
351 0 : *scale = 4; /* Value times 1048576ns */
352 0 : *value = roundup(threshold_ns, 1048576) / 1048576;
353 0 : } else if (threshold_ns <= 0x3ff * (u64) 33554432) {
354 0 : *scale = 5; /* Value times 33554432ns */
355 0 : *value = roundup(threshold_ns, 33554432) / 33554432;
356 : } else {
357 0 : *scale = 5;
358 0 : *value = 0x3ff; /* Max representable value */
359 : }
360 0 : }
361 :
362 0 : static void pcie_aspm_check_latency(struct pci_dev *endpoint)
363 : {
364 : u32 latency, encoding, lnkcap_up, lnkcap_dw;
365 0 : u32 l1_switch_latency = 0, latency_up_l0s;
366 : u32 latency_up_l1, latency_dw_l0s, latency_dw_l1;
367 : u32 acceptable_l0s, acceptable_l1;
368 : struct pcie_link_state *link;
369 :
370 : /* Device not in D0 doesn't need latency check */
371 0 : if ((endpoint->current_state != PCI_D0) &&
372 : (endpoint->current_state != PCI_UNKNOWN))
373 0 : return;
374 :
375 0 : link = endpoint->bus->self->link_state;
376 :
377 : /* Calculate endpoint L0s acceptable latency */
378 0 : encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L0S) >> 6;
379 0 : acceptable_l0s = calc_l0s_acceptable(encoding);
380 :
381 : /* Calculate endpoint L1 acceptable latency */
382 0 : encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L1) >> 9;
383 0 : acceptable_l1 = calc_l1_acceptable(encoding);
384 :
385 0 : while (link) {
386 0 : struct pci_dev *dev = pci_function_0(link->pdev->subordinate);
387 :
388 : /* Read direction exit latencies */
389 0 : pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP,
390 : &lnkcap_up);
391 0 : pcie_capability_read_dword(dev, PCI_EXP_LNKCAP,
392 : &lnkcap_dw);
393 0 : latency_up_l0s = calc_l0s_latency(lnkcap_up);
394 0 : latency_up_l1 = calc_l1_latency(lnkcap_up);
395 0 : latency_dw_l0s = calc_l0s_latency(lnkcap_dw);
396 0 : latency_dw_l1 = calc_l1_latency(lnkcap_dw);
397 :
398 : /* Check upstream direction L0s latency */
399 0 : if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
400 : (latency_up_l0s > acceptable_l0s))
401 0 : link->aspm_capable &= ~ASPM_STATE_L0S_UP;
402 :
403 : /* Check downstream direction L0s latency */
404 0 : if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
405 : (latency_dw_l0s > acceptable_l0s))
406 0 : link->aspm_capable &= ~ASPM_STATE_L0S_DW;
407 : /*
408 : * Check L1 latency.
409 : * Every switch on the path to root complex need 1
410 : * more microsecond for L1. Spec doesn't mention L0s.
411 : *
412 : * The exit latencies for L1 substates are not advertised
413 : * by a device. Since the spec also doesn't mention a way
414 : * to determine max latencies introduced by enabling L1
415 : * substates on the components, it is not clear how to do
416 : * a L1 substate exit latency check. We assume that the
417 : * L1 exit latencies advertised by a device include L1
418 : * substate latencies (and hence do not do any check).
419 : */
420 0 : latency = max_t(u32, latency_up_l1, latency_dw_l1);
421 0 : if ((link->aspm_capable & ASPM_STATE_L1) &&
422 0 : (latency + l1_switch_latency > acceptable_l1))
423 0 : link->aspm_capable &= ~ASPM_STATE_L1;
424 0 : l1_switch_latency += 1000;
425 :
426 0 : link = link->parent;
427 : }
428 : }
429 :
430 0 : static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
431 : u32 clear, u32 set)
432 : {
433 : u32 val;
434 :
435 0 : pci_read_config_dword(pdev, pos, &val);
436 0 : val &= ~clear;
437 0 : val |= set;
438 0 : pci_write_config_dword(pdev, pos, val);
439 0 : }
440 :
441 : /* Calculate L1.2 PM substate timing parameters */
442 0 : static void aspm_calc_l12_info(struct pcie_link_state *link,
443 : u32 parent_l1ss_cap, u32 child_l1ss_cap)
444 : {
445 0 : struct pci_dev *child = link->downstream, *parent = link->pdev;
446 : u32 val1, val2, scale1, scale2;
447 : u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
448 0 : u32 ctl1 = 0, ctl2 = 0;
449 : u32 pctl1, pctl2, cctl1, cctl2;
450 : u32 pl1_2_enables, cl1_2_enables;
451 :
452 : /* Choose the greater of the two Port Common_Mode_Restore_Times */
453 0 : val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
454 0 : val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
455 0 : t_common_mode = max(val1, val2);
456 :
457 : /* Choose the greater of the two Port T_POWER_ON times */
458 0 : val1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
459 0 : scale1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
460 0 : val2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
461 0 : scale2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
462 :
463 0 : if (calc_l12_pwron(parent, scale1, val1) >
464 0 : calc_l12_pwron(child, scale2, val2)) {
465 0 : ctl2 |= scale1 | (val1 << 3);
466 0 : t_power_on = calc_l12_pwron(parent, scale1, val1);
467 : } else {
468 0 : ctl2 |= scale2 | (val2 << 3);
469 0 : t_power_on = calc_l12_pwron(child, scale2, val2);
470 : }
471 :
472 : /*
473 : * Set LTR_L1.2_THRESHOLD to the time required to transition the
474 : * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
475 : * downstream devices report (via LTR) that they can tolerate at
476 : * least that much latency.
477 : *
478 : * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
479 : * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
480 : * least 4us.
481 : */
482 0 : l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
483 0 : encode_l12_threshold(l1_2_threshold, &scale, &value);
484 0 : ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
485 :
486 : /* Some broken devices only support dword access to L1 SS */
487 0 : pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
488 0 : pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2);
489 0 : pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1);
490 0 : pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2);
491 :
492 0 : if (ctl1 == pctl1 && ctl1 == cctl1 &&
493 0 : ctl2 == pctl2 && ctl2 == cctl2)
494 0 : return;
495 :
496 : /* Disable L1.2 while updating. See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
497 0 : pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;
498 0 : cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
499 :
500 0 : if (pl1_2_enables || cl1_2_enables) {
501 0 : pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
502 : PCI_L1SS_CTL1_L1_2_MASK, 0);
503 0 : pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
504 : PCI_L1SS_CTL1_L1_2_MASK, 0);
505 : }
506 :
507 : /* Program T_POWER_ON times in both ports */
508 0 : pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
509 0 : pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
510 :
511 : /* Program Common_Mode_Restore_Time in upstream device */
512 0 : pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
513 : PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
514 :
515 : /* Program LTR_L1.2_THRESHOLD time in both ports */
516 0 : pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
517 : PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
518 : PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
519 0 : pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
520 : PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
521 : PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
522 :
523 0 : if (pl1_2_enables || cl1_2_enables) {
524 0 : pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
525 : pl1_2_enables);
526 0 : pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,
527 : cl1_2_enables);
528 : }
529 : }
530 :
531 0 : static void aspm_l1ss_init(struct pcie_link_state *link)
532 : {
533 0 : struct pci_dev *child = link->downstream, *parent = link->pdev;
534 : u32 parent_l1ss_cap, child_l1ss_cap;
535 0 : u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;
536 :
537 0 : if (!parent->l1ss || !child->l1ss)
538 0 : return;
539 :
540 : /* Setup L1 substate */
541 0 : pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
542 : &parent_l1ss_cap);
543 0 : pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
544 : &child_l1ss_cap);
545 :
546 0 : if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
547 0 : parent_l1ss_cap = 0;
548 0 : if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
549 0 : child_l1ss_cap = 0;
550 :
551 : /*
552 : * If we don't have LTR for the entire path from the Root Complex
553 : * to this device, we can't use ASPM L1.2 because it relies on the
554 : * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18.
555 : */
556 0 : if (!child->ltr_path)
557 0 : child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
558 :
559 0 : if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
560 0 : link->aspm_support |= ASPM_STATE_L1_1;
561 0 : if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
562 0 : link->aspm_support |= ASPM_STATE_L1_2;
563 0 : if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
564 0 : link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
565 0 : if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
566 0 : link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
567 :
568 0 : if (parent_l1ss_cap)
569 0 : pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
570 : &parent_l1ss_ctl1);
571 0 : if (child_l1ss_cap)
572 0 : pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
573 : &child_l1ss_ctl1);
574 :
575 0 : if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
576 0 : link->aspm_enabled |= ASPM_STATE_L1_1;
577 0 : if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
578 0 : link->aspm_enabled |= ASPM_STATE_L1_2;
579 0 : if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
580 0 : link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
581 0 : if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
582 0 : link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
583 :
584 0 : if (link->aspm_support & ASPM_STATE_L1_2_MASK)
585 0 : aspm_calc_l12_info(link, parent_l1ss_cap, child_l1ss_cap);
586 : }
587 :
588 0 : static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
589 : {
590 0 : struct pci_dev *child = link->downstream, *parent = link->pdev;
591 : u32 parent_lnkcap, child_lnkcap;
592 : u16 parent_lnkctl, child_lnkctl;
593 0 : struct pci_bus *linkbus = parent->subordinate;
594 :
595 0 : if (blacklist) {
596 : /* Set enabled/disable so that we will disable ASPM later */
597 0 : link->aspm_enabled = ASPM_STATE_ALL;
598 0 : link->aspm_disable = ASPM_STATE_ALL;
599 0 : return;
600 : }
601 :
602 : /*
603 : * If ASPM not supported, don't mess with the clocks and link,
604 : * bail out now.
605 : */
606 0 : pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
607 0 : pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
608 0 : if (!(parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPMS))
609 : return;
610 :
611 : /* Configure common clock before checking latencies */
612 0 : pcie_aspm_configure_common_clock(link);
613 :
614 : /*
615 : * Re-read upstream/downstream components' register state after
616 : * clock configuration. L0s & L1 exit latencies in the otherwise
617 : * read-only Link Capabilities may change depending on common clock
618 : * configuration (PCIe r5.0, sec 7.5.3.6).
619 : */
620 0 : pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
621 0 : pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
622 0 : pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
623 0 : pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
624 :
625 : /*
626 : * Setup L0s state
627 : *
628 : * Note that we must not enable L0s in either direction on a
629 : * given link unless components on both sides of the link each
630 : * support L0s.
631 : */
632 0 : if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L0S)
633 0 : link->aspm_support |= ASPM_STATE_L0S;
634 :
635 0 : if (child_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
636 0 : link->aspm_enabled |= ASPM_STATE_L0S_UP;
637 0 : if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
638 0 : link->aspm_enabled |= ASPM_STATE_L0S_DW;
639 :
640 : /* Setup L1 state */
641 0 : if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
642 0 : link->aspm_support |= ASPM_STATE_L1;
643 :
644 0 : if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
645 0 : link->aspm_enabled |= ASPM_STATE_L1;
646 :
647 0 : aspm_l1ss_init(link);
648 :
649 : /* Save default state */
650 0 : link->aspm_default = link->aspm_enabled;
651 :
652 : /* Setup initial capable state. Will be updated later */
653 0 : link->aspm_capable = link->aspm_support;
654 :
655 : /* Get and check endpoint acceptable latencies */
656 0 : list_for_each_entry(child, &linkbus->devices, bus_list) {
657 0 : if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
658 0 : pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
659 0 : continue;
660 :
661 0 : pcie_aspm_check_latency(child);
662 : }
663 : }
664 :
665 : /* Configure the ASPM L1 substates */
666 0 : static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
667 : {
668 : u32 val, enable_req;
669 0 : struct pci_dev *child = link->downstream, *parent = link->pdev;
670 :
671 0 : enable_req = (link->aspm_enabled ^ state) & state;
672 :
673 : /*
674 : * Here are the rules specified in the PCIe spec for enabling L1SS:
675 : * - When enabling L1.x, enable bit at parent first, then at child
676 : * - When disabling L1.x, disable bit at child first, then at parent
677 : * - When enabling ASPM L1.x, need to disable L1
678 : * (at child followed by parent).
679 : * - The ASPM/PCIPM L1.2 must be disabled while programming timing
680 : * parameters
681 : *
682 : * To keep it simple, disable all L1SS bits first, and later enable
683 : * what is needed.
684 : */
685 :
686 : /* Disable all L1 substates */
687 0 : pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
688 : PCI_L1SS_CTL1_L1SS_MASK, 0);
689 0 : pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
690 : PCI_L1SS_CTL1_L1SS_MASK, 0);
691 : /*
692 : * If needed, disable L1, and it gets enabled later
693 : * in pcie_config_aspm_link().
694 : */
695 0 : if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
696 0 : pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
697 : PCI_EXP_LNKCTL_ASPM_L1, 0);
698 0 : pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
699 : PCI_EXP_LNKCTL_ASPM_L1, 0);
700 : }
701 :
702 0 : val = 0;
703 0 : if (state & ASPM_STATE_L1_1)
704 0 : val |= PCI_L1SS_CTL1_ASPM_L1_1;
705 0 : if (state & ASPM_STATE_L1_2)
706 0 : val |= PCI_L1SS_CTL1_ASPM_L1_2;
707 0 : if (state & ASPM_STATE_L1_1_PCIPM)
708 0 : val |= PCI_L1SS_CTL1_PCIPM_L1_1;
709 0 : if (state & ASPM_STATE_L1_2_PCIPM)
710 0 : val |= PCI_L1SS_CTL1_PCIPM_L1_2;
711 :
712 : /* Enable what we need to enable */
713 0 : pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
714 : PCI_L1SS_CTL1_L1SS_MASK, val);
715 0 : pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
716 : PCI_L1SS_CTL1_L1SS_MASK, val);
717 0 : }
718 :
719 : static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
720 : {
721 0 : pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
722 : PCI_EXP_LNKCTL_ASPMC, val);
723 : }
724 :
725 0 : static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
726 : {
727 0 : u32 upstream = 0, dwstream = 0;
728 0 : struct pci_dev *child = link->downstream, *parent = link->pdev;
729 0 : struct pci_bus *linkbus = parent->subordinate;
730 :
731 : /* Enable only the states that were not explicitly disabled */
732 0 : state &= (link->aspm_capable & ~link->aspm_disable);
733 :
734 : /* Can't enable any substates if L1 is not enabled */
735 0 : if (!(state & ASPM_STATE_L1))
736 0 : state &= ~ASPM_STATE_L1SS;
737 :
738 : /* Spec says both ports must be in D0 before enabling PCI PM substates*/
739 0 : if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
740 0 : state &= ~ASPM_STATE_L1_SS_PCIPM;
741 0 : state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
742 : }
743 :
744 : /* Nothing to do if the link is already in the requested state */
745 0 : if (link->aspm_enabled == state)
746 : return;
747 : /* Convert ASPM state to upstream/downstream ASPM register state */
748 0 : if (state & ASPM_STATE_L0S_UP)
749 0 : dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
750 0 : if (state & ASPM_STATE_L0S_DW)
751 0 : upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
752 0 : if (state & ASPM_STATE_L1) {
753 0 : upstream |= PCI_EXP_LNKCTL_ASPM_L1;
754 0 : dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
755 : }
756 :
757 0 : if (link->aspm_capable & ASPM_STATE_L1SS)
758 0 : pcie_config_aspm_l1ss(link, state);
759 :
760 : /*
761 : * Spec 2.0 suggests all functions should be configured the
762 : * same setting for ASPM. Enabling ASPM L1 should be done in
763 : * upstream component first and then downstream, and vice
764 : * versa for disabling ASPM L1. Spec doesn't mention L0S.
765 : */
766 0 : if (state & ASPM_STATE_L1)
767 : pcie_config_aspm_dev(parent, upstream);
768 0 : list_for_each_entry(child, &linkbus->devices, bus_list)
769 0 : pcie_config_aspm_dev(child, dwstream);
770 0 : if (!(state & ASPM_STATE_L1))
771 : pcie_config_aspm_dev(parent, upstream);
772 :
773 0 : link->aspm_enabled = state;
774 : }
775 :
776 0 : static void pcie_config_aspm_path(struct pcie_link_state *link)
777 : {
778 0 : while (link) {
779 0 : pcie_config_aspm_link(link, policy_to_aspm_state(link));
780 0 : link = link->parent;
781 : }
782 0 : }
783 :
784 : static void free_link_state(struct pcie_link_state *link)
785 : {
786 0 : link->pdev->link_state = NULL;
787 0 : kfree(link);
788 : }
789 :
790 0 : static int pcie_aspm_sanity_check(struct pci_dev *pdev)
791 : {
792 : struct pci_dev *child;
793 : u32 reg32;
794 :
795 : /*
796 : * Some functions in a slot might not all be PCIe functions,
797 : * very strange. Disable ASPM for the whole slot
798 : */
799 0 : list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
800 0 : if (!pci_is_pcie(child))
801 : return -EINVAL;
802 :
803 : /*
804 : * If ASPM is disabled then we're not going to change
805 : * the BIOS state. It's safe to continue even if it's a
806 : * pre-1.1 device
807 : */
808 :
809 0 : if (aspm_disabled)
810 0 : continue;
811 :
812 : /*
813 : * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
814 : * RBER bit to determine if a function is 1.1 version device
815 : */
816 0 : pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
817 0 : if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
818 0 : pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
819 : return -EINVAL;
820 : }
821 : }
822 : return 0;
823 : }
824 :
825 0 : static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
826 : {
827 : struct pcie_link_state *link;
828 :
829 0 : link = kzalloc(sizeof(*link), GFP_KERNEL);
830 0 : if (!link)
831 : return NULL;
832 :
833 0 : INIT_LIST_HEAD(&link->sibling);
834 0 : link->pdev = pdev;
835 0 : link->downstream = pci_function_0(pdev->subordinate);
836 :
837 : /*
838 : * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
839 : * hierarchies. Note that some PCIe host implementations omit
840 : * the root ports entirely, in which case a downstream port on
841 : * a switch may become the root of the link state chain for all
842 : * its subordinate endpoints.
843 : */
844 0 : if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
845 0 : pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
846 0 : !pdev->bus->parent->self) {
847 0 : link->root = link;
848 : } else {
849 : struct pcie_link_state *parent;
850 :
851 0 : parent = pdev->bus->parent->self->link_state;
852 0 : if (!parent) {
853 0 : kfree(link);
854 0 : return NULL;
855 : }
856 :
857 0 : link->parent = parent;
858 0 : link->root = link->parent->root;
859 : }
860 :
861 0 : list_add(&link->sibling, &link_list);
862 0 : pdev->link_state = link;
863 0 : return link;
864 : }
865 :
866 : static void pcie_aspm_update_sysfs_visibility(struct pci_dev *pdev)
867 : {
868 : struct pci_dev *child;
869 :
870 0 : list_for_each_entry(child, &pdev->subordinate->devices, bus_list)
871 0 : sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group);
872 : }
873 :
874 : /*
875 : * pcie_aspm_init_link_state: Initiate PCI express link state.
876 : * It is called after the pcie and its children devices are scanned.
877 : * @pdev: the root port or switch downstream port
878 : */
879 0 : void pcie_aspm_init_link_state(struct pci_dev *pdev)
880 : {
881 : struct pcie_link_state *link;
882 0 : int blacklist = !!pcie_aspm_sanity_check(pdev);
883 :
884 0 : if (!aspm_support_enabled)
885 : return;
886 :
887 0 : if (pdev->link_state)
888 : return;
889 :
890 : /*
891 : * We allocate pcie_link_state for the component on the upstream
892 : * end of a Link, so there's nothing to do unless this device is
893 : * downstream port.
894 : */
895 0 : if (!pcie_downstream_port(pdev))
896 : return;
897 :
898 : /* VIA has a strange chipset, root port is under a bridge */
899 0 : if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
900 0 : pdev->bus->self)
901 : return;
902 :
903 0 : down_read(&pci_bus_sem);
904 0 : if (list_empty(&pdev->subordinate->devices))
905 : goto out;
906 :
907 0 : mutex_lock(&aspm_lock);
908 0 : link = alloc_pcie_link_state(pdev);
909 0 : if (!link)
910 : goto unlock;
911 : /*
912 : * Setup initial ASPM state. Note that we need to configure
913 : * upstream links also because capable state of them can be
914 : * update through pcie_aspm_cap_init().
915 : */
916 0 : pcie_aspm_cap_init(link, blacklist);
917 :
918 : /* Setup initial Clock PM state */
919 0 : pcie_clkpm_cap_init(link, blacklist);
920 :
921 : /*
922 : * At this stage drivers haven't had an opportunity to change the
923 : * link policy setting. Enabling ASPM on broken hardware can cripple
924 : * it even before the driver has had a chance to disable ASPM, so
925 : * default to a safe level right now. If we're enabling ASPM beyond
926 : * the BIOS's expectation, we'll do so once pci_enable_device() is
927 : * called.
928 : */
929 0 : if (aspm_policy != POLICY_POWERSAVE &&
930 : aspm_policy != POLICY_POWER_SUPERSAVE) {
931 0 : pcie_config_aspm_path(link);
932 0 : pcie_set_clkpm(link, policy_to_clkpm_state(link));
933 : }
934 :
935 0 : pcie_aspm_update_sysfs_visibility(pdev);
936 :
937 : unlock:
938 0 : mutex_unlock(&aspm_lock);
939 : out:
940 0 : up_read(&pci_bus_sem);
941 : }
942 :
943 : /* Recheck latencies and update aspm_capable for links under the root */
944 0 : static void pcie_update_aspm_capable(struct pcie_link_state *root)
945 : {
946 : struct pcie_link_state *link;
947 0 : BUG_ON(root->parent);
948 0 : list_for_each_entry(link, &link_list, sibling) {
949 0 : if (link->root != root)
950 0 : continue;
951 0 : link->aspm_capable = link->aspm_support;
952 : }
953 0 : list_for_each_entry(link, &link_list, sibling) {
954 : struct pci_dev *child;
955 0 : struct pci_bus *linkbus = link->pdev->subordinate;
956 0 : if (link->root != root)
957 0 : continue;
958 0 : list_for_each_entry(child, &linkbus->devices, bus_list) {
959 0 : if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
960 0 : (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
961 0 : continue;
962 0 : pcie_aspm_check_latency(child);
963 : }
964 : }
965 0 : }
966 :
967 : /* @pdev: the endpoint device */
968 0 : void pcie_aspm_exit_link_state(struct pci_dev *pdev)
969 : {
970 0 : struct pci_dev *parent = pdev->bus->self;
971 : struct pcie_link_state *link, *root, *parent_link;
972 :
973 0 : if (!parent || !parent->link_state)
974 : return;
975 :
976 0 : down_read(&pci_bus_sem);
977 0 : mutex_lock(&aspm_lock);
978 :
979 0 : link = parent->link_state;
980 0 : root = link->root;
981 0 : parent_link = link->parent;
982 :
983 : /*
984 : * link->downstream is a pointer to the pci_dev of function 0. If
985 : * we remove that function, the pci_dev is about to be deallocated,
986 : * so we can't use link->downstream again. Free the link state to
987 : * avoid this.
988 : *
989 : * If we're removing a non-0 function, it's possible we could
990 : * retain the link state, but PCIe r6.0, sec 7.5.3.7, recommends
991 : * programming the same ASPM Control value for all functions of
992 : * multi-function devices, so disable ASPM for all of them.
993 : */
994 0 : pcie_config_aspm_link(link, 0);
995 0 : list_del(&link->sibling);
996 0 : free_link_state(link);
997 :
998 : /* Recheck latencies and configure upstream links */
999 0 : if (parent_link) {
1000 0 : pcie_update_aspm_capable(root);
1001 0 : pcie_config_aspm_path(parent_link);
1002 : }
1003 :
1004 0 : mutex_unlock(&aspm_lock);
1005 0 : up_read(&pci_bus_sem);
1006 : }
1007 :
1008 0 : void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1009 : {
1010 0 : struct pcie_link_state *link = pdev->link_state;
1011 :
1012 0 : if (aspm_disabled || !link)
1013 : return;
1014 :
1015 0 : if (aspm_policy != POLICY_POWERSAVE &&
1016 : aspm_policy != POLICY_POWER_SUPERSAVE)
1017 : return;
1018 :
1019 0 : down_read(&pci_bus_sem);
1020 0 : mutex_lock(&aspm_lock);
1021 0 : pcie_config_aspm_path(link);
1022 0 : pcie_set_clkpm(link, policy_to_clkpm_state(link));
1023 0 : mutex_unlock(&aspm_lock);
1024 0 : up_read(&pci_bus_sem);
1025 : }
1026 :
1027 : static struct pcie_link_state *pcie_aspm_get_link(struct pci_dev *pdev)
1028 : {
1029 : struct pci_dev *bridge;
1030 :
1031 0 : if (!pci_is_pcie(pdev))
1032 : return NULL;
1033 :
1034 0 : bridge = pci_upstream_bridge(pdev);
1035 0 : if (!bridge || !pci_is_pcie(bridge))
1036 : return NULL;
1037 :
1038 0 : return bridge->link_state;
1039 : }
1040 :
1041 0 : static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1042 : {
1043 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1044 :
1045 0 : if (!link)
1046 : return -EINVAL;
1047 : /*
1048 : * A driver requested that ASPM be disabled on this device, but
1049 : * if we don't have permission to manage ASPM (e.g., on ACPI
1050 : * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1051 : * the _OSC method), we can't honor that request. Windows has
1052 : * a similar mechanism using "PciASPMOptOut", which is also
1053 : * ignored in this situation.
1054 : */
1055 0 : if (aspm_disabled) {
1056 0 : pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1057 0 : return -EPERM;
1058 : }
1059 :
1060 0 : if (sem)
1061 0 : down_read(&pci_bus_sem);
1062 0 : mutex_lock(&aspm_lock);
1063 0 : if (state & PCIE_LINK_STATE_L0S)
1064 0 : link->aspm_disable |= ASPM_STATE_L0S;
1065 0 : if (state & PCIE_LINK_STATE_L1)
1066 0 : link->aspm_disable |= ASPM_STATE_L1;
1067 0 : if (state & PCIE_LINK_STATE_L1_1)
1068 0 : link->aspm_disable |= ASPM_STATE_L1_1;
1069 0 : if (state & PCIE_LINK_STATE_L1_2)
1070 0 : link->aspm_disable |= ASPM_STATE_L1_2;
1071 0 : if (state & PCIE_LINK_STATE_L1_1_PCIPM)
1072 0 : link->aspm_disable |= ASPM_STATE_L1_1_PCIPM;
1073 0 : if (state & PCIE_LINK_STATE_L1_2_PCIPM)
1074 0 : link->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
1075 0 : pcie_config_aspm_link(link, policy_to_aspm_state(link));
1076 :
1077 0 : if (state & PCIE_LINK_STATE_CLKPM)
1078 0 : link->clkpm_disable = 1;
1079 0 : pcie_set_clkpm(link, policy_to_clkpm_state(link));
1080 0 : mutex_unlock(&aspm_lock);
1081 0 : if (sem)
1082 0 : up_read(&pci_bus_sem);
1083 :
1084 : return 0;
1085 : }
1086 :
1087 0 : int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1088 : {
1089 0 : return __pci_disable_link_state(pdev, state, false);
1090 : }
1091 : EXPORT_SYMBOL(pci_disable_link_state_locked);
1092 :
1093 : /**
1094 : * pci_disable_link_state - Disable device's link state, so the link will
1095 : * never enter specific states. Note that if the BIOS didn't grant ASPM
1096 : * control to the OS, this does nothing because we can't touch the LNKCTL
1097 : * register. Returns 0 or a negative errno.
1098 : *
1099 : * @pdev: PCI device
1100 : * @state: ASPM link state to disable
1101 : */
1102 0 : int pci_disable_link_state(struct pci_dev *pdev, int state)
1103 : {
1104 0 : return __pci_disable_link_state(pdev, state, true);
1105 : }
1106 : EXPORT_SYMBOL(pci_disable_link_state);
1107 :
1108 : /**
1109 : * pci_enable_link_state - Clear and set the default device link state so that
1110 : * the link may be allowed to enter the specified states. Note that if the
1111 : * BIOS didn't grant ASPM control to the OS, this does nothing because we can't
1112 : * touch the LNKCTL register. Also note that this does not enable states
1113 : * disabled by pci_disable_link_state(). Return 0 or a negative errno.
1114 : *
1115 : * @pdev: PCI device
1116 : * @state: Mask of ASPM link states to enable
1117 : */
1118 0 : int pci_enable_link_state(struct pci_dev *pdev, int state)
1119 : {
1120 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1121 :
1122 0 : if (!link)
1123 : return -EINVAL;
1124 : /*
1125 : * A driver requested that ASPM be enabled on this device, but
1126 : * if we don't have permission to manage ASPM (e.g., on ACPI
1127 : * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1128 : * the _OSC method), we can't honor that request.
1129 : */
1130 0 : if (aspm_disabled) {
1131 0 : pci_warn(pdev, "can't override BIOS ASPM; OS doesn't have ASPM control\n");
1132 0 : return -EPERM;
1133 : }
1134 :
1135 0 : down_read(&pci_bus_sem);
1136 0 : mutex_lock(&aspm_lock);
1137 0 : link->aspm_default = 0;
1138 0 : if (state & PCIE_LINK_STATE_L0S)
1139 0 : link->aspm_default |= ASPM_STATE_L0S;
1140 0 : if (state & PCIE_LINK_STATE_L1)
1141 0 : link->aspm_default |= ASPM_STATE_L1;
1142 : /* L1 PM substates require L1 */
1143 0 : if (state & PCIE_LINK_STATE_L1_1)
1144 0 : link->aspm_default |= ASPM_STATE_L1_1 | ASPM_STATE_L1;
1145 0 : if (state & PCIE_LINK_STATE_L1_2)
1146 0 : link->aspm_default |= ASPM_STATE_L1_2 | ASPM_STATE_L1;
1147 0 : if (state & PCIE_LINK_STATE_L1_1_PCIPM)
1148 0 : link->aspm_default |= ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1;
1149 0 : if (state & PCIE_LINK_STATE_L1_2_PCIPM)
1150 0 : link->aspm_default |= ASPM_STATE_L1_2_PCIPM | ASPM_STATE_L1;
1151 0 : pcie_config_aspm_link(link, policy_to_aspm_state(link));
1152 :
1153 0 : link->clkpm_default = (state & PCIE_LINK_STATE_CLKPM) ? 1 : 0;
1154 0 : pcie_set_clkpm(link, policy_to_clkpm_state(link));
1155 0 : mutex_unlock(&aspm_lock);
1156 0 : up_read(&pci_bus_sem);
1157 :
1158 0 : return 0;
1159 : }
1160 : EXPORT_SYMBOL(pci_enable_link_state);
1161 :
1162 0 : static int pcie_aspm_set_policy(const char *val,
1163 : const struct kernel_param *kp)
1164 : {
1165 : int i;
1166 : struct pcie_link_state *link;
1167 :
1168 0 : if (aspm_disabled)
1169 : return -EPERM;
1170 0 : i = sysfs_match_string(policy_str, val);
1171 0 : if (i < 0)
1172 : return i;
1173 0 : if (i == aspm_policy)
1174 : return 0;
1175 :
1176 0 : down_read(&pci_bus_sem);
1177 0 : mutex_lock(&aspm_lock);
1178 0 : aspm_policy = i;
1179 0 : list_for_each_entry(link, &link_list, sibling) {
1180 0 : pcie_config_aspm_link(link, policy_to_aspm_state(link));
1181 0 : pcie_set_clkpm(link, policy_to_clkpm_state(link));
1182 : }
1183 0 : mutex_unlock(&aspm_lock);
1184 0 : up_read(&pci_bus_sem);
1185 0 : return 0;
1186 : }
1187 :
1188 0 : static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1189 : {
1190 0 : int i, cnt = 0;
1191 0 : for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1192 0 : if (i == aspm_policy)
1193 0 : cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1194 : else
1195 0 : cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1196 0 : cnt += sprintf(buffer + cnt, "\n");
1197 0 : return cnt;
1198 : }
1199 :
1200 : module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1201 : NULL, 0644);
1202 :
1203 : /**
1204 : * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1205 : * @pdev: Target device.
1206 : *
1207 : * Relies on the upstream bridge's link_state being valid. The link_state
1208 : * is deallocated only when the last child of the bridge (i.e., @pdev or a
1209 : * sibling) is removed, and the caller should be holding a reference to
1210 : * @pdev, so this should be safe.
1211 : */
1212 0 : bool pcie_aspm_enabled(struct pci_dev *pdev)
1213 : {
1214 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1215 :
1216 0 : if (!link)
1217 : return false;
1218 :
1219 0 : return link->aspm_enabled;
1220 : }
1221 : EXPORT_SYMBOL_GPL(pcie_aspm_enabled);
1222 :
1223 0 : static ssize_t aspm_attr_show_common(struct device *dev,
1224 : struct device_attribute *attr,
1225 : char *buf, u8 state)
1226 : {
1227 0 : struct pci_dev *pdev = to_pci_dev(dev);
1228 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1229 :
1230 0 : return sysfs_emit(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0);
1231 : }
1232 :
1233 0 : static ssize_t aspm_attr_store_common(struct device *dev,
1234 : struct device_attribute *attr,
1235 : const char *buf, size_t len, u8 state)
1236 : {
1237 0 : struct pci_dev *pdev = to_pci_dev(dev);
1238 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1239 : bool state_enable;
1240 :
1241 0 : if (kstrtobool(buf, &state_enable) < 0)
1242 : return -EINVAL;
1243 :
1244 0 : down_read(&pci_bus_sem);
1245 0 : mutex_lock(&aspm_lock);
1246 :
1247 0 : if (state_enable) {
1248 0 : link->aspm_disable &= ~state;
1249 : /* need to enable L1 for substates */
1250 0 : if (state & ASPM_STATE_L1SS)
1251 0 : link->aspm_disable &= ~ASPM_STATE_L1;
1252 : } else {
1253 0 : link->aspm_disable |= state;
1254 : }
1255 :
1256 0 : pcie_config_aspm_link(link, policy_to_aspm_state(link));
1257 :
1258 0 : mutex_unlock(&aspm_lock);
1259 0 : up_read(&pci_bus_sem);
1260 :
1261 0 : return len;
1262 : }
1263 :
1264 : #define ASPM_ATTR(_f, _s) \
1265 : static ssize_t _f##_show(struct device *dev, \
1266 : struct device_attribute *attr, char *buf) \
1267 : { return aspm_attr_show_common(dev, attr, buf, ASPM_STATE_##_s); } \
1268 : \
1269 : static ssize_t _f##_store(struct device *dev, \
1270 : struct device_attribute *attr, \
1271 : const char *buf, size_t len) \
1272 : { return aspm_attr_store_common(dev, attr, buf, len, ASPM_STATE_##_s); }
1273 :
1274 0 : ASPM_ATTR(l0s_aspm, L0S)
1275 0 : ASPM_ATTR(l1_aspm, L1)
1276 0 : ASPM_ATTR(l1_1_aspm, L1_1)
1277 0 : ASPM_ATTR(l1_2_aspm, L1_2)
1278 0 : ASPM_ATTR(l1_1_pcipm, L1_1_PCIPM)
1279 0 : ASPM_ATTR(l1_2_pcipm, L1_2_PCIPM)
1280 :
1281 0 : static ssize_t clkpm_show(struct device *dev,
1282 : struct device_attribute *attr, char *buf)
1283 : {
1284 0 : struct pci_dev *pdev = to_pci_dev(dev);
1285 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1286 :
1287 0 : return sysfs_emit(buf, "%d\n", link->clkpm_enabled);
1288 : }
1289 :
1290 0 : static ssize_t clkpm_store(struct device *dev,
1291 : struct device_attribute *attr,
1292 : const char *buf, size_t len)
1293 : {
1294 0 : struct pci_dev *pdev = to_pci_dev(dev);
1295 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1296 : bool state_enable;
1297 :
1298 0 : if (kstrtobool(buf, &state_enable) < 0)
1299 : return -EINVAL;
1300 :
1301 0 : down_read(&pci_bus_sem);
1302 0 : mutex_lock(&aspm_lock);
1303 :
1304 0 : link->clkpm_disable = !state_enable;
1305 0 : pcie_set_clkpm(link, policy_to_clkpm_state(link));
1306 :
1307 0 : mutex_unlock(&aspm_lock);
1308 0 : up_read(&pci_bus_sem);
1309 :
1310 0 : return len;
1311 : }
1312 :
1313 : static DEVICE_ATTR_RW(clkpm);
1314 : static DEVICE_ATTR_RW(l0s_aspm);
1315 : static DEVICE_ATTR_RW(l1_aspm);
1316 : static DEVICE_ATTR_RW(l1_1_aspm);
1317 : static DEVICE_ATTR_RW(l1_2_aspm);
1318 : static DEVICE_ATTR_RW(l1_1_pcipm);
1319 : static DEVICE_ATTR_RW(l1_2_pcipm);
1320 :
1321 : static struct attribute *aspm_ctrl_attrs[] = {
1322 : &dev_attr_clkpm.attr,
1323 : &dev_attr_l0s_aspm.attr,
1324 : &dev_attr_l1_aspm.attr,
1325 : &dev_attr_l1_1_aspm.attr,
1326 : &dev_attr_l1_2_aspm.attr,
1327 : &dev_attr_l1_1_pcipm.attr,
1328 : &dev_attr_l1_2_pcipm.attr,
1329 : NULL
1330 : };
1331 :
1332 0 : static umode_t aspm_ctrl_attrs_are_visible(struct kobject *kobj,
1333 : struct attribute *a, int n)
1334 : {
1335 0 : struct device *dev = kobj_to_dev(kobj);
1336 0 : struct pci_dev *pdev = to_pci_dev(dev);
1337 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1338 : static const u8 aspm_state_map[] = {
1339 : ASPM_STATE_L0S,
1340 : ASPM_STATE_L1,
1341 : ASPM_STATE_L1_1,
1342 : ASPM_STATE_L1_2,
1343 : ASPM_STATE_L1_1_PCIPM,
1344 : ASPM_STATE_L1_2_PCIPM,
1345 : };
1346 :
1347 0 : if (aspm_disabled || !link)
1348 : return 0;
1349 :
1350 0 : if (n == 0)
1351 0 : return link->clkpm_capable ? a->mode : 0;
1352 :
1353 0 : return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0;
1354 : }
1355 :
1356 : const struct attribute_group aspm_ctrl_attr_group = {
1357 : .name = "link",
1358 : .attrs = aspm_ctrl_attrs,
1359 : .is_visible = aspm_ctrl_attrs_are_visible,
1360 : };
1361 :
1362 0 : static int __init pcie_aspm_disable(char *str)
1363 : {
1364 0 : if (!strcmp(str, "off")) {
1365 0 : aspm_policy = POLICY_DEFAULT;
1366 0 : aspm_disabled = 1;
1367 0 : aspm_support_enabled = false;
1368 0 : printk(KERN_INFO "PCIe ASPM is disabled\n");
1369 0 : } else if (!strcmp(str, "force")) {
1370 0 : aspm_force = 1;
1371 0 : printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1372 : }
1373 0 : return 1;
1374 : }
1375 :
1376 : __setup("pcie_aspm=", pcie_aspm_disable);
1377 :
1378 0 : void pcie_no_aspm(void)
1379 : {
1380 : /*
1381 : * Disabling ASPM is intended to prevent the kernel from modifying
1382 : * existing hardware state, not to clear existing state. To that end:
1383 : * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1384 : * (b) prevent userspace from changing policy
1385 : */
1386 0 : if (!aspm_force) {
1387 0 : aspm_policy = POLICY_DEFAULT;
1388 0 : aspm_disabled = 1;
1389 : }
1390 0 : }
1391 :
1392 0 : bool pcie_aspm_support_enabled(void)
1393 : {
1394 0 : return aspm_support_enabled;
1395 : }
|
