Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0
2 : /*
3 : * PCI detection and setup code
4 : */
5 :
6 : #include <linux/kernel.h>
7 : #include <linux/delay.h>
8 : #include <linux/init.h>
9 : #include <linux/pci.h>
10 : #include <linux/msi.h>
11 : #include <linux/of_device.h>
12 : #include <linux/of_pci.h>
13 : #include <linux/pci_hotplug.h>
14 : #include <linux/slab.h>
15 : #include <linux/module.h>
16 : #include <linux/cpumask.h>
17 : #include <linux/aer.h>
18 : #include <linux/acpi.h>
19 : #include <linux/hypervisor.h>
20 : #include <linux/irqdomain.h>
21 : #include <linux/pm_runtime.h>
22 : #include <linux/bitfield.h>
23 : #include "pci.h"
24 :
25 : #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
26 : #define CARDBUS_RESERVE_BUSNR 3
27 :
28 : static struct resource busn_resource = {
29 : .name = "PCI busn",
30 : .start = 0,
31 : .end = 255,
32 : .flags = IORESOURCE_BUS,
33 : };
34 :
35 : /* Ugh. Need to stop exporting this to modules. */
36 : LIST_HEAD(pci_root_buses);
37 : EXPORT_SYMBOL(pci_root_buses);
38 :
39 : static LIST_HEAD(pci_domain_busn_res_list);
40 :
41 : struct pci_domain_busn_res {
42 : struct list_head list;
43 : struct resource res;
44 : int domain_nr;
45 : };
46 :
47 0 : static struct resource *get_pci_domain_busn_res(int domain_nr)
48 : {
49 : struct pci_domain_busn_res *r;
50 :
51 0 : list_for_each_entry(r, &pci_domain_busn_res_list, list)
52 0 : if (r->domain_nr == domain_nr)
53 0 : return &r->res;
54 :
55 0 : r = kzalloc(sizeof(*r), GFP_KERNEL);
56 0 : if (!r)
57 : return NULL;
58 :
59 0 : r->domain_nr = domain_nr;
60 0 : r->res.start = 0;
61 0 : r->res.end = 0xff;
62 0 : r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
63 :
64 0 : list_add_tail(&r->list, &pci_domain_busn_res_list);
65 :
66 0 : return &r->res;
67 : }
68 :
69 : /*
70 : * Some device drivers need know if PCI is initiated.
71 : * Basically, we think PCI is not initiated when there
72 : * is no device to be found on the pci_bus_type.
73 : */
74 0 : int no_pci_devices(void)
75 : {
76 : struct device *dev;
77 : int no_devices;
78 :
79 0 : dev = bus_find_next_device(&pci_bus_type, NULL);
80 0 : no_devices = (dev == NULL);
81 0 : put_device(dev);
82 0 : return no_devices;
83 : }
84 : EXPORT_SYMBOL(no_pci_devices);
85 :
86 : /*
87 : * PCI Bus Class
88 : */
89 0 : static void release_pcibus_dev(struct device *dev)
90 : {
91 0 : struct pci_bus *pci_bus = to_pci_bus(dev);
92 :
93 0 : put_device(pci_bus->bridge);
94 0 : pci_bus_remove_resources(pci_bus);
95 0 : pci_release_bus_of_node(pci_bus);
96 0 : kfree(pci_bus);
97 0 : }
98 :
99 : static struct class pcibus_class = {
100 : .name = "pci_bus",
101 : .dev_release = &release_pcibus_dev,
102 : .dev_groups = pcibus_groups,
103 : };
104 :
105 1 : static int __init pcibus_class_init(void)
106 : {
107 1 : return class_register(&pcibus_class);
108 : }
109 : postcore_initcall(pcibus_class_init);
110 :
111 : static u64 pci_size(u64 base, u64 maxbase, u64 mask)
112 : {
113 0 : u64 size = mask & maxbase; /* Find the significant bits */
114 0 : if (!size)
115 : return 0;
116 :
117 : /*
118 : * Get the lowest of them to find the decode size, and from that
119 : * the extent.
120 : */
121 0 : size = size & ~(size-1);
122 :
123 : /*
124 : * base == maxbase can be valid only if the BAR has already been
125 : * programmed with all 1s.
126 : */
127 0 : if (base == maxbase && ((base | (size - 1)) & mask) != mask)
128 : return 0;
129 :
130 : return size;
131 : }
132 :
133 : static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
134 : {
135 : u32 mem_type;
136 : unsigned long flags;
137 :
138 0 : if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
139 0 : flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
140 0 : flags |= IORESOURCE_IO;
141 : return flags;
142 : }
143 :
144 0 : flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
145 0 : flags |= IORESOURCE_MEM;
146 0 : if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
147 0 : flags |= IORESOURCE_PREFETCH;
148 :
149 0 : mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
150 0 : switch (mem_type) {
151 : case PCI_BASE_ADDRESS_MEM_TYPE_32:
152 : break;
153 : case PCI_BASE_ADDRESS_MEM_TYPE_1M:
154 : /* 1M mem BAR treated as 32-bit BAR */
155 : break;
156 : case PCI_BASE_ADDRESS_MEM_TYPE_64:
157 0 : flags |= IORESOURCE_MEM_64;
158 : break;
159 : default:
160 : /* mem unknown type treated as 32-bit BAR */
161 : break;
162 : }
163 : return flags;
164 : }
165 :
166 : #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
167 :
168 : /**
169 : * __pci_read_base - Read a PCI BAR
170 : * @dev: the PCI device
171 : * @type: type of the BAR
172 : * @res: resource buffer to be filled in
173 : * @pos: BAR position in the config space
174 : *
175 : * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
176 : */
177 0 : int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
178 : struct resource *res, unsigned int pos)
179 : {
180 0 : u32 l = 0, sz = 0, mask;
181 : u64 l64, sz64, mask64;
182 : u16 orig_cmd;
183 : struct pci_bus_region region, inverted_region;
184 :
185 0 : mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
186 :
187 : /* No printks while decoding is disabled! */
188 0 : if (!dev->mmio_always_on) {
189 0 : pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
190 0 : if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
191 0 : pci_write_config_word(dev, PCI_COMMAND,
192 : orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
193 : }
194 : }
195 :
196 0 : res->name = pci_name(dev);
197 :
198 0 : pci_read_config_dword(dev, pos, &l);
199 0 : pci_write_config_dword(dev, pos, l | mask);
200 0 : pci_read_config_dword(dev, pos, &sz);
201 0 : pci_write_config_dword(dev, pos, l);
202 :
203 : /*
204 : * All bits set in sz means the device isn't working properly.
205 : * If the BAR isn't implemented, all bits must be 0. If it's a
206 : * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 : * 1 must be clear.
208 : */
209 0 : if (PCI_POSSIBLE_ERROR(sz))
210 0 : sz = 0;
211 :
212 : /*
213 : * I don't know how l can have all bits set. Copied from old code.
214 : * Maybe it fixes a bug on some ancient platform.
215 : */
216 0 : if (PCI_POSSIBLE_ERROR(l))
217 0 : l = 0;
218 :
219 0 : if (type == pci_bar_unknown) {
220 0 : res->flags = decode_bar(dev, l);
221 0 : res->flags |= IORESOURCE_SIZEALIGN;
222 0 : if (res->flags & IORESOURCE_IO) {
223 0 : l64 = l & PCI_BASE_ADDRESS_IO_MASK;
224 0 : sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
225 0 : mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
226 : } else {
227 0 : l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
228 0 : sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
229 0 : mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 : }
231 : } else {
232 0 : if (l & PCI_ROM_ADDRESS_ENABLE)
233 0 : res->flags |= IORESOURCE_ROM_ENABLE;
234 0 : l64 = l & PCI_ROM_ADDRESS_MASK;
235 0 : sz64 = sz & PCI_ROM_ADDRESS_MASK;
236 0 : mask64 = PCI_ROM_ADDRESS_MASK;
237 : }
238 :
239 0 : if (res->flags & IORESOURCE_MEM_64) {
240 0 : pci_read_config_dword(dev, pos + 4, &l);
241 0 : pci_write_config_dword(dev, pos + 4, ~0);
242 0 : pci_read_config_dword(dev, pos + 4, &sz);
243 0 : pci_write_config_dword(dev, pos + 4, l);
244 :
245 0 : l64 |= ((u64)l << 32);
246 0 : sz64 |= ((u64)sz << 32);
247 0 : mask64 |= ((u64)~0 << 32);
248 : }
249 :
250 0 : if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
251 0 : pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
252 :
253 0 : if (!sz64)
254 : goto fail;
255 :
256 0 : sz64 = pci_size(l64, sz64, mask64);
257 0 : if (!sz64) {
258 0 : pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
259 : pos);
260 0 : goto fail;
261 : }
262 :
263 : if (res->flags & IORESOURCE_MEM_64) {
264 : if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
265 : && sz64 > 0x100000000ULL) {
266 : res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
267 : res->start = 0;
268 : res->end = 0;
269 : pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
270 : pos, (unsigned long long)sz64);
271 : goto out;
272 : }
273 :
274 : if ((sizeof(pci_bus_addr_t) < 8) && l) {
275 : /* Above 32-bit boundary; try to reallocate */
276 : res->flags |= IORESOURCE_UNSET;
277 : res->start = 0;
278 : res->end = sz64 - 1;
279 : pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
280 : pos, (unsigned long long)l64);
281 : goto out;
282 : }
283 : }
284 :
285 0 : region.start = l64;
286 0 : region.end = l64 + sz64 - 1;
287 :
288 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
289 0 : pcibios_resource_to_bus(dev->bus, &inverted_region, res);
290 :
291 : /*
292 : * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
293 : * the corresponding resource address (the physical address used by
294 : * the CPU. Converting that resource address back to a bus address
295 : * should yield the original BAR value:
296 : *
297 : * resource_to_bus(bus_to_resource(A)) == A
298 : *
299 : * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
300 : * be claimed by the device.
301 : */
302 0 : if (inverted_region.start != region.start) {
303 0 : res->flags |= IORESOURCE_UNSET;
304 0 : res->start = 0;
305 0 : res->end = region.end - region.start;
306 0 : pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
307 : pos, (unsigned long long)region.start);
308 : }
309 :
310 : goto out;
311 :
312 :
313 : fail:
314 0 : res->flags = 0;
315 : out:
316 0 : if (res->flags)
317 0 : pci_info(dev, "reg 0x%x: %pR\n", pos, res);
318 :
319 0 : return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
320 : }
321 :
322 0 : static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
323 : {
324 : unsigned int pos, reg;
325 :
326 0 : if (dev->non_compliant_bars)
327 : return;
328 :
329 : /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
330 0 : if (dev->is_virtfn)
331 : return;
332 :
333 0 : for (pos = 0; pos < howmany; pos++) {
334 0 : struct resource *res = &dev->resource[pos];
335 0 : reg = PCI_BASE_ADDRESS_0 + (pos << 2);
336 0 : pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
337 : }
338 :
339 0 : if (rom) {
340 0 : struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
341 0 : dev->rom_base_reg = rom;
342 0 : res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
343 : IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
344 0 : __pci_read_base(dev, pci_bar_mem32, res, rom);
345 : }
346 : }
347 :
348 0 : static void pci_read_bridge_windows(struct pci_dev *bridge)
349 : {
350 : u16 io;
351 : u32 pmem, tmp;
352 :
353 0 : pci_read_config_word(bridge, PCI_IO_BASE, &io);
354 0 : if (!io) {
355 0 : pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
356 0 : pci_read_config_word(bridge, PCI_IO_BASE, &io);
357 0 : pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
358 : }
359 0 : if (io)
360 0 : bridge->io_window = 1;
361 :
362 : /*
363 : * DECchip 21050 pass 2 errata: the bridge may miss an address
364 : * disconnect boundary by one PCI data phase. Workaround: do not
365 : * use prefetching on this device.
366 : */
367 0 : if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
368 0 : return;
369 :
370 0 : pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
371 0 : if (!pmem) {
372 0 : pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
373 : 0xffe0fff0);
374 0 : pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
375 0 : pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
376 : }
377 0 : if (!pmem)
378 : return;
379 :
380 0 : bridge->pref_window = 1;
381 :
382 0 : if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
383 :
384 : /*
385 : * Bridge claims to have a 64-bit prefetchable memory
386 : * window; verify that the upper bits are actually
387 : * writable.
388 : */
389 0 : pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
390 0 : pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
391 : 0xffffffff);
392 0 : pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
393 0 : pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
394 0 : if (tmp)
395 0 : bridge->pref_64_window = 1;
396 : }
397 : }
398 :
399 0 : static void pci_read_bridge_io(struct pci_bus *child)
400 : {
401 0 : struct pci_dev *dev = child->self;
402 : u8 io_base_lo, io_limit_lo;
403 : unsigned long io_mask, io_granularity, base, limit;
404 : struct pci_bus_region region;
405 : struct resource *res;
406 :
407 0 : io_mask = PCI_IO_RANGE_MASK;
408 0 : io_granularity = 0x1000;
409 0 : if (dev->io_window_1k) {
410 : /* Support 1K I/O space granularity */
411 0 : io_mask = PCI_IO_1K_RANGE_MASK;
412 0 : io_granularity = 0x400;
413 : }
414 :
415 0 : res = child->resource[0];
416 0 : pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
417 0 : pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
418 0 : base = (io_base_lo & io_mask) << 8;
419 0 : limit = (io_limit_lo & io_mask) << 8;
420 :
421 0 : if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
422 : u16 io_base_hi, io_limit_hi;
423 :
424 0 : pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
425 0 : pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
426 0 : base |= ((unsigned long) io_base_hi << 16);
427 0 : limit |= ((unsigned long) io_limit_hi << 16);
428 : }
429 :
430 0 : if (base <= limit) {
431 0 : res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
432 0 : region.start = base;
433 0 : region.end = limit + io_granularity - 1;
434 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
435 0 : pci_info(dev, " bridge window %pR\n", res);
436 : }
437 0 : }
438 :
439 0 : static void pci_read_bridge_mmio(struct pci_bus *child)
440 : {
441 0 : struct pci_dev *dev = child->self;
442 : u16 mem_base_lo, mem_limit_lo;
443 : unsigned long base, limit;
444 : struct pci_bus_region region;
445 : struct resource *res;
446 :
447 0 : res = child->resource[1];
448 0 : pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
449 0 : pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
450 0 : base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
451 0 : limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
452 0 : if (base <= limit) {
453 0 : res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
454 0 : region.start = base;
455 0 : region.end = limit + 0xfffff;
456 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
457 0 : pci_info(dev, " bridge window %pR\n", res);
458 : }
459 0 : }
460 :
461 0 : static void pci_read_bridge_mmio_pref(struct pci_bus *child)
462 : {
463 0 : struct pci_dev *dev = child->self;
464 : u16 mem_base_lo, mem_limit_lo;
465 : u64 base64, limit64;
466 : pci_bus_addr_t base, limit;
467 : struct pci_bus_region region;
468 : struct resource *res;
469 :
470 0 : res = child->resource[2];
471 0 : pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
472 0 : pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
473 0 : base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
474 0 : limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
475 :
476 0 : if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
477 : u32 mem_base_hi, mem_limit_hi;
478 :
479 0 : pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
480 0 : pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
481 :
482 : /*
483 : * Some bridges set the base > limit by default, and some
484 : * (broken) BIOSes do not initialize them. If we find
485 : * this, just assume they are not being used.
486 : */
487 0 : if (mem_base_hi <= mem_limit_hi) {
488 0 : base64 |= (u64) mem_base_hi << 32;
489 0 : limit64 |= (u64) mem_limit_hi << 32;
490 : }
491 : }
492 :
493 0 : base = (pci_bus_addr_t) base64;
494 0 : limit = (pci_bus_addr_t) limit64;
495 :
496 : if (base != base64) {
497 : pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
498 : (unsigned long long) base64);
499 : return;
500 : }
501 :
502 0 : if (base <= limit) {
503 0 : res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
504 0 : IORESOURCE_MEM | IORESOURCE_PREFETCH;
505 0 : if (res->flags & PCI_PREF_RANGE_TYPE_64)
506 0 : res->flags |= IORESOURCE_MEM_64;
507 0 : region.start = base;
508 0 : region.end = limit + 0xfffff;
509 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
510 0 : pci_info(dev, " bridge window %pR\n", res);
511 : }
512 : }
513 :
514 0 : void pci_read_bridge_bases(struct pci_bus *child)
515 : {
516 0 : struct pci_dev *dev = child->self;
517 : struct resource *res;
518 : int i;
519 :
520 0 : if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
521 : return;
522 :
523 0 : pci_info(dev, "PCI bridge to %pR%s\n",
524 : &child->busn_res,
525 : dev->transparent ? " (subtractive decode)" : "");
526 :
527 0 : pci_bus_remove_resources(child);
528 0 : for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
529 0 : child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
530 :
531 0 : pci_read_bridge_io(child);
532 0 : pci_read_bridge_mmio(child);
533 0 : pci_read_bridge_mmio_pref(child);
534 :
535 0 : if (dev->transparent) {
536 0 : pci_bus_for_each_resource(child->parent, res) {
537 0 : if (res && res->flags) {
538 0 : pci_bus_add_resource(child, res,
539 : PCI_SUBTRACTIVE_DECODE);
540 0 : pci_info(dev, " bridge window %pR (subtractive decode)\n",
541 : res);
542 : }
543 : }
544 : }
545 : }
546 :
547 0 : static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
548 : {
549 : struct pci_bus *b;
550 :
551 0 : b = kzalloc(sizeof(*b), GFP_KERNEL);
552 0 : if (!b)
553 : return NULL;
554 :
555 0 : INIT_LIST_HEAD(&b->node);
556 0 : INIT_LIST_HEAD(&b->children);
557 0 : INIT_LIST_HEAD(&b->devices);
558 0 : INIT_LIST_HEAD(&b->slots);
559 0 : INIT_LIST_HEAD(&b->resources);
560 0 : b->max_bus_speed = PCI_SPEED_UNKNOWN;
561 0 : b->cur_bus_speed = PCI_SPEED_UNKNOWN;
562 : #ifdef CONFIG_PCI_DOMAINS_GENERIC
563 : if (parent)
564 : b->domain_nr = parent->domain_nr;
565 : #endif
566 : return b;
567 : }
568 :
569 0 : static void pci_release_host_bridge_dev(struct device *dev)
570 : {
571 0 : struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
572 :
573 0 : if (bridge->release_fn)
574 0 : bridge->release_fn(bridge);
575 :
576 0 : pci_free_resource_list(&bridge->windows);
577 0 : pci_free_resource_list(&bridge->dma_ranges);
578 0 : kfree(bridge);
579 0 : }
580 :
581 : static void pci_init_host_bridge(struct pci_host_bridge *bridge)
582 : {
583 0 : INIT_LIST_HEAD(&bridge->windows);
584 0 : INIT_LIST_HEAD(&bridge->dma_ranges);
585 :
586 : /*
587 : * We assume we can manage these PCIe features. Some systems may
588 : * reserve these for use by the platform itself, e.g., an ACPI BIOS
589 : * may implement its own AER handling and use _OSC to prevent the
590 : * OS from interfering.
591 : */
592 0 : bridge->native_aer = 1;
593 0 : bridge->native_pcie_hotplug = 1;
594 0 : bridge->native_shpc_hotplug = 1;
595 0 : bridge->native_pme = 1;
596 0 : bridge->native_ltr = 1;
597 0 : bridge->native_dpc = 1;
598 0 : bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
599 0 : bridge->native_cxl_error = 1;
600 :
601 0 : device_initialize(&bridge->dev);
602 : }
603 :
604 0 : struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
605 : {
606 : struct pci_host_bridge *bridge;
607 :
608 0 : bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
609 0 : if (!bridge)
610 : return NULL;
611 :
612 0 : pci_init_host_bridge(bridge);
613 0 : bridge->dev.release = pci_release_host_bridge_dev;
614 :
615 0 : return bridge;
616 : }
617 : EXPORT_SYMBOL(pci_alloc_host_bridge);
618 :
619 0 : static void devm_pci_alloc_host_bridge_release(void *data)
620 : {
621 0 : pci_free_host_bridge(data);
622 0 : }
623 :
624 0 : struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
625 : size_t priv)
626 : {
627 : int ret;
628 : struct pci_host_bridge *bridge;
629 :
630 0 : bridge = pci_alloc_host_bridge(priv);
631 0 : if (!bridge)
632 : return NULL;
633 :
634 0 : bridge->dev.parent = dev;
635 :
636 0 : ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
637 : bridge);
638 0 : if (ret)
639 : return NULL;
640 :
641 0 : ret = devm_of_pci_bridge_init(dev, bridge);
642 : if (ret)
643 : return NULL;
644 :
645 0 : return bridge;
646 : }
647 : EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
648 :
649 0 : void pci_free_host_bridge(struct pci_host_bridge *bridge)
650 : {
651 0 : put_device(&bridge->dev);
652 0 : }
653 : EXPORT_SYMBOL(pci_free_host_bridge);
654 :
655 : /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
656 : static const unsigned char pcix_bus_speed[] = {
657 : PCI_SPEED_UNKNOWN, /* 0 */
658 : PCI_SPEED_66MHz_PCIX, /* 1 */
659 : PCI_SPEED_100MHz_PCIX, /* 2 */
660 : PCI_SPEED_133MHz_PCIX, /* 3 */
661 : PCI_SPEED_UNKNOWN, /* 4 */
662 : PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
663 : PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
664 : PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
665 : PCI_SPEED_UNKNOWN, /* 8 */
666 : PCI_SPEED_66MHz_PCIX_266, /* 9 */
667 : PCI_SPEED_100MHz_PCIX_266, /* A */
668 : PCI_SPEED_133MHz_PCIX_266, /* B */
669 : PCI_SPEED_UNKNOWN, /* C */
670 : PCI_SPEED_66MHz_PCIX_533, /* D */
671 : PCI_SPEED_100MHz_PCIX_533, /* E */
672 : PCI_SPEED_133MHz_PCIX_533 /* F */
673 : };
674 :
675 : /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
676 : const unsigned char pcie_link_speed[] = {
677 : PCI_SPEED_UNKNOWN, /* 0 */
678 : PCIE_SPEED_2_5GT, /* 1 */
679 : PCIE_SPEED_5_0GT, /* 2 */
680 : PCIE_SPEED_8_0GT, /* 3 */
681 : PCIE_SPEED_16_0GT, /* 4 */
682 : PCIE_SPEED_32_0GT, /* 5 */
683 : PCIE_SPEED_64_0GT, /* 6 */
684 : PCI_SPEED_UNKNOWN, /* 7 */
685 : PCI_SPEED_UNKNOWN, /* 8 */
686 : PCI_SPEED_UNKNOWN, /* 9 */
687 : PCI_SPEED_UNKNOWN, /* A */
688 : PCI_SPEED_UNKNOWN, /* B */
689 : PCI_SPEED_UNKNOWN, /* C */
690 : PCI_SPEED_UNKNOWN, /* D */
691 : PCI_SPEED_UNKNOWN, /* E */
692 : PCI_SPEED_UNKNOWN /* F */
693 : };
694 : EXPORT_SYMBOL_GPL(pcie_link_speed);
695 :
696 0 : const char *pci_speed_string(enum pci_bus_speed speed)
697 : {
698 : /* Indexed by the pci_bus_speed enum */
699 : static const char *speed_strings[] = {
700 : "33 MHz PCI", /* 0x00 */
701 : "66 MHz PCI", /* 0x01 */
702 : "66 MHz PCI-X", /* 0x02 */
703 : "100 MHz PCI-X", /* 0x03 */
704 : "133 MHz PCI-X", /* 0x04 */
705 : NULL, /* 0x05 */
706 : NULL, /* 0x06 */
707 : NULL, /* 0x07 */
708 : NULL, /* 0x08 */
709 : "66 MHz PCI-X 266", /* 0x09 */
710 : "100 MHz PCI-X 266", /* 0x0a */
711 : "133 MHz PCI-X 266", /* 0x0b */
712 : "Unknown AGP", /* 0x0c */
713 : "1x AGP", /* 0x0d */
714 : "2x AGP", /* 0x0e */
715 : "4x AGP", /* 0x0f */
716 : "8x AGP", /* 0x10 */
717 : "66 MHz PCI-X 533", /* 0x11 */
718 : "100 MHz PCI-X 533", /* 0x12 */
719 : "133 MHz PCI-X 533", /* 0x13 */
720 : "2.5 GT/s PCIe", /* 0x14 */
721 : "5.0 GT/s PCIe", /* 0x15 */
722 : "8.0 GT/s PCIe", /* 0x16 */
723 : "16.0 GT/s PCIe", /* 0x17 */
724 : "32.0 GT/s PCIe", /* 0x18 */
725 : "64.0 GT/s PCIe", /* 0x19 */
726 : };
727 :
728 0 : if (speed < ARRAY_SIZE(speed_strings))
729 0 : return speed_strings[speed];
730 : return "Unknown";
731 : }
732 : EXPORT_SYMBOL_GPL(pci_speed_string);
733 :
734 0 : void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
735 : {
736 0 : bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
737 0 : }
738 : EXPORT_SYMBOL_GPL(pcie_update_link_speed);
739 :
740 : static unsigned char agp_speeds[] = {
741 : AGP_UNKNOWN,
742 : AGP_1X,
743 : AGP_2X,
744 : AGP_4X,
745 : AGP_8X
746 : };
747 :
748 : static enum pci_bus_speed agp_speed(int agp3, int agpstat)
749 : {
750 0 : int index = 0;
751 :
752 0 : if (agpstat & 4)
753 : index = 3;
754 0 : else if (agpstat & 2)
755 : index = 2;
756 0 : else if (agpstat & 1)
757 : index = 1;
758 : else
759 : goto out;
760 :
761 0 : if (agp3) {
762 0 : index += 2;
763 0 : if (index == 5)
764 0 : index = 0;
765 : }
766 :
767 : out:
768 0 : return agp_speeds[index];
769 : }
770 :
771 0 : static void pci_set_bus_speed(struct pci_bus *bus)
772 : {
773 0 : struct pci_dev *bridge = bus->self;
774 : int pos;
775 :
776 0 : pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
777 0 : if (!pos)
778 0 : pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
779 0 : if (pos) {
780 : u32 agpstat, agpcmd;
781 :
782 0 : pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
783 0 : bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
784 :
785 0 : pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
786 0 : bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
787 : }
788 :
789 0 : pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
790 0 : if (pos) {
791 : u16 status;
792 : enum pci_bus_speed max;
793 :
794 0 : pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
795 : &status);
796 :
797 0 : if (status & PCI_X_SSTATUS_533MHZ) {
798 : max = PCI_SPEED_133MHz_PCIX_533;
799 0 : } else if (status & PCI_X_SSTATUS_266MHZ) {
800 : max = PCI_SPEED_133MHz_PCIX_266;
801 0 : } else if (status & PCI_X_SSTATUS_133MHZ) {
802 0 : if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
803 : max = PCI_SPEED_133MHz_PCIX_ECC;
804 : else
805 0 : max = PCI_SPEED_133MHz_PCIX;
806 : } else {
807 : max = PCI_SPEED_66MHz_PCIX;
808 : }
809 :
810 0 : bus->max_bus_speed = max;
811 0 : bus->cur_bus_speed = pcix_bus_speed[
812 0 : (status & PCI_X_SSTATUS_FREQ) >> 6];
813 :
814 : return;
815 : }
816 :
817 0 : if (pci_is_pcie(bridge)) {
818 : u32 linkcap;
819 : u16 linksta;
820 :
821 0 : pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
822 0 : bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
823 :
824 0 : pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
825 0 : pcie_update_link_speed(bus, linksta);
826 : }
827 : }
828 :
829 0 : static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
830 : {
831 : struct irq_domain *d;
832 :
833 : /* If the host bridge driver sets a MSI domain of the bridge, use it */
834 0 : d = dev_get_msi_domain(bus->bridge);
835 :
836 : /*
837 : * Any firmware interface that can resolve the msi_domain
838 : * should be called from here.
839 : */
840 0 : if (!d)
841 0 : d = pci_host_bridge_of_msi_domain(bus);
842 0 : if (!d)
843 0 : d = pci_host_bridge_acpi_msi_domain(bus);
844 :
845 : /*
846 : * If no IRQ domain was found via the OF tree, try looking it up
847 : * directly through the fwnode_handle.
848 : */
849 0 : if (!d) {
850 0 : struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
851 :
852 0 : if (fwnode)
853 0 : d = irq_find_matching_fwnode(fwnode,
854 : DOMAIN_BUS_PCI_MSI);
855 : }
856 :
857 0 : return d;
858 : }
859 :
860 0 : static void pci_set_bus_msi_domain(struct pci_bus *bus)
861 : {
862 : struct irq_domain *d;
863 : struct pci_bus *b;
864 :
865 : /*
866 : * The bus can be a root bus, a subordinate bus, or a virtual bus
867 : * created by an SR-IOV device. Walk up to the first bridge device
868 : * found or derive the domain from the host bridge.
869 : */
870 0 : for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
871 0 : if (b->self)
872 0 : d = dev_get_msi_domain(&b->self->dev);
873 : }
874 :
875 0 : if (!d)
876 0 : d = pci_host_bridge_msi_domain(b);
877 :
878 0 : dev_set_msi_domain(&bus->dev, d);
879 0 : }
880 :
881 0 : static int pci_register_host_bridge(struct pci_host_bridge *bridge)
882 : {
883 0 : struct device *parent = bridge->dev.parent;
884 : struct resource_entry *window, *next, *n;
885 : struct pci_bus *bus, *b;
886 : resource_size_t offset, next_offset;
887 0 : LIST_HEAD(resources);
888 : struct resource *res, *next_res;
889 : char addr[64], *fmt;
890 : const char *name;
891 : int err;
892 :
893 0 : bus = pci_alloc_bus(NULL);
894 0 : if (!bus)
895 : return -ENOMEM;
896 :
897 0 : bridge->bus = bus;
898 :
899 0 : bus->sysdata = bridge->sysdata;
900 0 : bus->ops = bridge->ops;
901 0 : bus->number = bus->busn_res.start = bridge->busnr;
902 : #ifdef CONFIG_PCI_DOMAINS_GENERIC
903 : if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET)
904 : bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
905 : else
906 : bus->domain_nr = bridge->domain_nr;
907 : if (bus->domain_nr < 0) {
908 : err = bus->domain_nr;
909 : goto free;
910 : }
911 : #endif
912 :
913 0 : b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
914 0 : if (b) {
915 : /* Ignore it if we already got here via a different bridge */
916 : dev_dbg(&b->dev, "bus already known\n");
917 : err = -EEXIST;
918 : goto free;
919 : }
920 :
921 0 : dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
922 : bridge->busnr);
923 :
924 0 : err = pcibios_root_bridge_prepare(bridge);
925 0 : if (err)
926 : goto free;
927 :
928 : /* Temporarily move resources off the list */
929 0 : list_splice_init(&bridge->windows, &resources);
930 0 : err = device_add(&bridge->dev);
931 0 : if (err) {
932 0 : put_device(&bridge->dev);
933 0 : goto free;
934 : }
935 0 : bus->bridge = get_device(&bridge->dev);
936 0 : device_enable_async_suspend(bus->bridge);
937 0 : pci_set_bus_of_node(bus);
938 0 : pci_set_bus_msi_domain(bus);
939 0 : if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) &&
940 0 : !pci_host_of_has_msi_map(parent))
941 0 : bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
942 :
943 : if (!parent)
944 : set_dev_node(bus->bridge, pcibus_to_node(bus));
945 :
946 0 : bus->dev.class = &pcibus_class;
947 0 : bus->dev.parent = bus->bridge;
948 :
949 0 : dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
950 0 : name = dev_name(&bus->dev);
951 :
952 0 : err = device_register(&bus->dev);
953 0 : if (err)
954 : goto unregister;
955 :
956 0 : pcibios_add_bus(bus);
957 :
958 0 : if (bus->ops->add_bus) {
959 0 : err = bus->ops->add_bus(bus);
960 0 : if (WARN_ON(err < 0))
961 0 : dev_err(&bus->dev, "failed to add bus: %d\n", err);
962 : }
963 :
964 : /* Create legacy_io and legacy_mem files for this bus */
965 0 : pci_create_legacy_files(bus);
966 :
967 0 : if (parent)
968 0 : dev_info(parent, "PCI host bridge to bus %s\n", name);
969 : else
970 0 : pr_info("PCI host bridge to bus %s\n", name);
971 :
972 : if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
973 : dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
974 :
975 : /* Coalesce contiguous windows */
976 0 : resource_list_for_each_entry_safe(window, n, &resources) {
977 0 : if (list_is_last(&window->node, &resources))
978 : break;
979 :
980 0 : next = list_next_entry(window, node);
981 0 : offset = window->offset;
982 0 : res = window->res;
983 0 : next_offset = next->offset;
984 0 : next_res = next->res;
985 :
986 0 : if (res->flags != next_res->flags || offset != next_offset)
987 0 : continue;
988 :
989 0 : if (res->end + 1 == next_res->start) {
990 0 : next_res->start = res->start;
991 0 : res->flags = res->start = res->end = 0;
992 : }
993 : }
994 :
995 : /* Add initial resources to the bus */
996 0 : resource_list_for_each_entry_safe(window, n, &resources) {
997 0 : offset = window->offset;
998 0 : res = window->res;
999 0 : if (!res->flags && !res->start && !res->end) {
1000 0 : release_resource(res);
1001 0 : continue;
1002 : }
1003 :
1004 0 : list_move_tail(&window->node, &bridge->windows);
1005 :
1006 0 : if (res->flags & IORESOURCE_BUS)
1007 0 : pci_bus_insert_busn_res(bus, bus->number, res->end);
1008 : else
1009 0 : pci_bus_add_resource(bus, res, 0);
1010 :
1011 0 : if (offset) {
1012 0 : if (resource_type(res) == IORESOURCE_IO)
1013 : fmt = " (bus address [%#06llx-%#06llx])";
1014 : else
1015 0 : fmt = " (bus address [%#010llx-%#010llx])";
1016 :
1017 0 : snprintf(addr, sizeof(addr), fmt,
1018 0 : (unsigned long long)(res->start - offset),
1019 0 : (unsigned long long)(res->end - offset));
1020 : } else
1021 0 : addr[0] = '\0';
1022 :
1023 0 : dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
1024 : }
1025 :
1026 0 : down_write(&pci_bus_sem);
1027 0 : list_add_tail(&bus->node, &pci_root_buses);
1028 0 : up_write(&pci_bus_sem);
1029 :
1030 0 : return 0;
1031 :
1032 : unregister:
1033 0 : put_device(&bridge->dev);
1034 0 : device_del(&bridge->dev);
1035 :
1036 : free:
1037 : #ifdef CONFIG_PCI_DOMAINS_GENERIC
1038 : pci_bus_release_domain_nr(bus, parent);
1039 : #endif
1040 0 : kfree(bus);
1041 0 : return err;
1042 : }
1043 :
1044 0 : static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
1045 : {
1046 : int pos;
1047 : u32 status;
1048 :
1049 : /*
1050 : * If extended config space isn't accessible on a bridge's primary
1051 : * bus, we certainly can't access it on the secondary bus.
1052 : */
1053 0 : if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1054 : return false;
1055 :
1056 : /*
1057 : * PCIe Root Ports and switch ports are PCIe on both sides, so if
1058 : * extended config space is accessible on the primary, it's also
1059 : * accessible on the secondary.
1060 : */
1061 0 : if (pci_is_pcie(bridge) &&
1062 0 : (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1063 0 : pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1064 0 : pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1065 : return true;
1066 :
1067 : /*
1068 : * For the other bridge types:
1069 : * - PCI-to-PCI bridges
1070 : * - PCIe-to-PCI/PCI-X forward bridges
1071 : * - PCI/PCI-X-to-PCIe reverse bridges
1072 : * extended config space on the secondary side is only accessible
1073 : * if the bridge supports PCI-X Mode 2.
1074 : */
1075 0 : pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1076 0 : if (!pos)
1077 : return false;
1078 :
1079 0 : pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1080 0 : return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1081 : }
1082 :
1083 0 : static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1084 : struct pci_dev *bridge, int busnr)
1085 : {
1086 : struct pci_bus *child;
1087 : struct pci_host_bridge *host;
1088 : int i;
1089 : int ret;
1090 :
1091 : /* Allocate a new bus and inherit stuff from the parent */
1092 0 : child = pci_alloc_bus(parent);
1093 0 : if (!child)
1094 : return NULL;
1095 :
1096 0 : child->parent = parent;
1097 0 : child->sysdata = parent->sysdata;
1098 0 : child->bus_flags = parent->bus_flags;
1099 :
1100 0 : host = pci_find_host_bridge(parent);
1101 0 : if (host->child_ops)
1102 0 : child->ops = host->child_ops;
1103 : else
1104 0 : child->ops = parent->ops;
1105 :
1106 : /*
1107 : * Initialize some portions of the bus device, but don't register
1108 : * it now as the parent is not properly set up yet.
1109 : */
1110 0 : child->dev.class = &pcibus_class;
1111 0 : dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1112 :
1113 : /* Set up the primary, secondary and subordinate bus numbers */
1114 0 : child->number = child->busn_res.start = busnr;
1115 0 : child->primary = parent->busn_res.start;
1116 0 : child->busn_res.end = 0xff;
1117 :
1118 0 : if (!bridge) {
1119 0 : child->dev.parent = parent->bridge;
1120 0 : goto add_dev;
1121 : }
1122 :
1123 0 : child->self = bridge;
1124 0 : child->bridge = get_device(&bridge->dev);
1125 0 : child->dev.parent = child->bridge;
1126 0 : pci_set_bus_of_node(child);
1127 0 : pci_set_bus_speed(child);
1128 :
1129 : /*
1130 : * Check whether extended config space is accessible on the child
1131 : * bus. Note that we currently assume it is always accessible on
1132 : * the root bus.
1133 : */
1134 0 : if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1135 0 : child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1136 0 : pci_info(child, "extended config space not accessible\n");
1137 : }
1138 :
1139 : /* Set up default resource pointers and names */
1140 0 : for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1141 0 : child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1142 0 : child->resource[i]->name = child->name;
1143 : }
1144 0 : bridge->subordinate = child;
1145 :
1146 : add_dev:
1147 0 : pci_set_bus_msi_domain(child);
1148 0 : ret = device_register(&child->dev);
1149 0 : WARN_ON(ret < 0);
1150 :
1151 0 : pcibios_add_bus(child);
1152 :
1153 0 : if (child->ops->add_bus) {
1154 0 : ret = child->ops->add_bus(child);
1155 0 : if (WARN_ON(ret < 0))
1156 0 : dev_err(&child->dev, "failed to add bus: %d\n", ret);
1157 : }
1158 :
1159 : /* Create legacy_io and legacy_mem files for this bus */
1160 : pci_create_legacy_files(child);
1161 :
1162 : return child;
1163 : }
1164 :
1165 0 : struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1166 : int busnr)
1167 : {
1168 : struct pci_bus *child;
1169 :
1170 0 : child = pci_alloc_child_bus(parent, dev, busnr);
1171 0 : if (child) {
1172 0 : down_write(&pci_bus_sem);
1173 0 : list_add_tail(&child->node, &parent->children);
1174 0 : up_write(&pci_bus_sem);
1175 : }
1176 0 : return child;
1177 : }
1178 : EXPORT_SYMBOL(pci_add_new_bus);
1179 :
1180 0 : static void pci_enable_crs(struct pci_dev *pdev)
1181 : {
1182 0 : u16 root_cap = 0;
1183 :
1184 : /* Enable CRS Software Visibility if supported */
1185 0 : pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1186 0 : if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1187 : pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1188 : PCI_EXP_RTCTL_CRSSVE);
1189 0 : }
1190 :
1191 : static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1192 : unsigned int available_buses);
1193 : /**
1194 : * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1195 : * numbers from EA capability.
1196 : * @dev: Bridge
1197 : * @sec: updated with secondary bus number from EA
1198 : * @sub: updated with subordinate bus number from EA
1199 : *
1200 : * If @dev is a bridge with EA capability that specifies valid secondary
1201 : * and subordinate bus numbers, return true with the bus numbers in @sec
1202 : * and @sub. Otherwise return false.
1203 : */
1204 0 : static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1205 : {
1206 : int ea, offset;
1207 : u32 dw;
1208 : u8 ea_sec, ea_sub;
1209 :
1210 0 : if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1211 : return false;
1212 :
1213 : /* find PCI EA capability in list */
1214 0 : ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1215 0 : if (!ea)
1216 : return false;
1217 :
1218 0 : offset = ea + PCI_EA_FIRST_ENT;
1219 0 : pci_read_config_dword(dev, offset, &dw);
1220 0 : ea_sec = dw & PCI_EA_SEC_BUS_MASK;
1221 0 : ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1222 0 : if (ea_sec == 0 || ea_sub < ea_sec)
1223 : return false;
1224 :
1225 0 : *sec = ea_sec;
1226 0 : *sub = ea_sub;
1227 0 : return true;
1228 : }
1229 :
1230 : /*
1231 : * pci_scan_bridge_extend() - Scan buses behind a bridge
1232 : * @bus: Parent bus the bridge is on
1233 : * @dev: Bridge itself
1234 : * @max: Starting subordinate number of buses behind this bridge
1235 : * @available_buses: Total number of buses available for this bridge and
1236 : * the devices below. After the minimal bus space has
1237 : * been allocated the remaining buses will be
1238 : * distributed equally between hotplug-capable bridges.
1239 : * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1240 : * that need to be reconfigured.
1241 : *
1242 : * If it's a bridge, configure it and scan the bus behind it.
1243 : * For CardBus bridges, we don't scan behind as the devices will
1244 : * be handled by the bridge driver itself.
1245 : *
1246 : * We need to process bridges in two passes -- first we scan those
1247 : * already configured by the BIOS and after we are done with all of
1248 : * them, we proceed to assigning numbers to the remaining buses in
1249 : * order to avoid overlaps between old and new bus numbers.
1250 : *
1251 : * Return: New subordinate number covering all buses behind this bridge.
1252 : */
1253 0 : static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1254 : int max, unsigned int available_buses,
1255 : int pass)
1256 : {
1257 : struct pci_bus *child;
1258 0 : int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1259 0 : u32 buses, i, j = 0;
1260 : u16 bctl;
1261 : u8 primary, secondary, subordinate;
1262 0 : int broken = 0;
1263 : bool fixed_buses;
1264 : u8 fixed_sec, fixed_sub;
1265 : int next_busnr;
1266 :
1267 : /*
1268 : * Make sure the bridge is powered on to be able to access config
1269 : * space of devices below it.
1270 : */
1271 0 : pm_runtime_get_sync(&dev->dev);
1272 :
1273 0 : pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1274 0 : primary = buses & 0xFF;
1275 0 : secondary = (buses >> 8) & 0xFF;
1276 0 : subordinate = (buses >> 16) & 0xFF;
1277 :
1278 : pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1279 : secondary, subordinate, pass);
1280 :
1281 0 : if (!primary && (primary != bus->number) && secondary && subordinate) {
1282 0 : pci_warn(dev, "Primary bus is hard wired to 0\n");
1283 0 : primary = bus->number;
1284 : }
1285 :
1286 : /* Check if setup is sensible at all */
1287 0 : if (!pass &&
1288 0 : (primary != bus->number || secondary <= bus->number ||
1289 : secondary > subordinate)) {
1290 0 : pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1291 : secondary, subordinate);
1292 0 : broken = 1;
1293 : }
1294 :
1295 : /*
1296 : * Disable Master-Abort Mode during probing to avoid reporting of
1297 : * bus errors in some architectures.
1298 : */
1299 0 : pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1300 0 : pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1301 0 : bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1302 :
1303 0 : pci_enable_crs(dev);
1304 :
1305 : if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1306 : !is_cardbus && !broken) {
1307 : unsigned int cmax, buses;
1308 :
1309 : /*
1310 : * Bus already configured by firmware, process it in the
1311 : * first pass and just note the configuration.
1312 : */
1313 : if (pass)
1314 : goto out;
1315 :
1316 : /*
1317 : * The bus might already exist for two reasons: Either we
1318 : * are rescanning the bus or the bus is reachable through
1319 : * more than one bridge. The second case can happen with
1320 : * the i450NX chipset.
1321 : */
1322 : child = pci_find_bus(pci_domain_nr(bus), secondary);
1323 : if (!child) {
1324 : child = pci_add_new_bus(bus, dev, secondary);
1325 : if (!child)
1326 : goto out;
1327 : child->primary = primary;
1328 : pci_bus_insert_busn_res(child, secondary, subordinate);
1329 : child->bridge_ctl = bctl;
1330 : }
1331 :
1332 : buses = subordinate - secondary;
1333 : cmax = pci_scan_child_bus_extend(child, buses);
1334 : if (cmax > subordinate)
1335 : pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1336 : subordinate, cmax);
1337 :
1338 : /* Subordinate should equal child->busn_res.end */
1339 : if (subordinate > max)
1340 : max = subordinate;
1341 : } else {
1342 :
1343 : /*
1344 : * We need to assign a number to this bus which we always
1345 : * do in the second pass.
1346 : */
1347 0 : if (!pass) {
1348 : if (pcibios_assign_all_busses() || broken || is_cardbus)
1349 :
1350 : /*
1351 : * Temporarily disable forwarding of the
1352 : * configuration cycles on all bridges in
1353 : * this bus segment to avoid possible
1354 : * conflicts in the second pass between two
1355 : * bridges programmed with overlapping bus
1356 : * ranges.
1357 : */
1358 0 : pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1359 : buses & ~0xffffff);
1360 0 : goto out;
1361 : }
1362 :
1363 : /* Clear errors */
1364 0 : pci_write_config_word(dev, PCI_STATUS, 0xffff);
1365 :
1366 : /* Read bus numbers from EA Capability (if present) */
1367 0 : fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1368 0 : if (fixed_buses)
1369 0 : next_busnr = fixed_sec;
1370 : else
1371 0 : next_busnr = max + 1;
1372 :
1373 : /*
1374 : * Prevent assigning a bus number that already exists.
1375 : * This can happen when a bridge is hot-plugged, so in this
1376 : * case we only re-scan this bus.
1377 : */
1378 0 : child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1379 0 : if (!child) {
1380 0 : child = pci_add_new_bus(bus, dev, next_busnr);
1381 0 : if (!child)
1382 : goto out;
1383 0 : pci_bus_insert_busn_res(child, next_busnr,
1384 0 : bus->busn_res.end);
1385 : }
1386 0 : max++;
1387 0 : if (available_buses)
1388 0 : available_buses--;
1389 :
1390 0 : buses = (buses & 0xff000000)
1391 0 : | ((unsigned int)(child->primary) << 0)
1392 0 : | ((unsigned int)(child->busn_res.start) << 8)
1393 0 : | ((unsigned int)(child->busn_res.end) << 16);
1394 :
1395 : /*
1396 : * yenta.c forces a secondary latency timer of 176.
1397 : * Copy that behaviour here.
1398 : */
1399 0 : if (is_cardbus) {
1400 0 : buses &= ~0xff000000;
1401 0 : buses |= CARDBUS_LATENCY_TIMER << 24;
1402 : }
1403 :
1404 : /* We need to blast all three values with a single write */
1405 0 : pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1406 :
1407 0 : if (!is_cardbus) {
1408 0 : child->bridge_ctl = bctl;
1409 0 : max = pci_scan_child_bus_extend(child, available_buses);
1410 : } else {
1411 :
1412 : /*
1413 : * For CardBus bridges, we leave 4 bus numbers as
1414 : * cards with a PCI-to-PCI bridge can be inserted
1415 : * later.
1416 : */
1417 0 : for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1418 0 : struct pci_bus *parent = bus;
1419 0 : if (pci_find_bus(pci_domain_nr(bus),
1420 0 : max+i+1))
1421 : break;
1422 0 : while (parent->parent) {
1423 : if ((!pcibios_assign_all_busses()) &&
1424 : (parent->busn_res.end > max) &&
1425 : (parent->busn_res.end <= max+i)) {
1426 : j = 1;
1427 : }
1428 : parent = parent->parent;
1429 : }
1430 : if (j) {
1431 :
1432 : /*
1433 : * Often, there are two CardBus
1434 : * bridges -- try to leave one
1435 : * valid bus number for each one.
1436 : */
1437 : i /= 2;
1438 : break;
1439 : }
1440 : }
1441 0 : max += i;
1442 : }
1443 :
1444 : /*
1445 : * Set subordinate bus number to its real value.
1446 : * If fixed subordinate bus number exists from EA
1447 : * capability then use it.
1448 : */
1449 0 : if (fixed_buses)
1450 0 : max = fixed_sub;
1451 0 : pci_bus_update_busn_res_end(child, max);
1452 0 : pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1453 : }
1454 :
1455 0 : sprintf(child->name,
1456 : (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1457 0 : pci_domain_nr(bus), child->number);
1458 :
1459 : /* Check that all devices are accessible */
1460 0 : while (bus->parent) {
1461 0 : if ((child->busn_res.end > bus->busn_res.end) ||
1462 0 : (child->number > bus->busn_res.end) ||
1463 0 : (child->number < bus->number) ||
1464 0 : (child->busn_res.end < bus->number)) {
1465 0 : dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1466 : &child->busn_res);
1467 0 : break;
1468 : }
1469 : bus = bus->parent;
1470 : }
1471 :
1472 : out:
1473 0 : pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1474 :
1475 0 : pm_runtime_put(&dev->dev);
1476 :
1477 0 : return max;
1478 : }
1479 :
1480 : /*
1481 : * pci_scan_bridge() - Scan buses behind a bridge
1482 : * @bus: Parent bus the bridge is on
1483 : * @dev: Bridge itself
1484 : * @max: Starting subordinate number of buses behind this bridge
1485 : * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1486 : * that need to be reconfigured.
1487 : *
1488 : * If it's a bridge, configure it and scan the bus behind it.
1489 : * For CardBus bridges, we don't scan behind as the devices will
1490 : * be handled by the bridge driver itself.
1491 : *
1492 : * We need to process bridges in two passes -- first we scan those
1493 : * already configured by the BIOS and after we are done with all of
1494 : * them, we proceed to assigning numbers to the remaining buses in
1495 : * order to avoid overlaps between old and new bus numbers.
1496 : *
1497 : * Return: New subordinate number covering all buses behind this bridge.
1498 : */
1499 0 : int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1500 : {
1501 0 : return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1502 : }
1503 : EXPORT_SYMBOL(pci_scan_bridge);
1504 :
1505 : /*
1506 : * Read interrupt line and base address registers.
1507 : * The architecture-dependent code can tweak these, of course.
1508 : */
1509 0 : static void pci_read_irq(struct pci_dev *dev)
1510 : {
1511 : unsigned char irq;
1512 :
1513 : /* VFs are not allowed to use INTx, so skip the config reads */
1514 0 : if (dev->is_virtfn) {
1515 0 : dev->pin = 0;
1516 0 : dev->irq = 0;
1517 0 : return;
1518 : }
1519 :
1520 0 : pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1521 0 : dev->pin = irq;
1522 0 : if (irq)
1523 0 : pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1524 0 : dev->irq = irq;
1525 : }
1526 :
1527 0 : void set_pcie_port_type(struct pci_dev *pdev)
1528 : {
1529 : int pos;
1530 : u16 reg16;
1531 : u32 reg32;
1532 : int type;
1533 : struct pci_dev *parent;
1534 :
1535 0 : pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1536 0 : if (!pos)
1537 0 : return;
1538 :
1539 0 : pdev->pcie_cap = pos;
1540 0 : pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1541 0 : pdev->pcie_flags_reg = reg16;
1542 0 : pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);
1543 0 : pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);
1544 :
1545 0 : pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
1546 0 : if (reg32 & PCI_EXP_LNKCAP_DLLLARC)
1547 0 : pdev->link_active_reporting = 1;
1548 :
1549 0 : parent = pci_upstream_bridge(pdev);
1550 0 : if (!parent)
1551 : return;
1552 :
1553 : /*
1554 : * Some systems do not identify their upstream/downstream ports
1555 : * correctly so detect impossible configurations here and correct
1556 : * the port type accordingly.
1557 : */
1558 0 : type = pci_pcie_type(pdev);
1559 0 : if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1560 : /*
1561 : * If pdev claims to be downstream port but the parent
1562 : * device is also downstream port assume pdev is actually
1563 : * upstream port.
1564 : */
1565 0 : if (pcie_downstream_port(parent)) {
1566 0 : pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1567 0 : pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1568 0 : pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1569 : }
1570 0 : } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1571 : /*
1572 : * If pdev claims to be upstream port but the parent
1573 : * device is also upstream port assume pdev is actually
1574 : * downstream port.
1575 : */
1576 0 : if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1577 0 : pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1578 0 : pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1579 0 : pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1580 : }
1581 : }
1582 : }
1583 :
1584 0 : void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1585 : {
1586 : u32 reg32;
1587 :
1588 0 : pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1589 0 : if (reg32 & PCI_EXP_SLTCAP_HPC)
1590 0 : pdev->is_hotplug_bridge = 1;
1591 0 : }
1592 :
1593 : static void set_pcie_thunderbolt(struct pci_dev *dev)
1594 : {
1595 : u16 vsec;
1596 :
1597 : /* Is the device part of a Thunderbolt controller? */
1598 0 : vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT);
1599 0 : if (vsec)
1600 0 : dev->is_thunderbolt = 1;
1601 : }
1602 :
1603 : static void set_pcie_untrusted(struct pci_dev *dev)
1604 : {
1605 : struct pci_dev *parent;
1606 :
1607 : /*
1608 : * If the upstream bridge is untrusted we treat this device
1609 : * untrusted as well.
1610 : */
1611 0 : parent = pci_upstream_bridge(dev);
1612 0 : if (parent && (parent->untrusted || parent->external_facing))
1613 0 : dev->untrusted = true;
1614 : }
1615 :
1616 : static void pci_set_removable(struct pci_dev *dev)
1617 : {
1618 0 : struct pci_dev *parent = pci_upstream_bridge(dev);
1619 :
1620 : /*
1621 : * We (only) consider everything downstream from an external_facing
1622 : * device to be removable by the user. We're mainly concerned with
1623 : * consumer platforms with user accessible thunderbolt ports that are
1624 : * vulnerable to DMA attacks, and we expect those ports to be marked by
1625 : * the firmware as external_facing. Devices in traditional hotplug
1626 : * slots can technically be removed, but the expectation is that unless
1627 : * the port is marked with external_facing, such devices are less
1628 : * accessible to user / may not be removed by end user, and thus not
1629 : * exposed as "removable" to userspace.
1630 : */
1631 0 : if (parent &&
1632 0 : (parent->external_facing || dev_is_removable(&parent->dev)))
1633 0 : dev_set_removable(&dev->dev, DEVICE_REMOVABLE);
1634 : }
1635 :
1636 : /**
1637 : * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1638 : * @dev: PCI device
1639 : *
1640 : * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1641 : * when forwarding a type1 configuration request the bridge must check that
1642 : * the extended register address field is zero. The bridge is not permitted
1643 : * to forward the transactions and must handle it as an Unsupported Request.
1644 : * Some bridges do not follow this rule and simply drop the extended register
1645 : * bits, resulting in the standard config space being aliased, every 256
1646 : * bytes across the entire configuration space. Test for this condition by
1647 : * comparing the first dword of each potential alias to the vendor/device ID.
1648 : * Known offenders:
1649 : * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1650 : * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1651 : */
1652 0 : static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1653 : {
1654 : #ifdef CONFIG_PCI_QUIRKS
1655 : int pos;
1656 : u32 header, tmp;
1657 :
1658 0 : pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1659 :
1660 0 : for (pos = PCI_CFG_SPACE_SIZE;
1661 0 : pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1662 0 : if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1663 0 : || header != tmp)
1664 : return false;
1665 : }
1666 :
1667 : return true;
1668 : #else
1669 : return false;
1670 : #endif
1671 : }
1672 :
1673 : /**
1674 : * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1675 : * @dev: PCI device
1676 : *
1677 : * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1678 : * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1679 : * access it. Maybe we don't have a way to generate extended config space
1680 : * accesses, or the device is behind a reverse Express bridge. So we try
1681 : * reading the dword at 0x100 which must either be 0 or a valid extended
1682 : * capability header.
1683 : */
1684 0 : static int pci_cfg_space_size_ext(struct pci_dev *dev)
1685 : {
1686 : u32 status;
1687 0 : int pos = PCI_CFG_SPACE_SIZE;
1688 :
1689 0 : if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1690 : return PCI_CFG_SPACE_SIZE;
1691 0 : if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))
1692 : return PCI_CFG_SPACE_SIZE;
1693 :
1694 : return PCI_CFG_SPACE_EXP_SIZE;
1695 : }
1696 :
1697 0 : int pci_cfg_space_size(struct pci_dev *dev)
1698 : {
1699 : int pos;
1700 : u32 status;
1701 : u16 class;
1702 :
1703 : #ifdef CONFIG_PCI_IOV
1704 : /*
1705 : * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1706 : * implement a PCIe capability and therefore must implement extended
1707 : * config space. We can skip the NO_EXTCFG test below and the
1708 : * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1709 : * the fact that the SR-IOV capability on the PF resides in extended
1710 : * config space and must be accessible and non-aliased to have enabled
1711 : * support for this VF. This is a micro performance optimization for
1712 : * systems supporting many VFs.
1713 : */
1714 : if (dev->is_virtfn)
1715 : return PCI_CFG_SPACE_EXP_SIZE;
1716 : #endif
1717 :
1718 0 : if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1719 : return PCI_CFG_SPACE_SIZE;
1720 :
1721 0 : class = dev->class >> 8;
1722 0 : if (class == PCI_CLASS_BRIDGE_HOST)
1723 0 : return pci_cfg_space_size_ext(dev);
1724 :
1725 0 : if (pci_is_pcie(dev))
1726 0 : return pci_cfg_space_size_ext(dev);
1727 :
1728 0 : pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1729 0 : if (!pos)
1730 : return PCI_CFG_SPACE_SIZE;
1731 :
1732 0 : pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1733 0 : if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1734 0 : return pci_cfg_space_size_ext(dev);
1735 :
1736 : return PCI_CFG_SPACE_SIZE;
1737 : }
1738 :
1739 : static u32 pci_class(struct pci_dev *dev)
1740 : {
1741 : u32 class;
1742 :
1743 : #ifdef CONFIG_PCI_IOV
1744 : if (dev->is_virtfn)
1745 : return dev->physfn->sriov->class;
1746 : #endif
1747 0 : pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1748 0 : return class;
1749 : }
1750 :
1751 : static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1752 : {
1753 : #ifdef CONFIG_PCI_IOV
1754 : if (dev->is_virtfn) {
1755 : *vendor = dev->physfn->sriov->subsystem_vendor;
1756 : *device = dev->physfn->sriov->subsystem_device;
1757 : return;
1758 : }
1759 : #endif
1760 0 : pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1761 0 : pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1762 : }
1763 :
1764 : static u8 pci_hdr_type(struct pci_dev *dev)
1765 : {
1766 : u8 hdr_type;
1767 :
1768 : #ifdef CONFIG_PCI_IOV
1769 : if (dev->is_virtfn)
1770 : return dev->physfn->sriov->hdr_type;
1771 : #endif
1772 0 : pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1773 0 : return hdr_type;
1774 : }
1775 :
1776 : #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1777 :
1778 : /**
1779 : * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1780 : * @dev: PCI device
1781 : *
1782 : * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1783 : * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1784 : */
1785 0 : static int pci_intx_mask_broken(struct pci_dev *dev)
1786 : {
1787 : u16 orig, toggle, new;
1788 :
1789 0 : pci_read_config_word(dev, PCI_COMMAND, &orig);
1790 0 : toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1791 0 : pci_write_config_word(dev, PCI_COMMAND, toggle);
1792 0 : pci_read_config_word(dev, PCI_COMMAND, &new);
1793 :
1794 0 : pci_write_config_word(dev, PCI_COMMAND, orig);
1795 :
1796 : /*
1797 : * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1798 : * r2.3, so strictly speaking, a device is not *broken* if it's not
1799 : * writable. But we'll live with the misnomer for now.
1800 : */
1801 0 : if (new != toggle)
1802 : return 1;
1803 0 : return 0;
1804 : }
1805 :
1806 0 : static void early_dump_pci_device(struct pci_dev *pdev)
1807 : {
1808 : u32 value[256 / 4];
1809 : int i;
1810 :
1811 0 : pci_info(pdev, "config space:\n");
1812 :
1813 0 : for (i = 0; i < 256; i += 4)
1814 0 : pci_read_config_dword(pdev, i, &value[i / 4]);
1815 :
1816 0 : print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1817 : value, 256, false);
1818 0 : }
1819 :
1820 : /**
1821 : * pci_setup_device - Fill in class and map information of a device
1822 : * @dev: the device structure to fill
1823 : *
1824 : * Initialize the device structure with information about the device's
1825 : * vendor,class,memory and IO-space addresses, IRQ lines etc.
1826 : * Called at initialisation of the PCI subsystem and by CardBus services.
1827 : * Returns 0 on success and negative if unknown type of device (not normal,
1828 : * bridge or CardBus).
1829 : */
1830 0 : int pci_setup_device(struct pci_dev *dev)
1831 : {
1832 : u32 class;
1833 : u16 cmd;
1834 : u8 hdr_type;
1835 0 : int err, pos = 0;
1836 : struct pci_bus_region region;
1837 : struct resource *res;
1838 :
1839 0 : hdr_type = pci_hdr_type(dev);
1840 :
1841 0 : dev->sysdata = dev->bus->sysdata;
1842 0 : dev->dev.parent = dev->bus->bridge;
1843 0 : dev->dev.bus = &pci_bus_type;
1844 0 : dev->hdr_type = hdr_type & 0x7f;
1845 0 : dev->multifunction = !!(hdr_type & 0x80);
1846 0 : dev->error_state = pci_channel_io_normal;
1847 0 : set_pcie_port_type(dev);
1848 :
1849 0 : err = pci_set_of_node(dev);
1850 : if (err)
1851 : return err;
1852 0 : pci_set_acpi_fwnode(dev);
1853 :
1854 0 : pci_dev_assign_slot(dev);
1855 :
1856 : /*
1857 : * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1858 : * set this higher, assuming the system even supports it.
1859 : */
1860 0 : dev->dma_mask = 0xffffffff;
1861 :
1862 0 : dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1863 0 : dev->bus->number, PCI_SLOT(dev->devfn),
1864 0 : PCI_FUNC(dev->devfn));
1865 :
1866 0 : class = pci_class(dev);
1867 :
1868 0 : dev->revision = class & 0xff;
1869 0 : dev->class = class >> 8; /* upper 3 bytes */
1870 :
1871 0 : if (pci_early_dump)
1872 0 : early_dump_pci_device(dev);
1873 :
1874 : /* Need to have dev->class ready */
1875 0 : dev->cfg_size = pci_cfg_space_size(dev);
1876 :
1877 : /* Need to have dev->cfg_size ready */
1878 0 : set_pcie_thunderbolt(dev);
1879 :
1880 0 : set_pcie_untrusted(dev);
1881 :
1882 : /* "Unknown power state" */
1883 0 : dev->current_state = PCI_UNKNOWN;
1884 :
1885 : /* Early fixups, before probing the BARs */
1886 0 : pci_fixup_device(pci_fixup_early, dev);
1887 :
1888 0 : pci_set_removable(dev);
1889 :
1890 0 : pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1891 : dev->vendor, dev->device, dev->hdr_type, dev->class);
1892 :
1893 : /* Device class may be changed after fixup */
1894 0 : class = dev->class >> 8;
1895 :
1896 0 : if (dev->non_compliant_bars && !dev->mmio_always_on) {
1897 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
1898 0 : if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1899 0 : pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1900 0 : cmd &= ~PCI_COMMAND_IO;
1901 0 : cmd &= ~PCI_COMMAND_MEMORY;
1902 0 : pci_write_config_word(dev, PCI_COMMAND, cmd);
1903 : }
1904 : }
1905 :
1906 0 : dev->broken_intx_masking = pci_intx_mask_broken(dev);
1907 :
1908 0 : switch (dev->hdr_type) { /* header type */
1909 : case PCI_HEADER_TYPE_NORMAL: /* standard header */
1910 0 : if (class == PCI_CLASS_BRIDGE_PCI)
1911 : goto bad;
1912 0 : pci_read_irq(dev);
1913 0 : pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1914 :
1915 0 : pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1916 :
1917 : /*
1918 : * Do the ugly legacy mode stuff here rather than broken chip
1919 : * quirk code. Legacy mode ATA controllers have fixed
1920 : * addresses. These are not always echoed in BAR0-3, and
1921 : * BAR0-3 in a few cases contain junk!
1922 : */
1923 0 : if (class == PCI_CLASS_STORAGE_IDE) {
1924 : u8 progif;
1925 0 : pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1926 0 : if ((progif & 1) == 0) {
1927 0 : region.start = 0x1F0;
1928 0 : region.end = 0x1F7;
1929 0 : res = &dev->resource[0];
1930 0 : res->flags = LEGACY_IO_RESOURCE;
1931 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
1932 0 : pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1933 : res);
1934 0 : region.start = 0x3F6;
1935 0 : region.end = 0x3F6;
1936 0 : res = &dev->resource[1];
1937 0 : res->flags = LEGACY_IO_RESOURCE;
1938 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
1939 0 : pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1940 : res);
1941 : }
1942 0 : if ((progif & 4) == 0) {
1943 0 : region.start = 0x170;
1944 0 : region.end = 0x177;
1945 0 : res = &dev->resource[2];
1946 0 : res->flags = LEGACY_IO_RESOURCE;
1947 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
1948 0 : pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1949 : res);
1950 0 : region.start = 0x376;
1951 0 : region.end = 0x376;
1952 0 : res = &dev->resource[3];
1953 0 : res->flags = LEGACY_IO_RESOURCE;
1954 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
1955 0 : pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1956 : res);
1957 : }
1958 : }
1959 : break;
1960 :
1961 : case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1962 : /*
1963 : * The PCI-to-PCI bridge spec requires that subtractive
1964 : * decoding (i.e. transparent) bridge must have programming
1965 : * interface code of 0x01.
1966 : */
1967 0 : pci_read_irq(dev);
1968 0 : dev->transparent = ((dev->class & 0xff) == 1);
1969 0 : pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1970 0 : pci_read_bridge_windows(dev);
1971 0 : set_pcie_hotplug_bridge(dev);
1972 0 : pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1973 0 : if (pos) {
1974 0 : pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1975 0 : pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1976 : }
1977 : break;
1978 :
1979 : case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1980 0 : if (class != PCI_CLASS_BRIDGE_CARDBUS)
1981 : goto bad;
1982 0 : pci_read_irq(dev);
1983 0 : pci_read_bases(dev, 1, 0);
1984 0 : pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1985 0 : pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1986 0 : break;
1987 :
1988 : default: /* unknown header */
1989 0 : pci_err(dev, "unknown header type %02x, ignoring device\n",
1990 : dev->hdr_type);
1991 0 : pci_release_of_node(dev);
1992 0 : return -EIO;
1993 :
1994 : bad:
1995 0 : pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1996 : dev->class, dev->hdr_type);
1997 0 : dev->class = PCI_CLASS_NOT_DEFINED << 8;
1998 : }
1999 :
2000 : /* We found a fine healthy device, go go go... */
2001 : return 0;
2002 : }
2003 :
2004 0 : static void pci_configure_mps(struct pci_dev *dev)
2005 : {
2006 0 : struct pci_dev *bridge = pci_upstream_bridge(dev);
2007 : int mps, mpss, p_mps, rc;
2008 :
2009 0 : if (!pci_is_pcie(dev))
2010 : return;
2011 :
2012 : /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
2013 0 : if (dev->is_virtfn)
2014 : return;
2015 :
2016 : /*
2017 : * For Root Complex Integrated Endpoints, program the maximum
2018 : * supported value unless limited by the PCIE_BUS_PEER2PEER case.
2019 : */
2020 0 : if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
2021 0 : if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2022 : mps = 128;
2023 : else
2024 0 : mps = 128 << dev->pcie_mpss;
2025 0 : rc = pcie_set_mps(dev, mps);
2026 0 : if (rc) {
2027 0 : pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2028 : mps);
2029 : }
2030 : return;
2031 : }
2032 :
2033 0 : if (!bridge || !pci_is_pcie(bridge))
2034 : return;
2035 :
2036 0 : mps = pcie_get_mps(dev);
2037 0 : p_mps = pcie_get_mps(bridge);
2038 :
2039 0 : if (mps == p_mps)
2040 : return;
2041 :
2042 0 : if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
2043 0 : pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2044 : mps, pci_name(bridge), p_mps);
2045 0 : return;
2046 : }
2047 :
2048 : /*
2049 : * Fancier MPS configuration is done later by
2050 : * pcie_bus_configure_settings()
2051 : */
2052 0 : if (pcie_bus_config != PCIE_BUS_DEFAULT)
2053 : return;
2054 :
2055 0 : mpss = 128 << dev->pcie_mpss;
2056 0 : if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
2057 0 : pcie_set_mps(bridge, mpss);
2058 0 : pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
2059 : mpss, p_mps, 128 << bridge->pcie_mpss);
2060 0 : p_mps = pcie_get_mps(bridge);
2061 : }
2062 :
2063 0 : rc = pcie_set_mps(dev, p_mps);
2064 0 : if (rc) {
2065 0 : pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2066 : p_mps);
2067 0 : return;
2068 : }
2069 :
2070 0 : pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
2071 : p_mps, mps, mpss);
2072 : }
2073 :
2074 0 : int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2075 : {
2076 : struct pci_host_bridge *host;
2077 : u32 cap;
2078 : u16 ctl;
2079 : int ret;
2080 :
2081 0 : if (!pci_is_pcie(dev))
2082 : return 0;
2083 :
2084 0 : ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2085 0 : if (ret)
2086 : return 0;
2087 :
2088 0 : if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2089 : return 0;
2090 :
2091 0 : ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2092 0 : if (ret)
2093 : return 0;
2094 :
2095 0 : host = pci_find_host_bridge(dev->bus);
2096 0 : if (!host)
2097 : return 0;
2098 :
2099 : /*
2100 : * If some device in the hierarchy doesn't handle Extended Tags
2101 : * correctly, make sure they're disabled.
2102 : */
2103 0 : if (host->no_ext_tags) {
2104 0 : if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2105 0 : pci_info(dev, "disabling Extended Tags\n");
2106 : pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2107 : PCI_EXP_DEVCTL_EXT_TAG);
2108 : }
2109 : return 0;
2110 : }
2111 :
2112 0 : if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2113 0 : pci_info(dev, "enabling Extended Tags\n");
2114 : pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2115 : PCI_EXP_DEVCTL_EXT_TAG);
2116 : }
2117 : return 0;
2118 : }
2119 :
2120 : /**
2121 : * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2122 : * @dev: PCI device to query
2123 : *
2124 : * Returns true if the device has enabled relaxed ordering attribute.
2125 : */
2126 0 : bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2127 : {
2128 : u16 v;
2129 :
2130 0 : pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2131 :
2132 0 : return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2133 : }
2134 : EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2135 :
2136 0 : static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2137 : {
2138 : struct pci_dev *root;
2139 :
2140 : /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2141 0 : if (dev->is_virtfn)
2142 : return;
2143 :
2144 0 : if (!pcie_relaxed_ordering_enabled(dev))
2145 : return;
2146 :
2147 : /*
2148 : * For now, we only deal with Relaxed Ordering issues with Root
2149 : * Ports. Peer-to-Peer DMA is another can of worms.
2150 : */
2151 0 : root = pcie_find_root_port(dev);
2152 0 : if (!root)
2153 : return;
2154 :
2155 0 : if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2156 0 : pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2157 : PCI_EXP_DEVCTL_RELAX_EN);
2158 0 : pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2159 : }
2160 : }
2161 :
2162 0 : static void pci_configure_ltr(struct pci_dev *dev)
2163 : {
2164 : #ifdef CONFIG_PCIEASPM
2165 0 : struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2166 : struct pci_dev *bridge;
2167 : u32 cap, ctl;
2168 :
2169 0 : if (!pci_is_pcie(dev))
2170 0 : return;
2171 :
2172 : /* Read L1 PM substate capabilities */
2173 0 : dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
2174 :
2175 0 : pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2176 0 : if (!(cap & PCI_EXP_DEVCAP2_LTR))
2177 : return;
2178 :
2179 0 : pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2180 0 : if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2181 0 : if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2182 0 : dev->ltr_path = 1;
2183 0 : return;
2184 : }
2185 :
2186 0 : bridge = pci_upstream_bridge(dev);
2187 0 : if (bridge && bridge->ltr_path)
2188 0 : dev->ltr_path = 1;
2189 :
2190 : return;
2191 : }
2192 :
2193 0 : if (!host->native_ltr)
2194 : return;
2195 :
2196 : /*
2197 : * Software must not enable LTR in an Endpoint unless the Root
2198 : * Complex and all intermediate Switches indicate support for LTR.
2199 : * PCIe r4.0, sec 6.18.
2200 : */
2201 0 : if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2202 0 : pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2203 : PCI_EXP_DEVCTL2_LTR_EN);
2204 0 : dev->ltr_path = 1;
2205 0 : return;
2206 : }
2207 :
2208 : /*
2209 : * If we're configuring a hot-added device, LTR was likely
2210 : * disabled in the upstream bridge, so re-enable it before enabling
2211 : * it in the new device.
2212 : */
2213 0 : bridge = pci_upstream_bridge(dev);
2214 0 : if (bridge && bridge->ltr_path) {
2215 0 : pci_bridge_reconfigure_ltr(dev);
2216 0 : pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2217 : PCI_EXP_DEVCTL2_LTR_EN);
2218 0 : dev->ltr_path = 1;
2219 : }
2220 : #endif
2221 : }
2222 :
2223 : static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2224 : {
2225 : #ifdef CONFIG_PCI_PASID
2226 : struct pci_dev *bridge;
2227 : int pcie_type;
2228 : u32 cap;
2229 :
2230 : if (!pci_is_pcie(dev))
2231 : return;
2232 :
2233 : pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2234 : if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2235 : return;
2236 :
2237 : pcie_type = pci_pcie_type(dev);
2238 : if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2239 : pcie_type == PCI_EXP_TYPE_RC_END)
2240 : dev->eetlp_prefix_path = 1;
2241 : else {
2242 : bridge = pci_upstream_bridge(dev);
2243 : if (bridge && bridge->eetlp_prefix_path)
2244 : dev->eetlp_prefix_path = 1;
2245 : }
2246 : #endif
2247 : }
2248 :
2249 0 : static void pci_configure_serr(struct pci_dev *dev)
2250 : {
2251 : u16 control;
2252 :
2253 0 : if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2254 :
2255 : /*
2256 : * A bridge will not forward ERR_ messages coming from an
2257 : * endpoint unless SERR# forwarding is enabled.
2258 : */
2259 0 : pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2260 0 : if (!(control & PCI_BRIDGE_CTL_SERR)) {
2261 0 : control |= PCI_BRIDGE_CTL_SERR;
2262 0 : pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2263 : }
2264 : }
2265 0 : }
2266 :
2267 0 : static void pci_configure_device(struct pci_dev *dev)
2268 : {
2269 0 : pci_configure_mps(dev);
2270 0 : pci_configure_extended_tags(dev, NULL);
2271 0 : pci_configure_relaxed_ordering(dev);
2272 0 : pci_configure_ltr(dev);
2273 0 : pci_configure_eetlp_prefix(dev);
2274 0 : pci_configure_serr(dev);
2275 :
2276 0 : pci_acpi_program_hp_params(dev);
2277 0 : }
2278 :
2279 : static void pci_release_capabilities(struct pci_dev *dev)
2280 : {
2281 0 : pci_aer_exit(dev);
2282 0 : pci_rcec_exit(dev);
2283 0 : pci_iov_release(dev);
2284 0 : pci_free_cap_save_buffers(dev);
2285 : }
2286 :
2287 : /**
2288 : * pci_release_dev - Free a PCI device structure when all users of it are
2289 : * finished
2290 : * @dev: device that's been disconnected
2291 : *
2292 : * Will be called only by the device core when all users of this PCI device are
2293 : * done.
2294 : */
2295 0 : static void pci_release_dev(struct device *dev)
2296 : {
2297 : struct pci_dev *pci_dev;
2298 :
2299 0 : pci_dev = to_pci_dev(dev);
2300 0 : pci_release_capabilities(pci_dev);
2301 0 : pci_release_of_node(pci_dev);
2302 0 : pcibios_release_device(pci_dev);
2303 0 : pci_bus_put(pci_dev->bus);
2304 0 : kfree(pci_dev->driver_override);
2305 0 : bitmap_free(pci_dev->dma_alias_mask);
2306 : dev_dbg(dev, "device released\n");
2307 0 : kfree(pci_dev);
2308 0 : }
2309 :
2310 0 : struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2311 : {
2312 : struct pci_dev *dev;
2313 :
2314 0 : dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2315 0 : if (!dev)
2316 : return NULL;
2317 :
2318 0 : INIT_LIST_HEAD(&dev->bus_list);
2319 0 : dev->dev.type = &pci_dev_type;
2320 0 : dev->bus = pci_bus_get(bus);
2321 0 : dev->driver_exclusive_resource = (struct resource) {
2322 : .name = "PCI Exclusive",
2323 : .start = 0,
2324 : .end = -1,
2325 : };
2326 :
2327 : #ifdef CONFIG_PCI_MSI
2328 : raw_spin_lock_init(&dev->msi_lock);
2329 : #endif
2330 0 : return dev;
2331 : }
2332 : EXPORT_SYMBOL(pci_alloc_dev);
2333 :
2334 : static bool pci_bus_crs_vendor_id(u32 l)
2335 : {
2336 0 : return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
2337 : }
2338 :
2339 0 : static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2340 : int timeout)
2341 : {
2342 0 : int delay = 1;
2343 :
2344 0 : if (!pci_bus_crs_vendor_id(*l))
2345 : return true; /* not a CRS completion */
2346 :
2347 0 : if (!timeout)
2348 : return false; /* CRS, but caller doesn't want to wait */
2349 :
2350 : /*
2351 : * We got the reserved Vendor ID that indicates a completion with
2352 : * Configuration Request Retry Status (CRS). Retry until we get a
2353 : * valid Vendor ID or we time out.
2354 : */
2355 0 : while (pci_bus_crs_vendor_id(*l)) {
2356 0 : if (delay > timeout) {
2357 0 : pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2358 : pci_domain_nr(bus), bus->number,
2359 : PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2360 :
2361 0 : return false;
2362 : }
2363 0 : if (delay >= 1000)
2364 0 : pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2365 : pci_domain_nr(bus), bus->number,
2366 : PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2367 :
2368 0 : msleep(delay);
2369 0 : delay *= 2;
2370 :
2371 0 : if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2372 : return false;
2373 : }
2374 :
2375 0 : if (delay >= 1000)
2376 0 : pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2377 : pci_domain_nr(bus), bus->number,
2378 : PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2379 :
2380 : return true;
2381 : }
2382 :
2383 0 : bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2384 : int timeout)
2385 : {
2386 0 : if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2387 : return false;
2388 :
2389 : /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
2390 0 : if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||
2391 0 : *l == 0x0000ffff || *l == 0xffff0000)
2392 : return false;
2393 :
2394 0 : if (pci_bus_crs_vendor_id(*l))
2395 0 : return pci_bus_wait_crs(bus, devfn, l, timeout);
2396 :
2397 : return true;
2398 : }
2399 :
2400 0 : bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2401 : int timeout)
2402 : {
2403 : #ifdef CONFIG_PCI_QUIRKS
2404 0 : struct pci_dev *bridge = bus->self;
2405 :
2406 : /*
2407 : * Certain IDT switches have an issue where they improperly trigger
2408 : * ACS Source Validation errors on completions for config reads.
2409 : */
2410 0 : if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2411 : bridge->device == 0x80b5)
2412 0 : return pci_idt_bus_quirk(bus, devfn, l, timeout);
2413 : #endif
2414 :
2415 0 : return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2416 : }
2417 : EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2418 :
2419 : /*
2420 : * Read the config data for a PCI device, sanity-check it,
2421 : * and fill in the dev structure.
2422 : */
2423 0 : static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2424 : {
2425 : struct pci_dev *dev;
2426 : u32 l;
2427 :
2428 0 : if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2429 : return NULL;
2430 :
2431 0 : dev = pci_alloc_dev(bus);
2432 0 : if (!dev)
2433 : return NULL;
2434 :
2435 0 : dev->devfn = devfn;
2436 0 : dev->vendor = l & 0xffff;
2437 0 : dev->device = (l >> 16) & 0xffff;
2438 :
2439 0 : if (pci_setup_device(dev)) {
2440 0 : pci_bus_put(dev->bus);
2441 0 : kfree(dev);
2442 0 : return NULL;
2443 : }
2444 :
2445 : return dev;
2446 : }
2447 :
2448 0 : void pcie_report_downtraining(struct pci_dev *dev)
2449 : {
2450 0 : if (!pci_is_pcie(dev))
2451 : return;
2452 :
2453 : /* Look from the device up to avoid downstream ports with no devices */
2454 0 : if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2455 0 : (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2456 0 : (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2457 : return;
2458 :
2459 : /* Multi-function PCIe devices share the same link/status */
2460 0 : if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2461 : return;
2462 :
2463 : /* Print link status only if the device is constrained by the fabric */
2464 0 : __pcie_print_link_status(dev, false);
2465 : }
2466 :
2467 0 : static void pci_init_capabilities(struct pci_dev *dev)
2468 : {
2469 0 : pci_ea_init(dev); /* Enhanced Allocation */
2470 0 : pci_msi_init(dev); /* Disable MSI */
2471 0 : pci_msix_init(dev); /* Disable MSI-X */
2472 :
2473 : /* Buffers for saving PCIe and PCI-X capabilities */
2474 0 : pci_allocate_cap_save_buffers(dev);
2475 :
2476 0 : pci_pm_init(dev); /* Power Management */
2477 0 : pci_vpd_init(dev); /* Vital Product Data */
2478 0 : pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */
2479 0 : pci_iov_init(dev); /* Single Root I/O Virtualization */
2480 0 : pci_ats_init(dev); /* Address Translation Services */
2481 0 : pci_pri_init(dev); /* Page Request Interface */
2482 0 : pci_pasid_init(dev); /* Process Address Space ID */
2483 0 : pci_acs_init(dev); /* Access Control Services */
2484 0 : pci_ptm_init(dev); /* Precision Time Measurement */
2485 0 : pci_aer_init(dev); /* Advanced Error Reporting */
2486 0 : pci_dpc_init(dev); /* Downstream Port Containment */
2487 0 : pci_rcec_init(dev); /* Root Complex Event Collector */
2488 0 : pci_doe_init(dev); /* Data Object Exchange */
2489 :
2490 0 : pcie_report_downtraining(dev);
2491 0 : pci_init_reset_methods(dev);
2492 0 : }
2493 :
2494 : /*
2495 : * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2496 : * devices. Firmware interfaces that can select the MSI domain on a
2497 : * per-device basis should be called from here.
2498 : */
2499 : static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2500 : {
2501 : struct irq_domain *d;
2502 :
2503 : /*
2504 : * If a domain has been set through the pcibios_device_add()
2505 : * callback, then this is the one (platform code knows best).
2506 : */
2507 0 : d = dev_get_msi_domain(&dev->dev);
2508 0 : if (d)
2509 : return d;
2510 :
2511 : /*
2512 : * Let's see if we have a firmware interface able to provide
2513 : * the domain.
2514 : */
2515 0 : d = pci_msi_get_device_domain(dev);
2516 0 : if (d)
2517 : return d;
2518 :
2519 : return NULL;
2520 : }
2521 :
2522 0 : static void pci_set_msi_domain(struct pci_dev *dev)
2523 : {
2524 : struct irq_domain *d;
2525 :
2526 : /*
2527 : * If the platform or firmware interfaces cannot supply a
2528 : * device-specific MSI domain, then inherit the default domain
2529 : * from the host bridge itself.
2530 : */
2531 0 : d = pci_dev_msi_domain(dev);
2532 0 : if (!d)
2533 0 : d = dev_get_msi_domain(&dev->bus->dev);
2534 :
2535 0 : dev_set_msi_domain(&dev->dev, d);
2536 0 : }
2537 :
2538 0 : void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2539 : {
2540 : int ret;
2541 :
2542 0 : pci_configure_device(dev);
2543 :
2544 0 : device_initialize(&dev->dev);
2545 0 : dev->dev.release = pci_release_dev;
2546 :
2547 0 : set_dev_node(&dev->dev, pcibus_to_node(bus));
2548 0 : dev->dev.dma_mask = &dev->dma_mask;
2549 0 : dev->dev.dma_parms = &dev->dma_parms;
2550 0 : dev->dev.coherent_dma_mask = 0xffffffffull;
2551 :
2552 0 : dma_set_max_seg_size(&dev->dev, 65536);
2553 0 : dma_set_seg_boundary(&dev->dev, 0xffffffff);
2554 :
2555 0 : pcie_failed_link_retrain(dev);
2556 :
2557 : /* Fix up broken headers */
2558 0 : pci_fixup_device(pci_fixup_header, dev);
2559 :
2560 0 : pci_reassigndev_resource_alignment(dev);
2561 :
2562 0 : dev->state_saved = false;
2563 :
2564 0 : pci_init_capabilities(dev);
2565 :
2566 : /*
2567 : * Add the device to our list of discovered devices
2568 : * and the bus list for fixup functions, etc.
2569 : */
2570 0 : down_write(&pci_bus_sem);
2571 0 : list_add_tail(&dev->bus_list, &bus->devices);
2572 0 : up_write(&pci_bus_sem);
2573 :
2574 0 : ret = pcibios_device_add(dev);
2575 0 : WARN_ON(ret < 0);
2576 :
2577 : /* Set up MSI IRQ domain */
2578 0 : pci_set_msi_domain(dev);
2579 :
2580 : /* Notifier could use PCI capabilities */
2581 0 : dev->match_driver = false;
2582 0 : ret = device_add(&dev->dev);
2583 0 : WARN_ON(ret < 0);
2584 0 : }
2585 :
2586 0 : struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2587 : {
2588 : struct pci_dev *dev;
2589 :
2590 0 : dev = pci_get_slot(bus, devfn);
2591 0 : if (dev) {
2592 0 : pci_dev_put(dev);
2593 0 : return dev;
2594 : }
2595 :
2596 0 : dev = pci_scan_device(bus, devfn);
2597 0 : if (!dev)
2598 : return NULL;
2599 :
2600 0 : pci_device_add(dev, bus);
2601 :
2602 0 : return dev;
2603 : }
2604 : EXPORT_SYMBOL(pci_scan_single_device);
2605 :
2606 0 : static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2607 : {
2608 : int pos;
2609 0 : u16 cap = 0;
2610 : unsigned int next_fn;
2611 :
2612 0 : if (!dev)
2613 : return -ENODEV;
2614 :
2615 0 : pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2616 0 : if (!pos)
2617 : return -ENODEV;
2618 :
2619 0 : pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2620 0 : next_fn = PCI_ARI_CAP_NFN(cap);
2621 0 : if (next_fn <= fn)
2622 : return -ENODEV; /* protect against malformed list */
2623 :
2624 0 : return next_fn;
2625 : }
2626 :
2627 0 : static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2628 : {
2629 0 : if (pci_ari_enabled(bus))
2630 0 : return next_ari_fn(bus, dev, fn);
2631 :
2632 0 : if (fn >= 7)
2633 : return -ENODEV;
2634 : /* only multifunction devices may have more functions */
2635 0 : if (dev && !dev->multifunction)
2636 : return -ENODEV;
2637 :
2638 0 : return fn + 1;
2639 : }
2640 :
2641 0 : static int only_one_child(struct pci_bus *bus)
2642 : {
2643 0 : struct pci_dev *bridge = bus->self;
2644 :
2645 : /*
2646 : * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2647 : * we scan for all possible devices, not just Device 0.
2648 : */
2649 0 : if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2650 : return 0;
2651 :
2652 : /*
2653 : * A PCIe Downstream Port normally leads to a Link with only Device
2654 : * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2655 : * only for Device 0 in that situation.
2656 : */
2657 0 : if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2658 : return 1;
2659 :
2660 : return 0;
2661 : }
2662 :
2663 : /**
2664 : * pci_scan_slot - Scan a PCI slot on a bus for devices
2665 : * @bus: PCI bus to scan
2666 : * @devfn: slot number to scan (must have zero function)
2667 : *
2668 : * Scan a PCI slot on the specified PCI bus for devices, adding
2669 : * discovered devices to the @bus->devices list. New devices
2670 : * will not have is_added set.
2671 : *
2672 : * Returns the number of new devices found.
2673 : */
2674 0 : int pci_scan_slot(struct pci_bus *bus, int devfn)
2675 : {
2676 : struct pci_dev *dev;
2677 0 : int fn = 0, nr = 0;
2678 :
2679 0 : if (only_one_child(bus) && (devfn > 0))
2680 : return 0; /* Already scanned the entire slot */
2681 :
2682 : do {
2683 0 : dev = pci_scan_single_device(bus, devfn + fn);
2684 0 : if (dev) {
2685 0 : if (!pci_dev_is_added(dev))
2686 0 : nr++;
2687 0 : if (fn > 0)
2688 0 : dev->multifunction = 1;
2689 0 : } else if (fn == 0) {
2690 : /*
2691 : * Function 0 is required unless we are running on
2692 : * a hypervisor that passes through individual PCI
2693 : * functions.
2694 : */
2695 : if (!hypervisor_isolated_pci_functions())
2696 : break;
2697 : }
2698 0 : fn = next_fn(bus, dev, fn);
2699 0 : } while (fn >= 0);
2700 :
2701 : /* Only one slot has PCIe device */
2702 0 : if (bus->self && nr)
2703 0 : pcie_aspm_init_link_state(bus->self);
2704 :
2705 : return nr;
2706 : }
2707 : EXPORT_SYMBOL(pci_scan_slot);
2708 :
2709 0 : static int pcie_find_smpss(struct pci_dev *dev, void *data)
2710 : {
2711 0 : u8 *smpss = data;
2712 :
2713 0 : if (!pci_is_pcie(dev))
2714 : return 0;
2715 :
2716 : /*
2717 : * We don't have a way to change MPS settings on devices that have
2718 : * drivers attached. A hot-added device might support only the minimum
2719 : * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2720 : * where devices may be hot-added, we limit the fabric MPS to 128 so
2721 : * hot-added devices will work correctly.
2722 : *
2723 : * However, if we hot-add a device to a slot directly below a Root
2724 : * Port, it's impossible for there to be other existing devices below
2725 : * the port. We don't limit the MPS in this case because we can
2726 : * reconfigure MPS on both the Root Port and the hot-added device,
2727 : * and there are no other devices involved.
2728 : *
2729 : * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2730 : */
2731 0 : if (dev->is_hotplug_bridge &&
2732 0 : pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2733 0 : *smpss = 0;
2734 :
2735 0 : if (*smpss > dev->pcie_mpss)
2736 0 : *smpss = dev->pcie_mpss;
2737 :
2738 : return 0;
2739 : }
2740 :
2741 0 : static void pcie_write_mps(struct pci_dev *dev, int mps)
2742 : {
2743 : int rc;
2744 :
2745 0 : if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2746 0 : mps = 128 << dev->pcie_mpss;
2747 :
2748 0 : if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2749 0 : dev->bus->self)
2750 :
2751 : /*
2752 : * For "Performance", the assumption is made that
2753 : * downstream communication will never be larger than
2754 : * the MRRS. So, the MPS only needs to be configured
2755 : * for the upstream communication. This being the case,
2756 : * walk from the top down and set the MPS of the child
2757 : * to that of the parent bus.
2758 : *
2759 : * Configure the device MPS with the smaller of the
2760 : * device MPSS or the bridge MPS (which is assumed to be
2761 : * properly configured at this point to the largest
2762 : * allowable MPS based on its parent bus).
2763 : */
2764 0 : mps = min(mps, pcie_get_mps(dev->bus->self));
2765 : }
2766 :
2767 0 : rc = pcie_set_mps(dev, mps);
2768 0 : if (rc)
2769 0 : pci_err(dev, "Failed attempting to set the MPS\n");
2770 0 : }
2771 :
2772 0 : static void pcie_write_mrrs(struct pci_dev *dev)
2773 : {
2774 : int rc, mrrs;
2775 :
2776 : /*
2777 : * In the "safe" case, do not configure the MRRS. There appear to be
2778 : * issues with setting MRRS to 0 on a number of devices.
2779 : */
2780 0 : if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2781 : return;
2782 :
2783 : /*
2784 : * For max performance, the MRRS must be set to the largest supported
2785 : * value. However, it cannot be configured larger than the MPS the
2786 : * device or the bus can support. This should already be properly
2787 : * configured by a prior call to pcie_write_mps().
2788 : */
2789 0 : mrrs = pcie_get_mps(dev);
2790 :
2791 : /*
2792 : * MRRS is a R/W register. Invalid values can be written, but a
2793 : * subsequent read will verify if the value is acceptable or not.
2794 : * If the MRRS value provided is not acceptable (e.g., too large),
2795 : * shrink the value until it is acceptable to the HW.
2796 : */
2797 0 : while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2798 0 : rc = pcie_set_readrq(dev, mrrs);
2799 0 : if (!rc)
2800 : break;
2801 :
2802 0 : pci_warn(dev, "Failed attempting to set the MRRS\n");
2803 0 : mrrs /= 2;
2804 : }
2805 :
2806 0 : if (mrrs < 128)
2807 0 : pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2808 : }
2809 :
2810 0 : static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2811 : {
2812 : int mps, orig_mps;
2813 :
2814 0 : if (!pci_is_pcie(dev))
2815 : return 0;
2816 :
2817 0 : if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2818 : pcie_bus_config == PCIE_BUS_DEFAULT)
2819 : return 0;
2820 :
2821 0 : mps = 128 << *(u8 *)data;
2822 0 : orig_mps = pcie_get_mps(dev);
2823 :
2824 0 : pcie_write_mps(dev, mps);
2825 0 : pcie_write_mrrs(dev);
2826 :
2827 0 : pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2828 : pcie_get_mps(dev), 128 << dev->pcie_mpss,
2829 : orig_mps, pcie_get_readrq(dev));
2830 :
2831 0 : return 0;
2832 : }
2833 :
2834 : /*
2835 : * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2836 : * parents then children fashion. If this changes, then this code will not
2837 : * work as designed.
2838 : */
2839 0 : void pcie_bus_configure_settings(struct pci_bus *bus)
2840 : {
2841 0 : u8 smpss = 0;
2842 :
2843 0 : if (!bus->self)
2844 0 : return;
2845 :
2846 0 : if (!pci_is_pcie(bus->self))
2847 : return;
2848 :
2849 : /*
2850 : * FIXME - Peer to peer DMA is possible, though the endpoint would need
2851 : * to be aware of the MPS of the destination. To work around this,
2852 : * simply force the MPS of the entire system to the smallest possible.
2853 : */
2854 0 : if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2855 : smpss = 0;
2856 :
2857 0 : if (pcie_bus_config == PCIE_BUS_SAFE) {
2858 0 : smpss = bus->self->pcie_mpss;
2859 :
2860 0 : pcie_find_smpss(bus->self, &smpss);
2861 0 : pci_walk_bus(bus, pcie_find_smpss, &smpss);
2862 : }
2863 :
2864 0 : pcie_bus_configure_set(bus->self, &smpss);
2865 0 : pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2866 : }
2867 : EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2868 :
2869 : /*
2870 : * Called after each bus is probed, but before its children are examined. This
2871 : * is marked as __weak because multiple architectures define it.
2872 : */
2873 0 : void __weak pcibios_fixup_bus(struct pci_bus *bus)
2874 : {
2875 : /* nothing to do, expected to be removed in the future */
2876 0 : }
2877 :
2878 : /**
2879 : * pci_scan_child_bus_extend() - Scan devices below a bus
2880 : * @bus: Bus to scan for devices
2881 : * @available_buses: Total number of buses available (%0 does not try to
2882 : * extend beyond the minimal)
2883 : *
2884 : * Scans devices below @bus including subordinate buses. Returns new
2885 : * subordinate number including all the found devices. Passing
2886 : * @available_buses causes the remaining bus space to be distributed
2887 : * equally between hotplug-capable bridges to allow future extension of the
2888 : * hierarchy.
2889 : */
2890 0 : static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2891 : unsigned int available_buses)
2892 : {
2893 0 : unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2894 0 : unsigned int start = bus->busn_res.start;
2895 0 : unsigned int devfn, cmax, max = start;
2896 : struct pci_dev *dev;
2897 :
2898 : dev_dbg(&bus->dev, "scanning bus\n");
2899 :
2900 : /* Go find them, Rover! */
2901 0 : for (devfn = 0; devfn < 256; devfn += 8)
2902 0 : pci_scan_slot(bus, devfn);
2903 :
2904 : /* Reserve buses for SR-IOV capability */
2905 0 : used_buses = pci_iov_bus_range(bus);
2906 0 : max += used_buses;
2907 :
2908 : /*
2909 : * After performing arch-dependent fixup of the bus, look behind
2910 : * all PCI-to-PCI bridges on this bus.
2911 : */
2912 0 : if (!bus->is_added) {
2913 : dev_dbg(&bus->dev, "fixups for bus\n");
2914 0 : pcibios_fixup_bus(bus);
2915 0 : bus->is_added = 1;
2916 : }
2917 :
2918 : /*
2919 : * Calculate how many hotplug bridges and normal bridges there
2920 : * are on this bus. We will distribute the additional available
2921 : * buses between hotplug bridges.
2922 : */
2923 0 : for_each_pci_bridge(dev, bus) {
2924 0 : if (dev->is_hotplug_bridge)
2925 0 : hotplug_bridges++;
2926 : else
2927 0 : normal_bridges++;
2928 : }
2929 :
2930 : /*
2931 : * Scan bridges that are already configured. We don't touch them
2932 : * unless they are misconfigured (which will be done in the second
2933 : * scan below).
2934 : */
2935 0 : for_each_pci_bridge(dev, bus) {
2936 0 : cmax = max;
2937 0 : max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2938 :
2939 : /*
2940 : * Reserve one bus for each bridge now to avoid extending
2941 : * hotplug bridges too much during the second scan below.
2942 : */
2943 0 : used_buses++;
2944 0 : if (max - cmax > 1)
2945 0 : used_buses += max - cmax - 1;
2946 : }
2947 :
2948 : /* Scan bridges that need to be reconfigured */
2949 0 : for_each_pci_bridge(dev, bus) {
2950 0 : unsigned int buses = 0;
2951 :
2952 0 : if (!hotplug_bridges && normal_bridges == 1) {
2953 : /*
2954 : * There is only one bridge on the bus (upstream
2955 : * port) so it gets all available buses which it
2956 : * can then distribute to the possible hotplug
2957 : * bridges below.
2958 : */
2959 : buses = available_buses;
2960 0 : } else if (dev->is_hotplug_bridge) {
2961 : /*
2962 : * Distribute the extra buses between hotplug
2963 : * bridges if any.
2964 : */
2965 0 : buses = available_buses / hotplug_bridges;
2966 0 : buses = min(buses, available_buses - used_buses + 1);
2967 : }
2968 :
2969 0 : cmax = max;
2970 0 : max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2971 : /* One bus is already accounted so don't add it again */
2972 0 : if (max - cmax > 1)
2973 0 : used_buses += max - cmax - 1;
2974 : }
2975 :
2976 : /*
2977 : * Make sure a hotplug bridge has at least the minimum requested
2978 : * number of buses but allow it to grow up to the maximum available
2979 : * bus number if there is room.
2980 : */
2981 0 : if (bus->self && bus->self->is_hotplug_bridge) {
2982 0 : used_buses = max_t(unsigned int, available_buses,
2983 : pci_hotplug_bus_size - 1);
2984 0 : if (max - start < used_buses) {
2985 0 : max = start + used_buses;
2986 :
2987 : /* Do not allocate more buses than we have room left */
2988 0 : if (max > bus->busn_res.end)
2989 0 : max = bus->busn_res.end;
2990 :
2991 : dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2992 : &bus->busn_res, max - start);
2993 : }
2994 : }
2995 :
2996 : /*
2997 : * We've scanned the bus and so we know all about what's on
2998 : * the other side of any bridges that may be on this bus plus
2999 : * any devices.
3000 : *
3001 : * Return how far we've got finding sub-buses.
3002 : */
3003 : dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
3004 0 : return max;
3005 : }
3006 :
3007 : /**
3008 : * pci_scan_child_bus() - Scan devices below a bus
3009 : * @bus: Bus to scan for devices
3010 : *
3011 : * Scans devices below @bus including subordinate buses. Returns new
3012 : * subordinate number including all the found devices.
3013 : */
3014 0 : unsigned int pci_scan_child_bus(struct pci_bus *bus)
3015 : {
3016 0 : return pci_scan_child_bus_extend(bus, 0);
3017 : }
3018 : EXPORT_SYMBOL_GPL(pci_scan_child_bus);
3019 :
3020 : /**
3021 : * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3022 : * @bridge: Host bridge to set up
3023 : *
3024 : * Default empty implementation. Replace with an architecture-specific setup
3025 : * routine, if necessary.
3026 : */
3027 0 : int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
3028 : {
3029 0 : return 0;
3030 : }
3031 :
3032 0 : void __weak pcibios_add_bus(struct pci_bus *bus)
3033 : {
3034 0 : }
3035 :
3036 0 : void __weak pcibios_remove_bus(struct pci_bus *bus)
3037 : {
3038 0 : }
3039 :
3040 0 : struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
3041 : struct pci_ops *ops, void *sysdata, struct list_head *resources)
3042 : {
3043 : int error;
3044 : struct pci_host_bridge *bridge;
3045 :
3046 0 : bridge = pci_alloc_host_bridge(0);
3047 0 : if (!bridge)
3048 : return NULL;
3049 :
3050 0 : bridge->dev.parent = parent;
3051 :
3052 0 : list_splice_init(resources, &bridge->windows);
3053 0 : bridge->sysdata = sysdata;
3054 0 : bridge->busnr = bus;
3055 0 : bridge->ops = ops;
3056 :
3057 0 : error = pci_register_host_bridge(bridge);
3058 0 : if (error < 0)
3059 : goto err_out;
3060 :
3061 0 : return bridge->bus;
3062 :
3063 : err_out:
3064 0 : put_device(&bridge->dev);
3065 0 : return NULL;
3066 : }
3067 : EXPORT_SYMBOL_GPL(pci_create_root_bus);
3068 :
3069 0 : int pci_host_probe(struct pci_host_bridge *bridge)
3070 : {
3071 : struct pci_bus *bus, *child;
3072 : int ret;
3073 :
3074 0 : ret = pci_scan_root_bus_bridge(bridge);
3075 0 : if (ret < 0) {
3076 0 : dev_err(bridge->dev.parent, "Scanning root bridge failed");
3077 0 : return ret;
3078 : }
3079 :
3080 0 : bus = bridge->bus;
3081 :
3082 : /*
3083 : * We insert PCI resources into the iomem_resource and
3084 : * ioport_resource trees in either pci_bus_claim_resources()
3085 : * or pci_bus_assign_resources().
3086 : */
3087 0 : if (pci_has_flag(PCI_PROBE_ONLY)) {
3088 0 : pci_bus_claim_resources(bus);
3089 : } else {
3090 0 : pci_bus_size_bridges(bus);
3091 0 : pci_bus_assign_resources(bus);
3092 :
3093 0 : list_for_each_entry(child, &bus->children, node)
3094 0 : pcie_bus_configure_settings(child);
3095 : }
3096 :
3097 0 : pci_bus_add_devices(bus);
3098 0 : return 0;
3099 : }
3100 : EXPORT_SYMBOL_GPL(pci_host_probe);
3101 :
3102 0 : int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3103 : {
3104 0 : struct resource *res = &b->busn_res;
3105 : struct resource *parent_res, *conflict;
3106 :
3107 0 : res->start = bus;
3108 0 : res->end = bus_max;
3109 0 : res->flags = IORESOURCE_BUS;
3110 :
3111 0 : if (!pci_is_root_bus(b))
3112 0 : parent_res = &b->parent->busn_res;
3113 : else {
3114 0 : parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3115 0 : res->flags |= IORESOURCE_PCI_FIXED;
3116 : }
3117 :
3118 0 : conflict = request_resource_conflict(parent_res, res);
3119 :
3120 0 : if (conflict)
3121 0 : dev_info(&b->dev,
3122 : "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3123 : res, pci_is_root_bus(b) ? "domain " : "",
3124 : parent_res, conflict->name, conflict);
3125 :
3126 0 : return conflict == NULL;
3127 : }
3128 :
3129 0 : int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3130 : {
3131 0 : struct resource *res = &b->busn_res;
3132 0 : struct resource old_res = *res;
3133 : resource_size_t size;
3134 : int ret;
3135 :
3136 0 : if (res->start > bus_max)
3137 : return -EINVAL;
3138 :
3139 0 : size = bus_max - res->start + 1;
3140 0 : ret = adjust_resource(res, res->start, size);
3141 0 : dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3142 : &old_res, ret ? "can not be" : "is", bus_max);
3143 :
3144 0 : if (!ret && !res->parent)
3145 0 : pci_bus_insert_busn_res(b, res->start, res->end);
3146 :
3147 : return ret;
3148 : }
3149 :
3150 0 : void pci_bus_release_busn_res(struct pci_bus *b)
3151 : {
3152 0 : struct resource *res = &b->busn_res;
3153 : int ret;
3154 :
3155 0 : if (!res->flags || !res->parent)
3156 : return;
3157 :
3158 0 : ret = release_resource(res);
3159 0 : dev_info(&b->dev, "busn_res: %pR %s released\n",
3160 : res, ret ? "can not be" : "is");
3161 : }
3162 :
3163 0 : int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3164 : {
3165 : struct resource_entry *window;
3166 0 : bool found = false;
3167 : struct pci_bus *b;
3168 : int max, bus, ret;
3169 :
3170 0 : if (!bridge)
3171 : return -EINVAL;
3172 :
3173 0 : resource_list_for_each_entry(window, &bridge->windows)
3174 0 : if (window->res->flags & IORESOURCE_BUS) {
3175 0 : bridge->busnr = window->res->start;
3176 0 : found = true;
3177 0 : break;
3178 : }
3179 :
3180 0 : ret = pci_register_host_bridge(bridge);
3181 0 : if (ret < 0)
3182 : return ret;
3183 :
3184 0 : b = bridge->bus;
3185 0 : bus = bridge->busnr;
3186 :
3187 0 : if (!found) {
3188 0 : dev_info(&b->dev,
3189 : "No busn resource found for root bus, will use [bus %02x-ff]\n",
3190 : bus);
3191 0 : pci_bus_insert_busn_res(b, bus, 255);
3192 : }
3193 :
3194 0 : max = pci_scan_child_bus(b);
3195 :
3196 0 : if (!found)
3197 0 : pci_bus_update_busn_res_end(b, max);
3198 :
3199 : return 0;
3200 : }
3201 : EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3202 :
3203 0 : struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3204 : struct pci_ops *ops, void *sysdata, struct list_head *resources)
3205 : {
3206 : struct resource_entry *window;
3207 0 : bool found = false;
3208 : struct pci_bus *b;
3209 : int max;
3210 :
3211 0 : resource_list_for_each_entry(window, resources)
3212 0 : if (window->res->flags & IORESOURCE_BUS) {
3213 : found = true;
3214 : break;
3215 : }
3216 :
3217 0 : b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3218 0 : if (!b)
3219 : return NULL;
3220 :
3221 0 : if (!found) {
3222 0 : dev_info(&b->dev,
3223 : "No busn resource found for root bus, will use [bus %02x-ff]\n",
3224 : bus);
3225 0 : pci_bus_insert_busn_res(b, bus, 255);
3226 : }
3227 :
3228 0 : max = pci_scan_child_bus(b);
3229 :
3230 0 : if (!found)
3231 0 : pci_bus_update_busn_res_end(b, max);
3232 :
3233 : return b;
3234 : }
3235 : EXPORT_SYMBOL(pci_scan_root_bus);
3236 :
3237 0 : struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3238 : void *sysdata)
3239 : {
3240 0 : LIST_HEAD(resources);
3241 : struct pci_bus *b;
3242 :
3243 0 : pci_add_resource(&resources, &ioport_resource);
3244 0 : pci_add_resource(&resources, &iomem_resource);
3245 0 : pci_add_resource(&resources, &busn_resource);
3246 0 : b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3247 0 : if (b) {
3248 : pci_scan_child_bus(b);
3249 : } else {
3250 0 : pci_free_resource_list(&resources);
3251 : }
3252 0 : return b;
3253 : }
3254 : EXPORT_SYMBOL(pci_scan_bus);
3255 :
3256 : /**
3257 : * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3258 : * @bridge: PCI bridge for the bus to scan
3259 : *
3260 : * Scan a PCI bus and child buses for new devices, add them,
3261 : * and enable them, resizing bridge mmio/io resource if necessary
3262 : * and possible. The caller must ensure the child devices are already
3263 : * removed for resizing to occur.
3264 : *
3265 : * Returns the max number of subordinate bus discovered.
3266 : */
3267 0 : unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3268 : {
3269 : unsigned int max;
3270 0 : struct pci_bus *bus = bridge->subordinate;
3271 :
3272 0 : max = pci_scan_child_bus(bus);
3273 :
3274 0 : pci_assign_unassigned_bridge_resources(bridge);
3275 :
3276 0 : pci_bus_add_devices(bus);
3277 :
3278 0 : return max;
3279 : }
3280 :
3281 : /**
3282 : * pci_rescan_bus - Scan a PCI bus for devices
3283 : * @bus: PCI bus to scan
3284 : *
3285 : * Scan a PCI bus and child buses for new devices, add them,
3286 : * and enable them.
3287 : *
3288 : * Returns the max number of subordinate bus discovered.
3289 : */
3290 0 : unsigned int pci_rescan_bus(struct pci_bus *bus)
3291 : {
3292 : unsigned int max;
3293 :
3294 0 : max = pci_scan_child_bus(bus);
3295 0 : pci_assign_unassigned_bus_resources(bus);
3296 0 : pci_bus_add_devices(bus);
3297 :
3298 0 : return max;
3299 : }
3300 : EXPORT_SYMBOL_GPL(pci_rescan_bus);
3301 :
3302 : /*
3303 : * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3304 : * routines should always be executed under this mutex.
3305 : */
3306 : static DEFINE_MUTEX(pci_rescan_remove_lock);
3307 :
3308 0 : void pci_lock_rescan_remove(void)
3309 : {
3310 0 : mutex_lock(&pci_rescan_remove_lock);
3311 0 : }
3312 : EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3313 :
3314 0 : void pci_unlock_rescan_remove(void)
3315 : {
3316 0 : mutex_unlock(&pci_rescan_remove_lock);
3317 0 : }
3318 : EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3319 :
3320 0 : static int __init pci_sort_bf_cmp(const struct device *d_a,
3321 : const struct device *d_b)
3322 : {
3323 0 : const struct pci_dev *a = to_pci_dev(d_a);
3324 0 : const struct pci_dev *b = to_pci_dev(d_b);
3325 :
3326 0 : if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3327 0 : else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3328 :
3329 0 : if (a->bus->number < b->bus->number) return -1;
3330 0 : else if (a->bus->number > b->bus->number) return 1;
3331 :
3332 0 : if (a->devfn < b->devfn) return -1;
3333 0 : else if (a->devfn > b->devfn) return 1;
3334 :
3335 0 : return 0;
3336 : }
3337 :
3338 0 : void __init pci_sort_breadthfirst(void)
3339 : {
3340 0 : bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3341 0 : }
3342 :
3343 0 : int pci_hp_add_bridge(struct pci_dev *dev)
3344 : {
3345 0 : struct pci_bus *parent = dev->bus;
3346 0 : int busnr, start = parent->busn_res.start;
3347 0 : unsigned int available_buses = 0;
3348 0 : int end = parent->busn_res.end;
3349 :
3350 0 : for (busnr = start; busnr <= end; busnr++) {
3351 0 : if (!pci_find_bus(pci_domain_nr(parent), busnr))
3352 : break;
3353 : }
3354 0 : if (busnr-- > end) {
3355 0 : pci_err(dev, "No bus number available for hot-added bridge\n");
3356 0 : return -1;
3357 : }
3358 :
3359 : /* Scan bridges that are already configured */
3360 0 : busnr = pci_scan_bridge(parent, dev, busnr, 0);
3361 :
3362 : /*
3363 : * Distribute the available bus numbers between hotplug-capable
3364 : * bridges to make extending the chain later possible.
3365 : */
3366 0 : available_buses = end - busnr;
3367 :
3368 : /* Scan bridges that need to be reconfigured */
3369 0 : pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3370 :
3371 0 : if (!dev->subordinate)
3372 : return -1;
3373 :
3374 0 : return 0;
3375 : }
3376 : EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
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