Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0
2 : /*
3 : * PCI Bus Services, see include/linux/pci.h for further explanation.
4 : *
5 : * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 : * David Mosberger-Tang
7 : *
8 : * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
9 : */
10 :
11 : #include <linux/acpi.h>
12 : #include <linux/kernel.h>
13 : #include <linux/delay.h>
14 : #include <linux/dmi.h>
15 : #include <linux/init.h>
16 : #include <linux/msi.h>
17 : #include <linux/of.h>
18 : #include <linux/pci.h>
19 : #include <linux/pm.h>
20 : #include <linux/slab.h>
21 : #include <linux/module.h>
22 : #include <linux/spinlock.h>
23 : #include <linux/string.h>
24 : #include <linux/log2.h>
25 : #include <linux/logic_pio.h>
26 : #include <linux/pm_wakeup.h>
27 : #include <linux/interrupt.h>
28 : #include <linux/device.h>
29 : #include <linux/pm_runtime.h>
30 : #include <linux/pci_hotplug.h>
31 : #include <linux/vmalloc.h>
32 : #include <asm/dma.h>
33 : #include <linux/aer.h>
34 : #include <linux/bitfield.h>
35 : #include "pci.h"
36 :
37 : DEFINE_MUTEX(pci_slot_mutex);
38 :
39 : const char *pci_power_names[] = {
40 : "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
41 : };
42 : EXPORT_SYMBOL_GPL(pci_power_names);
43 :
44 : #ifdef CONFIG_X86_32
45 : int isa_dma_bridge_buggy;
46 : EXPORT_SYMBOL(isa_dma_bridge_buggy);
47 : #endif
48 :
49 : int pci_pci_problems;
50 : EXPORT_SYMBOL(pci_pci_problems);
51 :
52 : unsigned int pci_pm_d3hot_delay;
53 :
54 : static void pci_pme_list_scan(struct work_struct *work);
55 :
56 : static LIST_HEAD(pci_pme_list);
57 : static DEFINE_MUTEX(pci_pme_list_mutex);
58 : static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
59 :
60 : struct pci_pme_device {
61 : struct list_head list;
62 : struct pci_dev *dev;
63 : };
64 :
65 : #define PME_TIMEOUT 1000 /* How long between PME checks */
66 :
67 : /*
68 : * Devices may extend the 1 sec period through Request Retry Status
69 : * completions (PCIe r6.0 sec 2.3.1). The spec does not provide an upper
70 : * limit, but 60 sec ought to be enough for any device to become
71 : * responsive.
72 : */
73 : #define PCIE_RESET_READY_POLL_MS 60000 /* msec */
74 :
75 0 : static void pci_dev_d3_sleep(struct pci_dev *dev)
76 : {
77 0 : unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
78 : unsigned int upper;
79 :
80 0 : if (delay_ms) {
81 : /* Use a 20% upper bound, 1ms minimum */
82 0 : upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U);
83 0 : usleep_range(delay_ms * USEC_PER_MSEC,
84 0 : (delay_ms + upper) * USEC_PER_MSEC);
85 : }
86 0 : }
87 :
88 0 : bool pci_reset_supported(struct pci_dev *dev)
89 : {
90 0 : return dev->reset_methods[0] != 0;
91 : }
92 :
93 : #ifdef CONFIG_PCI_DOMAINS
94 : int pci_domains_supported = 1;
95 : #endif
96 :
97 : #define DEFAULT_CARDBUS_IO_SIZE (256)
98 : #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
99 : /* pci=cbmemsize=nnM,cbiosize=nn can override this */
100 : unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
101 : unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
102 :
103 : #define DEFAULT_HOTPLUG_IO_SIZE (256)
104 : #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
105 : #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
106 : /* hpiosize=nn can override this */
107 : unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
108 : /*
109 : * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
110 : * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
111 : * pci=hpmemsize=nnM overrides both
112 : */
113 : unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
114 : unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
115 :
116 : #define DEFAULT_HOTPLUG_BUS_SIZE 1
117 : unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
118 :
119 :
120 : /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
121 : #ifdef CONFIG_PCIE_BUS_TUNE_OFF
122 : enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
123 : #elif defined CONFIG_PCIE_BUS_SAFE
124 : enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
125 : #elif defined CONFIG_PCIE_BUS_PERFORMANCE
126 : enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
127 : #elif defined CONFIG_PCIE_BUS_PEER2PEER
128 : enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
129 : #else
130 : enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
131 : #endif
132 :
133 : /*
134 : * The default CLS is used if arch didn't set CLS explicitly and not
135 : * all pci devices agree on the same value. Arch can override either
136 : * the dfl or actual value as it sees fit. Don't forget this is
137 : * measured in 32-bit words, not bytes.
138 : */
139 : u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
140 : u8 pci_cache_line_size;
141 :
142 : /*
143 : * If we set up a device for bus mastering, we need to check the latency
144 : * timer as certain BIOSes forget to set it properly.
145 : */
146 : unsigned int pcibios_max_latency = 255;
147 :
148 : /* If set, the PCIe ARI capability will not be used. */
149 : static bool pcie_ari_disabled;
150 :
151 : /* If set, the PCIe ATS capability will not be used. */
152 : static bool pcie_ats_disabled;
153 :
154 : /* If set, the PCI config space of each device is printed during boot. */
155 : bool pci_early_dump;
156 :
157 0 : bool pci_ats_disabled(void)
158 : {
159 0 : return pcie_ats_disabled;
160 : }
161 : EXPORT_SYMBOL_GPL(pci_ats_disabled);
162 :
163 : /* Disable bridge_d3 for all PCIe ports */
164 : static bool pci_bridge_d3_disable;
165 : /* Force bridge_d3 for all PCIe ports */
166 : static bool pci_bridge_d3_force;
167 :
168 0 : static int __init pcie_port_pm_setup(char *str)
169 : {
170 0 : if (!strcmp(str, "off"))
171 0 : pci_bridge_d3_disable = true;
172 0 : else if (!strcmp(str, "force"))
173 0 : pci_bridge_d3_force = true;
174 0 : return 1;
175 : }
176 : __setup("pcie_port_pm=", pcie_port_pm_setup);
177 :
178 : /**
179 : * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
180 : * @bus: pointer to PCI bus structure to search
181 : *
182 : * Given a PCI bus, returns the highest PCI bus number present in the set
183 : * including the given PCI bus and its list of child PCI buses.
184 : */
185 0 : unsigned char pci_bus_max_busnr(struct pci_bus *bus)
186 : {
187 : struct pci_bus *tmp;
188 : unsigned char max, n;
189 :
190 0 : max = bus->busn_res.end;
191 0 : list_for_each_entry(tmp, &bus->children, node) {
192 0 : n = pci_bus_max_busnr(tmp);
193 0 : if (n > max)
194 0 : max = n;
195 : }
196 0 : return max;
197 : }
198 : EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
199 :
200 : /**
201 : * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
202 : * @pdev: the PCI device
203 : *
204 : * Returns error bits set in PCI_STATUS and clears them.
205 : */
206 0 : int pci_status_get_and_clear_errors(struct pci_dev *pdev)
207 : {
208 : u16 status;
209 : int ret;
210 :
211 0 : ret = pci_read_config_word(pdev, PCI_STATUS, &status);
212 0 : if (ret != PCIBIOS_SUCCESSFUL)
213 : return -EIO;
214 :
215 0 : status &= PCI_STATUS_ERROR_BITS;
216 0 : if (status)
217 0 : pci_write_config_word(pdev, PCI_STATUS, status);
218 :
219 0 : return status;
220 : }
221 : EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
222 :
223 : #ifdef CONFIG_HAS_IOMEM
224 0 : static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar,
225 : bool write_combine)
226 : {
227 0 : struct resource *res = &pdev->resource[bar];
228 0 : resource_size_t start = res->start;
229 0 : resource_size_t size = resource_size(res);
230 :
231 : /*
232 : * Make sure the BAR is actually a memory resource, not an IO resource
233 : */
234 0 : if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
235 0 : pci_err(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
236 0 : return NULL;
237 : }
238 :
239 0 : if (write_combine)
240 0 : return ioremap_wc(start, size);
241 :
242 0 : return ioremap(start, size);
243 : }
244 :
245 0 : void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
246 : {
247 0 : return __pci_ioremap_resource(pdev, bar, false);
248 : }
249 : EXPORT_SYMBOL_GPL(pci_ioremap_bar);
250 :
251 0 : void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
252 : {
253 0 : return __pci_ioremap_resource(pdev, bar, true);
254 : }
255 : EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
256 : #endif
257 :
258 : /**
259 : * pci_dev_str_match_path - test if a path string matches a device
260 : * @dev: the PCI device to test
261 : * @path: string to match the device against
262 : * @endptr: pointer to the string after the match
263 : *
264 : * Test if a string (typically from a kernel parameter) formatted as a
265 : * path of device/function addresses matches a PCI device. The string must
266 : * be of the form:
267 : *
268 : * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
269 : *
270 : * A path for a device can be obtained using 'lspci -t'. Using a path
271 : * is more robust against bus renumbering than using only a single bus,
272 : * device and function address.
273 : *
274 : * Returns 1 if the string matches the device, 0 if it does not and
275 : * a negative error code if it fails to parse the string.
276 : */
277 0 : static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
278 : const char **endptr)
279 : {
280 : int ret;
281 : unsigned int seg, bus, slot, func;
282 : char *wpath, *p;
283 : char end;
284 :
285 0 : *endptr = strchrnul(path, ';');
286 :
287 0 : wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
288 0 : if (!wpath)
289 : return -ENOMEM;
290 :
291 : while (1) {
292 0 : p = strrchr(wpath, '/');
293 0 : if (!p)
294 : break;
295 0 : ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
296 0 : if (ret != 2) {
297 : ret = -EINVAL;
298 : goto free_and_exit;
299 : }
300 :
301 0 : if (dev->devfn != PCI_DEVFN(slot, func)) {
302 : ret = 0;
303 : goto free_and_exit;
304 : }
305 :
306 : /*
307 : * Note: we don't need to get a reference to the upstream
308 : * bridge because we hold a reference to the top level
309 : * device which should hold a reference to the bridge,
310 : * and so on.
311 : */
312 0 : dev = pci_upstream_bridge(dev);
313 0 : if (!dev) {
314 : ret = 0;
315 : goto free_and_exit;
316 : }
317 :
318 0 : *p = 0;
319 : }
320 :
321 0 : ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
322 : &func, &end);
323 0 : if (ret != 4) {
324 0 : seg = 0;
325 0 : ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
326 0 : if (ret != 3) {
327 : ret = -EINVAL;
328 : goto free_and_exit;
329 : }
330 : }
331 :
332 0 : ret = (seg == pci_domain_nr(dev->bus) &&
333 0 : bus == dev->bus->number &&
334 0 : dev->devfn == PCI_DEVFN(slot, func));
335 :
336 : free_and_exit:
337 0 : kfree(wpath);
338 0 : return ret;
339 : }
340 :
341 : /**
342 : * pci_dev_str_match - test if a string matches a device
343 : * @dev: the PCI device to test
344 : * @p: string to match the device against
345 : * @endptr: pointer to the string after the match
346 : *
347 : * Test if a string (typically from a kernel parameter) matches a specified
348 : * PCI device. The string may be of one of the following formats:
349 : *
350 : * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
351 : * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
352 : *
353 : * The first format specifies a PCI bus/device/function address which
354 : * may change if new hardware is inserted, if motherboard firmware changes,
355 : * or due to changes caused in kernel parameters. If the domain is
356 : * left unspecified, it is taken to be 0. In order to be robust against
357 : * bus renumbering issues, a path of PCI device/function numbers may be used
358 : * to address the specific device. The path for a device can be determined
359 : * through the use of 'lspci -t'.
360 : *
361 : * The second format matches devices using IDs in the configuration
362 : * space which may match multiple devices in the system. A value of 0
363 : * for any field will match all devices. (Note: this differs from
364 : * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
365 : * legacy reasons and convenience so users don't have to specify
366 : * FFFFFFFFs on the command line.)
367 : *
368 : * Returns 1 if the string matches the device, 0 if it does not and
369 : * a negative error code if the string cannot be parsed.
370 : */
371 0 : static int pci_dev_str_match(struct pci_dev *dev, const char *p,
372 : const char **endptr)
373 : {
374 : int ret;
375 : int count;
376 : unsigned short vendor, device, subsystem_vendor, subsystem_device;
377 :
378 0 : if (strncmp(p, "pci:", 4) == 0) {
379 : /* PCI vendor/device (subvendor/subdevice) IDs are specified */
380 0 : p += 4;
381 0 : ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
382 : &subsystem_vendor, &subsystem_device, &count);
383 0 : if (ret != 4) {
384 0 : ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
385 0 : if (ret != 2)
386 : return -EINVAL;
387 :
388 0 : subsystem_vendor = 0;
389 0 : subsystem_device = 0;
390 : }
391 :
392 0 : p += count;
393 :
394 0 : if ((!vendor || vendor == dev->vendor) &&
395 0 : (!device || device == dev->device) &&
396 0 : (!subsystem_vendor ||
397 0 : subsystem_vendor == dev->subsystem_vendor) &&
398 0 : (!subsystem_device ||
399 0 : subsystem_device == dev->subsystem_device))
400 : goto found;
401 : } else {
402 : /*
403 : * PCI Bus, Device, Function IDs are specified
404 : * (optionally, may include a path of devfns following it)
405 : */
406 0 : ret = pci_dev_str_match_path(dev, p, &p);
407 0 : if (ret < 0)
408 : return ret;
409 0 : else if (ret)
410 : goto found;
411 : }
412 :
413 0 : *endptr = p;
414 0 : return 0;
415 :
416 : found:
417 0 : *endptr = p;
418 0 : return 1;
419 : }
420 :
421 0 : static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
422 : u8 pos, int cap, int *ttl)
423 : {
424 : u8 id;
425 : u16 ent;
426 :
427 0 : pci_bus_read_config_byte(bus, devfn, pos, &pos);
428 :
429 0 : while ((*ttl)--) {
430 0 : if (pos < 0x40)
431 : break;
432 0 : pos &= ~3;
433 0 : pci_bus_read_config_word(bus, devfn, pos, &ent);
434 :
435 0 : id = ent & 0xff;
436 0 : if (id == 0xff)
437 : break;
438 0 : if (id == cap)
439 0 : return pos;
440 0 : pos = (ent >> 8);
441 : }
442 : return 0;
443 : }
444 :
445 : static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
446 : u8 pos, int cap)
447 : {
448 0 : int ttl = PCI_FIND_CAP_TTL;
449 :
450 0 : return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
451 : }
452 :
453 0 : u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
454 : {
455 0 : return __pci_find_next_cap(dev->bus, dev->devfn,
456 0 : pos + PCI_CAP_LIST_NEXT, cap);
457 : }
458 : EXPORT_SYMBOL_GPL(pci_find_next_capability);
459 :
460 0 : static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
461 : unsigned int devfn, u8 hdr_type)
462 : {
463 : u16 status;
464 :
465 0 : pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
466 0 : if (!(status & PCI_STATUS_CAP_LIST))
467 : return 0;
468 :
469 0 : switch (hdr_type) {
470 : case PCI_HEADER_TYPE_NORMAL:
471 : case PCI_HEADER_TYPE_BRIDGE:
472 : return PCI_CAPABILITY_LIST;
473 : case PCI_HEADER_TYPE_CARDBUS:
474 0 : return PCI_CB_CAPABILITY_LIST;
475 : }
476 :
477 0 : return 0;
478 : }
479 :
480 : /**
481 : * pci_find_capability - query for devices' capabilities
482 : * @dev: PCI device to query
483 : * @cap: capability code
484 : *
485 : * Tell if a device supports a given PCI capability.
486 : * Returns the address of the requested capability structure within the
487 : * device's PCI configuration space or 0 in case the device does not
488 : * support it. Possible values for @cap include:
489 : *
490 : * %PCI_CAP_ID_PM Power Management
491 : * %PCI_CAP_ID_AGP Accelerated Graphics Port
492 : * %PCI_CAP_ID_VPD Vital Product Data
493 : * %PCI_CAP_ID_SLOTID Slot Identification
494 : * %PCI_CAP_ID_MSI Message Signalled Interrupts
495 : * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
496 : * %PCI_CAP_ID_PCIX PCI-X
497 : * %PCI_CAP_ID_EXP PCI Express
498 : */
499 0 : u8 pci_find_capability(struct pci_dev *dev, int cap)
500 : {
501 : u8 pos;
502 :
503 0 : pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
504 0 : if (pos)
505 0 : pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
506 :
507 0 : return pos;
508 : }
509 : EXPORT_SYMBOL(pci_find_capability);
510 :
511 : /**
512 : * pci_bus_find_capability - query for devices' capabilities
513 : * @bus: the PCI bus to query
514 : * @devfn: PCI device to query
515 : * @cap: capability code
516 : *
517 : * Like pci_find_capability() but works for PCI devices that do not have a
518 : * pci_dev structure set up yet.
519 : *
520 : * Returns the address of the requested capability structure within the
521 : * device's PCI configuration space or 0 in case the device does not
522 : * support it.
523 : */
524 0 : u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
525 : {
526 : u8 hdr_type, pos;
527 :
528 0 : pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
529 :
530 0 : pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
531 0 : if (pos)
532 0 : pos = __pci_find_next_cap(bus, devfn, pos, cap);
533 :
534 0 : return pos;
535 : }
536 : EXPORT_SYMBOL(pci_bus_find_capability);
537 :
538 : /**
539 : * pci_find_next_ext_capability - Find an extended capability
540 : * @dev: PCI device to query
541 : * @start: address at which to start looking (0 to start at beginning of list)
542 : * @cap: capability code
543 : *
544 : * Returns the address of the next matching extended capability structure
545 : * within the device's PCI configuration space or 0 if the device does
546 : * not support it. Some capabilities can occur several times, e.g., the
547 : * vendor-specific capability, and this provides a way to find them all.
548 : */
549 0 : u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
550 : {
551 : u32 header;
552 : int ttl;
553 0 : u16 pos = PCI_CFG_SPACE_SIZE;
554 :
555 : /* minimum 8 bytes per capability */
556 0 : ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
557 :
558 0 : if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
559 : return 0;
560 :
561 0 : if (start)
562 0 : pos = start;
563 :
564 0 : if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
565 : return 0;
566 :
567 : /*
568 : * If we have no capabilities, this is indicated by cap ID,
569 : * cap version and next pointer all being 0.
570 : */
571 0 : if (header == 0)
572 : return 0;
573 :
574 0 : while (ttl-- > 0) {
575 0 : if (PCI_EXT_CAP_ID(header) == cap && pos != start)
576 : return pos;
577 :
578 0 : pos = PCI_EXT_CAP_NEXT(header);
579 0 : if (pos < PCI_CFG_SPACE_SIZE)
580 : break;
581 :
582 0 : if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
583 : break;
584 : }
585 :
586 : return 0;
587 : }
588 : EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
589 :
590 : /**
591 : * pci_find_ext_capability - Find an extended capability
592 : * @dev: PCI device to query
593 : * @cap: capability code
594 : *
595 : * Returns the address of the requested extended capability structure
596 : * within the device's PCI configuration space or 0 if the device does
597 : * not support it. Possible values for @cap include:
598 : *
599 : * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
600 : * %PCI_EXT_CAP_ID_VC Virtual Channel
601 : * %PCI_EXT_CAP_ID_DSN Device Serial Number
602 : * %PCI_EXT_CAP_ID_PWR Power Budgeting
603 : */
604 0 : u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
605 : {
606 0 : return pci_find_next_ext_capability(dev, 0, cap);
607 : }
608 : EXPORT_SYMBOL_GPL(pci_find_ext_capability);
609 :
610 : /**
611 : * pci_get_dsn - Read and return the 8-byte Device Serial Number
612 : * @dev: PCI device to query
613 : *
614 : * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
615 : * Number.
616 : *
617 : * Returns the DSN, or zero if the capability does not exist.
618 : */
619 0 : u64 pci_get_dsn(struct pci_dev *dev)
620 : {
621 : u32 dword;
622 : u64 dsn;
623 : int pos;
624 :
625 0 : pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
626 0 : if (!pos)
627 : return 0;
628 :
629 : /*
630 : * The Device Serial Number is two dwords offset 4 bytes from the
631 : * capability position. The specification says that the first dword is
632 : * the lower half, and the second dword is the upper half.
633 : */
634 0 : pos += 4;
635 0 : pci_read_config_dword(dev, pos, &dword);
636 0 : dsn = (u64)dword;
637 0 : pci_read_config_dword(dev, pos + 4, &dword);
638 0 : dsn |= ((u64)dword) << 32;
639 :
640 0 : return dsn;
641 : }
642 : EXPORT_SYMBOL_GPL(pci_get_dsn);
643 :
644 0 : static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
645 : {
646 0 : int rc, ttl = PCI_FIND_CAP_TTL;
647 : u8 cap, mask;
648 :
649 0 : if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
650 : mask = HT_3BIT_CAP_MASK;
651 : else
652 0 : mask = HT_5BIT_CAP_MASK;
653 :
654 0 : pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
655 : PCI_CAP_ID_HT, &ttl);
656 0 : while (pos) {
657 0 : rc = pci_read_config_byte(dev, pos + 3, &cap);
658 0 : if (rc != PCIBIOS_SUCCESSFUL)
659 : return 0;
660 :
661 0 : if ((cap & mask) == ht_cap)
662 : return pos;
663 :
664 0 : pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
665 0 : pos + PCI_CAP_LIST_NEXT,
666 : PCI_CAP_ID_HT, &ttl);
667 : }
668 :
669 : return 0;
670 : }
671 :
672 : /**
673 : * pci_find_next_ht_capability - query a device's HyperTransport capabilities
674 : * @dev: PCI device to query
675 : * @pos: Position from which to continue searching
676 : * @ht_cap: HyperTransport capability code
677 : *
678 : * To be used in conjunction with pci_find_ht_capability() to search for
679 : * all capabilities matching @ht_cap. @pos should always be a value returned
680 : * from pci_find_ht_capability().
681 : *
682 : * NB. To be 100% safe against broken PCI devices, the caller should take
683 : * steps to avoid an infinite loop.
684 : */
685 0 : u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
686 : {
687 0 : return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
688 : }
689 : EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
690 :
691 : /**
692 : * pci_find_ht_capability - query a device's HyperTransport capabilities
693 : * @dev: PCI device to query
694 : * @ht_cap: HyperTransport capability code
695 : *
696 : * Tell if a device supports a given HyperTransport capability.
697 : * Returns an address within the device's PCI configuration space
698 : * or 0 in case the device does not support the request capability.
699 : * The address points to the PCI capability, of type PCI_CAP_ID_HT,
700 : * which has a HyperTransport capability matching @ht_cap.
701 : */
702 0 : u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
703 : {
704 : u8 pos;
705 :
706 0 : pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
707 0 : if (pos)
708 0 : pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
709 :
710 0 : return pos;
711 : }
712 : EXPORT_SYMBOL_GPL(pci_find_ht_capability);
713 :
714 : /**
715 : * pci_find_vsec_capability - Find a vendor-specific extended capability
716 : * @dev: PCI device to query
717 : * @vendor: Vendor ID for which capability is defined
718 : * @cap: Vendor-specific capability ID
719 : *
720 : * If @dev has Vendor ID @vendor, search for a VSEC capability with
721 : * VSEC ID @cap. If found, return the capability offset in
722 : * config space; otherwise return 0.
723 : */
724 0 : u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
725 : {
726 0 : u16 vsec = 0;
727 : u32 header;
728 :
729 0 : if (vendor != dev->vendor)
730 : return 0;
731 :
732 0 : while ((vsec = pci_find_next_ext_capability(dev, vsec,
733 : PCI_EXT_CAP_ID_VNDR))) {
734 0 : if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER,
735 0 : &header) == PCIBIOS_SUCCESSFUL &&
736 0 : PCI_VNDR_HEADER_ID(header) == cap)
737 : return vsec;
738 : }
739 :
740 : return 0;
741 : }
742 : EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
743 :
744 : /**
745 : * pci_find_dvsec_capability - Find DVSEC for vendor
746 : * @dev: PCI device to query
747 : * @vendor: Vendor ID to match for the DVSEC
748 : * @dvsec: Designated Vendor-specific capability ID
749 : *
750 : * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability
751 : * offset in config space; otherwise return 0.
752 : */
753 0 : u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec)
754 : {
755 : int pos;
756 :
757 0 : pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DVSEC);
758 0 : if (!pos)
759 : return 0;
760 :
761 0 : while (pos) {
762 : u16 v, id;
763 :
764 0 : pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v);
765 0 : pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id);
766 0 : if (vendor == v && dvsec == id)
767 0 : return pos;
768 :
769 0 : pos = pci_find_next_ext_capability(dev, pos, PCI_EXT_CAP_ID_DVSEC);
770 : }
771 :
772 : return 0;
773 : }
774 : EXPORT_SYMBOL_GPL(pci_find_dvsec_capability);
775 :
776 : /**
777 : * pci_find_parent_resource - return resource region of parent bus of given
778 : * region
779 : * @dev: PCI device structure contains resources to be searched
780 : * @res: child resource record for which parent is sought
781 : *
782 : * For given resource region of given device, return the resource region of
783 : * parent bus the given region is contained in.
784 : */
785 0 : struct resource *pci_find_parent_resource(const struct pci_dev *dev,
786 : struct resource *res)
787 : {
788 0 : const struct pci_bus *bus = dev->bus;
789 : struct resource *r;
790 :
791 0 : pci_bus_for_each_resource(bus, r) {
792 0 : if (!r)
793 0 : continue;
794 0 : if (resource_contains(r, res)) {
795 :
796 : /*
797 : * If the window is prefetchable but the BAR is
798 : * not, the allocator made a mistake.
799 : */
800 0 : if (r->flags & IORESOURCE_PREFETCH &&
801 0 : !(res->flags & IORESOURCE_PREFETCH))
802 : return NULL;
803 :
804 : /*
805 : * If we're below a transparent bridge, there may
806 : * be both a positively-decoded aperture and a
807 : * subtractively-decoded region that contain the BAR.
808 : * We want the positively-decoded one, so this depends
809 : * on pci_bus_for_each_resource() giving us those
810 : * first.
811 : */
812 0 : return r;
813 : }
814 : }
815 : return NULL;
816 : }
817 : EXPORT_SYMBOL(pci_find_parent_resource);
818 :
819 : /**
820 : * pci_find_resource - Return matching PCI device resource
821 : * @dev: PCI device to query
822 : * @res: Resource to look for
823 : *
824 : * Goes over standard PCI resources (BARs) and checks if the given resource
825 : * is partially or fully contained in any of them. In that case the
826 : * matching resource is returned, %NULL otherwise.
827 : */
828 0 : struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
829 : {
830 : int i;
831 :
832 0 : for (i = 0; i < PCI_STD_NUM_BARS; i++) {
833 0 : struct resource *r = &dev->resource[i];
834 :
835 0 : if (r->start && resource_contains(r, res))
836 : return r;
837 : }
838 :
839 : return NULL;
840 : }
841 : EXPORT_SYMBOL(pci_find_resource);
842 :
843 : /**
844 : * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
845 : * @dev: the PCI device to operate on
846 : * @pos: config space offset of status word
847 : * @mask: mask of bit(s) to care about in status word
848 : *
849 : * Return 1 when mask bit(s) in status word clear, 0 otherwise.
850 : */
851 0 : int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
852 : {
853 : int i;
854 :
855 : /* Wait for Transaction Pending bit clean */
856 0 : for (i = 0; i < 4; i++) {
857 : u16 status;
858 0 : if (i)
859 0 : msleep((1 << (i - 1)) * 100);
860 :
861 0 : pci_read_config_word(dev, pos, &status);
862 0 : if (!(status & mask))
863 0 : return 1;
864 : }
865 :
866 : return 0;
867 : }
868 :
869 : static int pci_acs_enable;
870 :
871 : /**
872 : * pci_request_acs - ask for ACS to be enabled if supported
873 : */
874 0 : void pci_request_acs(void)
875 : {
876 0 : pci_acs_enable = 1;
877 0 : }
878 :
879 : static const char *disable_acs_redir_param;
880 :
881 : /**
882 : * pci_disable_acs_redir - disable ACS redirect capabilities
883 : * @dev: the PCI device
884 : *
885 : * For only devices specified in the disable_acs_redir parameter.
886 : */
887 0 : static void pci_disable_acs_redir(struct pci_dev *dev)
888 : {
889 0 : int ret = 0;
890 : const char *p;
891 : int pos;
892 : u16 ctrl;
893 :
894 0 : if (!disable_acs_redir_param)
895 0 : return;
896 :
897 0 : p = disable_acs_redir_param;
898 0 : while (*p) {
899 0 : ret = pci_dev_str_match(dev, p, &p);
900 0 : if (ret < 0) {
901 0 : pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
902 : disable_acs_redir_param);
903 :
904 : break;
905 0 : } else if (ret == 1) {
906 : /* Found a match */
907 : break;
908 : }
909 :
910 0 : if (*p != ';' && *p != ',') {
911 : /* End of param or invalid format */
912 : break;
913 : }
914 0 : p++;
915 : }
916 :
917 0 : if (ret != 1)
918 : return;
919 :
920 0 : if (!pci_dev_specific_disable_acs_redir(dev))
921 : return;
922 :
923 0 : pos = dev->acs_cap;
924 0 : if (!pos) {
925 0 : pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
926 0 : return;
927 : }
928 :
929 0 : pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
930 :
931 : /* P2P Request & Completion Redirect */
932 0 : ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
933 :
934 0 : pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
935 :
936 0 : pci_info(dev, "disabled ACS redirect\n");
937 : }
938 :
939 : /**
940 : * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
941 : * @dev: the PCI device
942 : */
943 0 : static void pci_std_enable_acs(struct pci_dev *dev)
944 : {
945 : int pos;
946 : u16 cap;
947 : u16 ctrl;
948 :
949 0 : pos = dev->acs_cap;
950 0 : if (!pos)
951 0 : return;
952 :
953 0 : pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
954 0 : pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
955 :
956 : /* Source Validation */
957 0 : ctrl |= (cap & PCI_ACS_SV);
958 :
959 : /* P2P Request Redirect */
960 0 : ctrl |= (cap & PCI_ACS_RR);
961 :
962 : /* P2P Completion Redirect */
963 0 : ctrl |= (cap & PCI_ACS_CR);
964 :
965 : /* Upstream Forwarding */
966 0 : ctrl |= (cap & PCI_ACS_UF);
967 :
968 : /* Enable Translation Blocking for external devices and noats */
969 0 : if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
970 0 : ctrl |= (cap & PCI_ACS_TB);
971 :
972 0 : pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
973 : }
974 :
975 : /**
976 : * pci_enable_acs - enable ACS if hardware support it
977 : * @dev: the PCI device
978 : */
979 0 : static void pci_enable_acs(struct pci_dev *dev)
980 : {
981 0 : if (!pci_acs_enable)
982 : goto disable_acs_redir;
983 :
984 0 : if (!pci_dev_specific_enable_acs(dev))
985 : goto disable_acs_redir;
986 :
987 0 : pci_std_enable_acs(dev);
988 :
989 : disable_acs_redir:
990 : /*
991 : * Note: pci_disable_acs_redir() must be called even if ACS was not
992 : * enabled by the kernel because it may have been enabled by
993 : * platform firmware. So if we are told to disable it, we should
994 : * always disable it after setting the kernel's default
995 : * preferences.
996 : */
997 0 : pci_disable_acs_redir(dev);
998 0 : }
999 :
1000 : /**
1001 : * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
1002 : * @dev: PCI device to have its BARs restored
1003 : *
1004 : * Restore the BAR values for a given device, so as to make it
1005 : * accessible by its driver.
1006 : */
1007 : static void pci_restore_bars(struct pci_dev *dev)
1008 : {
1009 : int i;
1010 :
1011 0 : for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
1012 0 : pci_update_resource(dev, i);
1013 : }
1014 :
1015 : static inline bool platform_pci_power_manageable(struct pci_dev *dev)
1016 : {
1017 : if (pci_use_mid_pm())
1018 : return true;
1019 :
1020 0 : return acpi_pci_power_manageable(dev);
1021 : }
1022 :
1023 : static inline int platform_pci_set_power_state(struct pci_dev *dev,
1024 : pci_power_t t)
1025 : {
1026 : if (pci_use_mid_pm())
1027 : return mid_pci_set_power_state(dev, t);
1028 :
1029 0 : return acpi_pci_set_power_state(dev, t);
1030 : }
1031 :
1032 : static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
1033 : {
1034 : if (pci_use_mid_pm())
1035 : return mid_pci_get_power_state(dev);
1036 :
1037 0 : return acpi_pci_get_power_state(dev);
1038 : }
1039 :
1040 : static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
1041 : {
1042 : if (!pci_use_mid_pm())
1043 : acpi_pci_refresh_power_state(dev);
1044 : }
1045 :
1046 : static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1047 : {
1048 : if (pci_use_mid_pm())
1049 : return PCI_POWER_ERROR;
1050 :
1051 : return acpi_pci_choose_state(dev);
1052 : }
1053 :
1054 : static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1055 : {
1056 : if (pci_use_mid_pm())
1057 : return PCI_POWER_ERROR;
1058 :
1059 0 : return acpi_pci_wakeup(dev, enable);
1060 : }
1061 :
1062 : static inline bool platform_pci_need_resume(struct pci_dev *dev)
1063 : {
1064 : if (pci_use_mid_pm())
1065 : return false;
1066 :
1067 0 : return acpi_pci_need_resume(dev);
1068 : }
1069 :
1070 : static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1071 : {
1072 : if (pci_use_mid_pm())
1073 : return false;
1074 :
1075 0 : return acpi_pci_bridge_d3(dev);
1076 : }
1077 :
1078 : /**
1079 : * pci_update_current_state - Read power state of given device and cache it
1080 : * @dev: PCI device to handle.
1081 : * @state: State to cache in case the device doesn't have the PM capability
1082 : *
1083 : * The power state is read from the PMCSR register, which however is
1084 : * inaccessible in D3cold. The platform firmware is therefore queried first
1085 : * to detect accessibility of the register. In case the platform firmware
1086 : * reports an incorrect state or the device isn't power manageable by the
1087 : * platform at all, we try to detect D3cold by testing accessibility of the
1088 : * vendor ID in config space.
1089 : */
1090 0 : void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1091 : {
1092 0 : if (platform_pci_get_power_state(dev) == PCI_D3cold) {
1093 : dev->current_state = PCI_D3cold;
1094 0 : } else if (dev->pm_cap) {
1095 : u16 pmcsr;
1096 :
1097 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1098 0 : if (PCI_POSSIBLE_ERROR(pmcsr)) {
1099 0 : dev->current_state = PCI_D3cold;
1100 0 : return;
1101 : }
1102 0 : dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1103 : } else {
1104 0 : dev->current_state = state;
1105 : }
1106 : }
1107 :
1108 : /**
1109 : * pci_refresh_power_state - Refresh the given device's power state data
1110 : * @dev: Target PCI device.
1111 : *
1112 : * Ask the platform to refresh the devices power state information and invoke
1113 : * pci_update_current_state() to update its current PCI power state.
1114 : */
1115 0 : void pci_refresh_power_state(struct pci_dev *dev)
1116 : {
1117 0 : platform_pci_refresh_power_state(dev);
1118 0 : pci_update_current_state(dev, dev->current_state);
1119 0 : }
1120 :
1121 : /**
1122 : * pci_platform_power_transition - Use platform to change device power state
1123 : * @dev: PCI device to handle.
1124 : * @state: State to put the device into.
1125 : */
1126 0 : int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1127 : {
1128 : int error;
1129 :
1130 0 : error = platform_pci_set_power_state(dev, state);
1131 : if (!error)
1132 : pci_update_current_state(dev, state);
1133 0 : else if (!dev->pm_cap) /* Fall back to PCI_D0 */
1134 0 : dev->current_state = PCI_D0;
1135 :
1136 0 : return error;
1137 : }
1138 : EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1139 :
1140 0 : static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1141 : {
1142 0 : pm_request_resume(&pci_dev->dev);
1143 0 : return 0;
1144 : }
1145 :
1146 : /**
1147 : * pci_resume_bus - Walk given bus and runtime resume devices on it
1148 : * @bus: Top bus of the subtree to walk.
1149 : */
1150 0 : void pci_resume_bus(struct pci_bus *bus)
1151 : {
1152 0 : if (bus)
1153 0 : pci_walk_bus(bus, pci_resume_one, NULL);
1154 0 : }
1155 :
1156 0 : static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1157 : {
1158 0 : int delay = 1;
1159 : u32 id;
1160 :
1161 : /*
1162 : * After reset, the device should not silently discard config
1163 : * requests, but it may still indicate that it needs more time by
1164 : * responding to them with CRS completions. The Root Port will
1165 : * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
1166 : * the read (except when CRS SV is enabled and the read was for the
1167 : * Vendor ID; in that case it synthesizes 0x0001 data).
1168 : *
1169 : * Wait for the device to return a non-CRS completion. Read the
1170 : * Command register instead of Vendor ID so we don't have to
1171 : * contend with the CRS SV value.
1172 : */
1173 0 : pci_read_config_dword(dev, PCI_COMMAND, &id);
1174 0 : while (PCI_POSSIBLE_ERROR(id)) {
1175 0 : if (delay > timeout) {
1176 0 : pci_warn(dev, "not ready %dms after %s; giving up\n",
1177 : delay - 1, reset_type);
1178 0 : return -ENOTTY;
1179 : }
1180 :
1181 0 : if (delay > PCI_RESET_WAIT)
1182 0 : pci_info(dev, "not ready %dms after %s; waiting\n",
1183 : delay - 1, reset_type);
1184 :
1185 0 : msleep(delay);
1186 0 : delay *= 2;
1187 0 : pci_read_config_dword(dev, PCI_COMMAND, &id);
1188 : }
1189 :
1190 0 : if (delay > PCI_RESET_WAIT)
1191 0 : pci_info(dev, "ready %dms after %s\n", delay - 1,
1192 : reset_type);
1193 :
1194 : return 0;
1195 : }
1196 :
1197 : /**
1198 : * pci_power_up - Put the given device into D0
1199 : * @dev: PCI device to power up
1200 : *
1201 : * On success, return 0 or 1, depending on whether or not it is necessary to
1202 : * restore the device's BARs subsequently (1 is returned in that case).
1203 : */
1204 0 : int pci_power_up(struct pci_dev *dev)
1205 : {
1206 : bool need_restore;
1207 : pci_power_t state;
1208 : u16 pmcsr;
1209 :
1210 0 : platform_pci_set_power_state(dev, PCI_D0);
1211 :
1212 0 : if (!dev->pm_cap) {
1213 0 : state = platform_pci_get_power_state(dev);
1214 : if (state == PCI_UNKNOWN)
1215 0 : dev->current_state = PCI_D0;
1216 : else
1217 : dev->current_state = state;
1218 :
1219 : if (state == PCI_D0)
1220 : return 0;
1221 :
1222 : return -EIO;
1223 : }
1224 :
1225 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1226 0 : if (PCI_POSSIBLE_ERROR(pmcsr)) {
1227 0 : pci_err(dev, "Unable to change power state from %s to D0, device inaccessible\n",
1228 : pci_power_name(dev->current_state));
1229 0 : dev->current_state = PCI_D3cold;
1230 0 : return -EIO;
1231 : }
1232 :
1233 0 : state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1234 :
1235 0 : need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) &&
1236 : !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET);
1237 :
1238 0 : if (state == PCI_D0)
1239 : goto end;
1240 :
1241 : /*
1242 : * Force the entire word to 0. This doesn't affect PME_Status, disables
1243 : * PME_En, and sets PowerState to 0.
1244 : */
1245 0 : pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);
1246 :
1247 : /* Mandatory transition delays; see PCI PM 1.2. */
1248 0 : if (state == PCI_D3hot)
1249 0 : pci_dev_d3_sleep(dev);
1250 0 : else if (state == PCI_D2)
1251 : udelay(PCI_PM_D2_DELAY);
1252 :
1253 : end:
1254 0 : dev->current_state = PCI_D0;
1255 0 : if (need_restore)
1256 : return 1;
1257 :
1258 0 : return 0;
1259 : }
1260 :
1261 : /**
1262 : * pci_set_full_power_state - Put a PCI device into D0 and update its state
1263 : * @dev: PCI device to power up
1264 : *
1265 : * Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register
1266 : * to confirm the state change, restore its BARs if they might be lost and
1267 : * reconfigure ASPM in acordance with the new power state.
1268 : *
1269 : * If pci_restore_state() is going to be called right after a power state change
1270 : * to D0, it is more efficient to use pci_power_up() directly instead of this
1271 : * function.
1272 : */
1273 0 : static int pci_set_full_power_state(struct pci_dev *dev)
1274 : {
1275 : u16 pmcsr;
1276 : int ret;
1277 :
1278 0 : ret = pci_power_up(dev);
1279 0 : if (ret < 0)
1280 : return ret;
1281 :
1282 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1283 0 : dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1284 0 : if (dev->current_state != PCI_D0) {
1285 0 : pci_info_ratelimited(dev, "Refused to change power state from %s to D0\n",
1286 : pci_power_name(dev->current_state));
1287 0 : } else if (ret > 0) {
1288 : /*
1289 : * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1290 : * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1291 : * from D3hot to D0 _may_ perform an internal reset, thereby
1292 : * going to "D0 Uninitialized" rather than "D0 Initialized".
1293 : * For example, at least some versions of the 3c905B and the
1294 : * 3c556B exhibit this behaviour.
1295 : *
1296 : * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1297 : * devices in a D3hot state at boot. Consequently, we need to
1298 : * restore at least the BARs so that the device will be
1299 : * accessible to its driver.
1300 : */
1301 : pci_restore_bars(dev);
1302 : }
1303 :
1304 : return 0;
1305 : }
1306 :
1307 : /**
1308 : * __pci_dev_set_current_state - Set current state of a PCI device
1309 : * @dev: Device to handle
1310 : * @data: pointer to state to be set
1311 : */
1312 0 : static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1313 : {
1314 0 : pci_power_t state = *(pci_power_t *)data;
1315 :
1316 0 : dev->current_state = state;
1317 0 : return 0;
1318 : }
1319 :
1320 : /**
1321 : * pci_bus_set_current_state - Walk given bus and set current state of devices
1322 : * @bus: Top bus of the subtree to walk.
1323 : * @state: state to be set
1324 : */
1325 0 : void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1326 : {
1327 0 : if (bus)
1328 0 : pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1329 0 : }
1330 :
1331 : /**
1332 : * pci_set_low_power_state - Put a PCI device into a low-power state.
1333 : * @dev: PCI device to handle.
1334 : * @state: PCI power state (D1, D2, D3hot) to put the device into.
1335 : *
1336 : * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1337 : *
1338 : * RETURN VALUE:
1339 : * -EINVAL if the requested state is invalid.
1340 : * -EIO if device does not support PCI PM or its PM capabilities register has a
1341 : * wrong version, or device doesn't support the requested state.
1342 : * 0 if device already is in the requested state.
1343 : * 0 if device's power state has been successfully changed.
1344 : */
1345 0 : static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state)
1346 : {
1347 : u16 pmcsr;
1348 :
1349 0 : if (!dev->pm_cap)
1350 : return -EIO;
1351 :
1352 : /*
1353 : * Validate transition: We can enter D0 from any state, but if
1354 : * we're already in a low-power state, we can only go deeper. E.g.,
1355 : * we can go from D1 to D3, but we can't go directly from D3 to D1;
1356 : * we'd have to go from D3 to D0, then to D1.
1357 : */
1358 0 : if (dev->current_state <= PCI_D3cold && dev->current_state > state) {
1359 : pci_dbg(dev, "Invalid power transition (from %s to %s)\n",
1360 : pci_power_name(dev->current_state),
1361 : pci_power_name(state));
1362 : return -EINVAL;
1363 : }
1364 :
1365 : /* Check if this device supports the desired state */
1366 0 : if ((state == PCI_D1 && !dev->d1_support)
1367 0 : || (state == PCI_D2 && !dev->d2_support))
1368 : return -EIO;
1369 :
1370 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1371 0 : if (PCI_POSSIBLE_ERROR(pmcsr)) {
1372 0 : pci_err(dev, "Unable to change power state from %s to %s, device inaccessible\n",
1373 : pci_power_name(dev->current_state),
1374 : pci_power_name(state));
1375 0 : dev->current_state = PCI_D3cold;
1376 0 : return -EIO;
1377 : }
1378 :
1379 0 : pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1380 0 : pmcsr |= state;
1381 :
1382 : /* Enter specified state */
1383 0 : pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1384 :
1385 : /* Mandatory power management transition delays; see PCI PM 1.2. */
1386 0 : if (state == PCI_D3hot)
1387 0 : pci_dev_d3_sleep(dev);
1388 0 : else if (state == PCI_D2)
1389 : udelay(PCI_PM_D2_DELAY);
1390 :
1391 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1392 0 : dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1393 0 : if (dev->current_state != state)
1394 0 : pci_info_ratelimited(dev, "Refused to change power state from %s to %s\n",
1395 : pci_power_name(dev->current_state),
1396 : pci_power_name(state));
1397 :
1398 : return 0;
1399 : }
1400 :
1401 : /**
1402 : * pci_set_power_state - Set the power state of a PCI device
1403 : * @dev: PCI device to handle.
1404 : * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1405 : *
1406 : * Transition a device to a new power state, using the platform firmware and/or
1407 : * the device's PCI PM registers.
1408 : *
1409 : * RETURN VALUE:
1410 : * -EINVAL if the requested state is invalid.
1411 : * -EIO if device does not support PCI PM or its PM capabilities register has a
1412 : * wrong version, or device doesn't support the requested state.
1413 : * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1414 : * 0 if device already is in the requested state.
1415 : * 0 if the transition is to D3 but D3 is not supported.
1416 : * 0 if device's power state has been successfully changed.
1417 : */
1418 0 : int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1419 : {
1420 : int error;
1421 :
1422 : /* Bound the state we're entering */
1423 0 : if (state > PCI_D3cold)
1424 : state = PCI_D3cold;
1425 0 : else if (state < PCI_D0)
1426 : state = PCI_D0;
1427 0 : else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1428 :
1429 : /*
1430 : * If the device or the parent bridge do not support PCI
1431 : * PM, ignore the request if we're doing anything other
1432 : * than putting it into D0 (which would only happen on
1433 : * boot).
1434 : */
1435 : return 0;
1436 :
1437 : /* Check if we're already there */
1438 0 : if (dev->current_state == state)
1439 : return 0;
1440 :
1441 0 : if (state == PCI_D0)
1442 0 : return pci_set_full_power_state(dev);
1443 :
1444 : /*
1445 : * This device is quirked not to be put into D3, so don't put it in
1446 : * D3
1447 : */
1448 0 : if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1449 : return 0;
1450 :
1451 0 : if (state == PCI_D3cold) {
1452 : /*
1453 : * To put the device in D3cold, put it into D3hot in the native
1454 : * way, then put it into D3cold using platform ops.
1455 : */
1456 0 : error = pci_set_low_power_state(dev, PCI_D3hot);
1457 :
1458 : if (pci_platform_power_transition(dev, PCI_D3cold))
1459 : return error;
1460 :
1461 : /* Powering off a bridge may power off the whole hierarchy */
1462 : if (dev->current_state == PCI_D3cold)
1463 : pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1464 : } else {
1465 0 : error = pci_set_low_power_state(dev, state);
1466 :
1467 : if (pci_platform_power_transition(dev, state))
1468 : return error;
1469 : }
1470 :
1471 : return 0;
1472 : }
1473 : EXPORT_SYMBOL(pci_set_power_state);
1474 :
1475 : #define PCI_EXP_SAVE_REGS 7
1476 :
1477 : static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1478 : u16 cap, bool extended)
1479 : {
1480 : struct pci_cap_saved_state *tmp;
1481 :
1482 0 : hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1483 0 : if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1484 : return tmp;
1485 : }
1486 : return NULL;
1487 : }
1488 :
1489 0 : struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1490 : {
1491 0 : return _pci_find_saved_cap(dev, cap, false);
1492 : }
1493 :
1494 0 : struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1495 : {
1496 0 : return _pci_find_saved_cap(dev, cap, true);
1497 : }
1498 :
1499 0 : static int pci_save_pcie_state(struct pci_dev *dev)
1500 : {
1501 0 : int i = 0;
1502 : struct pci_cap_saved_state *save_state;
1503 : u16 *cap;
1504 :
1505 0 : if (!pci_is_pcie(dev))
1506 : return 0;
1507 :
1508 0 : save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1509 0 : if (!save_state) {
1510 0 : pci_err(dev, "buffer not found in %s\n", __func__);
1511 0 : return -ENOMEM;
1512 : }
1513 :
1514 0 : cap = (u16 *)&save_state->cap.data[0];
1515 0 : pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1516 0 : pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1517 0 : pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1518 0 : pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1519 0 : pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1520 0 : pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1521 0 : pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1522 :
1523 0 : return 0;
1524 : }
1525 :
1526 0 : void pci_bridge_reconfigure_ltr(struct pci_dev *dev)
1527 : {
1528 : #ifdef CONFIG_PCIEASPM
1529 : struct pci_dev *bridge;
1530 : u32 ctl;
1531 :
1532 0 : bridge = pci_upstream_bridge(dev);
1533 0 : if (bridge && bridge->ltr_path) {
1534 0 : pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1535 0 : if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1536 : pci_dbg(bridge, "re-enabling LTR\n");
1537 : pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1538 : PCI_EXP_DEVCTL2_LTR_EN);
1539 : }
1540 : }
1541 : #endif
1542 0 : }
1543 :
1544 0 : static void pci_restore_pcie_state(struct pci_dev *dev)
1545 : {
1546 0 : int i = 0;
1547 : struct pci_cap_saved_state *save_state;
1548 : u16 *cap;
1549 :
1550 0 : save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1551 0 : if (!save_state)
1552 : return;
1553 :
1554 : /*
1555 : * Downstream ports reset the LTR enable bit when link goes down.
1556 : * Check and re-configure the bit here before restoring device.
1557 : * PCIe r5.0, sec 7.5.3.16.
1558 : */
1559 0 : pci_bridge_reconfigure_ltr(dev);
1560 :
1561 0 : cap = (u16 *)&save_state->cap.data[0];
1562 0 : pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1563 0 : pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1564 0 : pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1565 0 : pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1566 0 : pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1567 0 : pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1568 0 : pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1569 : }
1570 :
1571 0 : static int pci_save_pcix_state(struct pci_dev *dev)
1572 : {
1573 : int pos;
1574 : struct pci_cap_saved_state *save_state;
1575 :
1576 0 : pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1577 0 : if (!pos)
1578 : return 0;
1579 :
1580 0 : save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1581 0 : if (!save_state) {
1582 0 : pci_err(dev, "buffer not found in %s\n", __func__);
1583 0 : return -ENOMEM;
1584 : }
1585 :
1586 0 : pci_read_config_word(dev, pos + PCI_X_CMD,
1587 0 : (u16 *)save_state->cap.data);
1588 :
1589 0 : return 0;
1590 : }
1591 :
1592 0 : static void pci_restore_pcix_state(struct pci_dev *dev)
1593 : {
1594 0 : int i = 0, pos;
1595 : struct pci_cap_saved_state *save_state;
1596 : u16 *cap;
1597 :
1598 0 : save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1599 0 : pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1600 0 : if (!save_state || !pos)
1601 : return;
1602 0 : cap = (u16 *)&save_state->cap.data[0];
1603 :
1604 0 : pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1605 : }
1606 :
1607 0 : static void pci_save_ltr_state(struct pci_dev *dev)
1608 : {
1609 : int ltr;
1610 : struct pci_cap_saved_state *save_state;
1611 : u32 *cap;
1612 :
1613 0 : if (!pci_is_pcie(dev))
1614 : return;
1615 :
1616 0 : ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1617 0 : if (!ltr)
1618 : return;
1619 :
1620 0 : save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1621 0 : if (!save_state) {
1622 0 : pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1623 0 : return;
1624 : }
1625 :
1626 : /* Some broken devices only support dword access to LTR */
1627 0 : cap = &save_state->cap.data[0];
1628 0 : pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
1629 : }
1630 :
1631 0 : static void pci_restore_ltr_state(struct pci_dev *dev)
1632 : {
1633 : struct pci_cap_saved_state *save_state;
1634 : int ltr;
1635 : u32 *cap;
1636 :
1637 0 : save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1638 0 : ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1639 0 : if (!save_state || !ltr)
1640 : return;
1641 :
1642 : /* Some broken devices only support dword access to LTR */
1643 0 : cap = &save_state->cap.data[0];
1644 0 : pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
1645 : }
1646 :
1647 : /**
1648 : * pci_save_state - save the PCI configuration space of a device before
1649 : * suspending
1650 : * @dev: PCI device that we're dealing with
1651 : */
1652 0 : int pci_save_state(struct pci_dev *dev)
1653 : {
1654 : int i;
1655 : /* XXX: 100% dword access ok here? */
1656 0 : for (i = 0; i < 16; i++) {
1657 0 : pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1658 : pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1659 : i * 4, dev->saved_config_space[i]);
1660 : }
1661 0 : dev->state_saved = true;
1662 :
1663 0 : i = pci_save_pcie_state(dev);
1664 0 : if (i != 0)
1665 : return i;
1666 :
1667 0 : i = pci_save_pcix_state(dev);
1668 0 : if (i != 0)
1669 : return i;
1670 :
1671 0 : pci_save_ltr_state(dev);
1672 0 : pci_save_dpc_state(dev);
1673 0 : pci_save_aer_state(dev);
1674 0 : pci_save_ptm_state(dev);
1675 0 : return pci_save_vc_state(dev);
1676 : }
1677 : EXPORT_SYMBOL(pci_save_state);
1678 :
1679 0 : static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1680 : u32 saved_val, int retry, bool force)
1681 : {
1682 : u32 val;
1683 :
1684 0 : pci_read_config_dword(pdev, offset, &val);
1685 0 : if (!force && val == saved_val)
1686 : return;
1687 :
1688 : for (;;) {
1689 : pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1690 : offset, val, saved_val);
1691 0 : pci_write_config_dword(pdev, offset, saved_val);
1692 0 : if (retry-- <= 0)
1693 : return;
1694 :
1695 0 : pci_read_config_dword(pdev, offset, &val);
1696 0 : if (val == saved_val)
1697 : return;
1698 :
1699 : mdelay(1);
1700 : }
1701 : }
1702 :
1703 : static void pci_restore_config_space_range(struct pci_dev *pdev,
1704 : int start, int end, int retry,
1705 : bool force)
1706 : {
1707 : int index;
1708 :
1709 0 : for (index = end; index >= start; index--)
1710 0 : pci_restore_config_dword(pdev, 4 * index,
1711 : pdev->saved_config_space[index],
1712 : retry, force);
1713 : }
1714 :
1715 0 : static void pci_restore_config_space(struct pci_dev *pdev)
1716 : {
1717 0 : if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1718 : pci_restore_config_space_range(pdev, 10, 15, 0, false);
1719 : /* Restore BARs before the command register. */
1720 : pci_restore_config_space_range(pdev, 4, 9, 10, false);
1721 : pci_restore_config_space_range(pdev, 0, 3, 0, false);
1722 0 : } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1723 : pci_restore_config_space_range(pdev, 12, 15, 0, false);
1724 :
1725 : /*
1726 : * Force rewriting of prefetch registers to avoid S3 resume
1727 : * issues on Intel PCI bridges that occur when these
1728 : * registers are not explicitly written.
1729 : */
1730 : pci_restore_config_space_range(pdev, 9, 11, 0, true);
1731 : pci_restore_config_space_range(pdev, 0, 8, 0, false);
1732 : } else {
1733 : pci_restore_config_space_range(pdev, 0, 15, 0, false);
1734 : }
1735 0 : }
1736 :
1737 0 : static void pci_restore_rebar_state(struct pci_dev *pdev)
1738 : {
1739 : unsigned int pos, nbars, i;
1740 : u32 ctrl;
1741 :
1742 0 : pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1743 0 : if (!pos)
1744 0 : return;
1745 :
1746 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1747 0 : nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1748 : PCI_REBAR_CTRL_NBAR_SHIFT;
1749 :
1750 0 : for (i = 0; i < nbars; i++, pos += 8) {
1751 : struct resource *res;
1752 : int bar_idx, size;
1753 :
1754 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1755 0 : bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1756 0 : res = pdev->resource + bar_idx;
1757 0 : size = pci_rebar_bytes_to_size(resource_size(res));
1758 0 : ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1759 0 : ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1760 0 : pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1761 : }
1762 : }
1763 :
1764 : /**
1765 : * pci_restore_state - Restore the saved state of a PCI device
1766 : * @dev: PCI device that we're dealing with
1767 : */
1768 0 : void pci_restore_state(struct pci_dev *dev)
1769 : {
1770 0 : if (!dev->state_saved)
1771 : return;
1772 :
1773 : /*
1774 : * Restore max latencies (in the LTR capability) before enabling
1775 : * LTR itself (in the PCIe capability).
1776 : */
1777 0 : pci_restore_ltr_state(dev);
1778 :
1779 0 : pci_restore_pcie_state(dev);
1780 0 : pci_restore_pasid_state(dev);
1781 0 : pci_restore_pri_state(dev);
1782 0 : pci_restore_ats_state(dev);
1783 0 : pci_restore_vc_state(dev);
1784 0 : pci_restore_rebar_state(dev);
1785 0 : pci_restore_dpc_state(dev);
1786 0 : pci_restore_ptm_state(dev);
1787 :
1788 0 : pci_aer_clear_status(dev);
1789 0 : pci_restore_aer_state(dev);
1790 :
1791 0 : pci_restore_config_space(dev);
1792 :
1793 0 : pci_restore_pcix_state(dev);
1794 0 : pci_restore_msi_state(dev);
1795 :
1796 : /* Restore ACS and IOV configuration state */
1797 0 : pci_enable_acs(dev);
1798 0 : pci_restore_iov_state(dev);
1799 :
1800 0 : dev->state_saved = false;
1801 : }
1802 : EXPORT_SYMBOL(pci_restore_state);
1803 :
1804 : struct pci_saved_state {
1805 : u32 config_space[16];
1806 : struct pci_cap_saved_data cap[];
1807 : };
1808 :
1809 : /**
1810 : * pci_store_saved_state - Allocate and return an opaque struct containing
1811 : * the device saved state.
1812 : * @dev: PCI device that we're dealing with
1813 : *
1814 : * Return NULL if no state or error.
1815 : */
1816 0 : struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1817 : {
1818 : struct pci_saved_state *state;
1819 : struct pci_cap_saved_state *tmp;
1820 : struct pci_cap_saved_data *cap;
1821 : size_t size;
1822 :
1823 0 : if (!dev->state_saved)
1824 : return NULL;
1825 :
1826 0 : size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1827 :
1828 0 : hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1829 0 : size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1830 :
1831 0 : state = kzalloc(size, GFP_KERNEL);
1832 0 : if (!state)
1833 : return NULL;
1834 :
1835 0 : memcpy(state->config_space, dev->saved_config_space,
1836 : sizeof(state->config_space));
1837 :
1838 0 : cap = state->cap;
1839 0 : hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1840 0 : size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1841 0 : memcpy(cap, &tmp->cap, len);
1842 0 : cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1843 : }
1844 : /* Empty cap_save terminates list */
1845 :
1846 : return state;
1847 : }
1848 : EXPORT_SYMBOL_GPL(pci_store_saved_state);
1849 :
1850 : /**
1851 : * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1852 : * @dev: PCI device that we're dealing with
1853 : * @state: Saved state returned from pci_store_saved_state()
1854 : */
1855 0 : int pci_load_saved_state(struct pci_dev *dev,
1856 : struct pci_saved_state *state)
1857 : {
1858 : struct pci_cap_saved_data *cap;
1859 :
1860 0 : dev->state_saved = false;
1861 :
1862 0 : if (!state)
1863 : return 0;
1864 :
1865 0 : memcpy(dev->saved_config_space, state->config_space,
1866 : sizeof(state->config_space));
1867 :
1868 0 : cap = state->cap;
1869 0 : while (cap->size) {
1870 : struct pci_cap_saved_state *tmp;
1871 :
1872 0 : tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1873 0 : if (!tmp || tmp->cap.size != cap->size)
1874 : return -EINVAL;
1875 :
1876 0 : memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1877 0 : cap = (struct pci_cap_saved_data *)((u8 *)cap +
1878 0 : sizeof(struct pci_cap_saved_data) + cap->size);
1879 : }
1880 :
1881 0 : dev->state_saved = true;
1882 0 : return 0;
1883 : }
1884 : EXPORT_SYMBOL_GPL(pci_load_saved_state);
1885 :
1886 : /**
1887 : * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1888 : * and free the memory allocated for it.
1889 : * @dev: PCI device that we're dealing with
1890 : * @state: Pointer to saved state returned from pci_store_saved_state()
1891 : */
1892 0 : int pci_load_and_free_saved_state(struct pci_dev *dev,
1893 : struct pci_saved_state **state)
1894 : {
1895 0 : int ret = pci_load_saved_state(dev, *state);
1896 0 : kfree(*state);
1897 0 : *state = NULL;
1898 0 : return ret;
1899 : }
1900 : EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1901 :
1902 0 : int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1903 : {
1904 0 : return pci_enable_resources(dev, bars);
1905 : }
1906 :
1907 0 : static int do_pci_enable_device(struct pci_dev *dev, int bars)
1908 : {
1909 : int err;
1910 : struct pci_dev *bridge;
1911 : u16 cmd;
1912 : u8 pin;
1913 :
1914 0 : err = pci_set_power_state(dev, PCI_D0);
1915 0 : if (err < 0 && err != -EIO)
1916 : return err;
1917 :
1918 0 : bridge = pci_upstream_bridge(dev);
1919 0 : if (bridge)
1920 0 : pcie_aspm_powersave_config_link(bridge);
1921 :
1922 0 : err = pcibios_enable_device(dev, bars);
1923 0 : if (err < 0)
1924 : return err;
1925 0 : pci_fixup_device(pci_fixup_enable, dev);
1926 :
1927 0 : if (dev->msi_enabled || dev->msix_enabled)
1928 : return 0;
1929 :
1930 0 : pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1931 0 : if (pin) {
1932 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
1933 0 : if (cmd & PCI_COMMAND_INTX_DISABLE)
1934 0 : pci_write_config_word(dev, PCI_COMMAND,
1935 : cmd & ~PCI_COMMAND_INTX_DISABLE);
1936 : }
1937 :
1938 : return 0;
1939 : }
1940 :
1941 : /**
1942 : * pci_reenable_device - Resume abandoned device
1943 : * @dev: PCI device to be resumed
1944 : *
1945 : * NOTE: This function is a backend of pci_default_resume() and is not supposed
1946 : * to be called by normal code, write proper resume handler and use it instead.
1947 : */
1948 0 : int pci_reenable_device(struct pci_dev *dev)
1949 : {
1950 0 : if (pci_is_enabled(dev))
1951 0 : return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1952 : return 0;
1953 : }
1954 : EXPORT_SYMBOL(pci_reenable_device);
1955 :
1956 0 : static void pci_enable_bridge(struct pci_dev *dev)
1957 : {
1958 : struct pci_dev *bridge;
1959 : int retval;
1960 :
1961 0 : bridge = pci_upstream_bridge(dev);
1962 0 : if (bridge)
1963 0 : pci_enable_bridge(bridge);
1964 :
1965 0 : if (pci_is_enabled(dev)) {
1966 0 : if (!dev->is_busmaster)
1967 : pci_set_master(dev);
1968 : return;
1969 : }
1970 :
1971 0 : retval = pci_enable_device(dev);
1972 0 : if (retval)
1973 0 : pci_err(dev, "Error enabling bridge (%d), continuing\n",
1974 : retval);
1975 : pci_set_master(dev);
1976 : }
1977 :
1978 0 : static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1979 : {
1980 : struct pci_dev *bridge;
1981 : int err;
1982 0 : int i, bars = 0;
1983 :
1984 : /*
1985 : * Power state could be unknown at this point, either due to a fresh
1986 : * boot or a device removal call. So get the current power state
1987 : * so that things like MSI message writing will behave as expected
1988 : * (e.g. if the device really is in D0 at enable time).
1989 : */
1990 0 : pci_update_current_state(dev, dev->current_state);
1991 :
1992 0 : if (atomic_inc_return(&dev->enable_cnt) > 1)
1993 : return 0; /* already enabled */
1994 :
1995 0 : bridge = pci_upstream_bridge(dev);
1996 0 : if (bridge)
1997 0 : pci_enable_bridge(bridge);
1998 :
1999 : /* only skip sriov related */
2000 0 : for (i = 0; i <= PCI_ROM_RESOURCE; i++)
2001 0 : if (dev->resource[i].flags & flags)
2002 0 : bars |= (1 << i);
2003 0 : for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
2004 0 : if (dev->resource[i].flags & flags)
2005 0 : bars |= (1 << i);
2006 :
2007 0 : err = do_pci_enable_device(dev, bars);
2008 0 : if (err < 0)
2009 0 : atomic_dec(&dev->enable_cnt);
2010 : return err;
2011 : }
2012 :
2013 : /**
2014 : * pci_enable_device_io - Initialize a device for use with IO space
2015 : * @dev: PCI device to be initialized
2016 : *
2017 : * Initialize device before it's used by a driver. Ask low-level code
2018 : * to enable I/O resources. Wake up the device if it was suspended.
2019 : * Beware, this function can fail.
2020 : */
2021 0 : int pci_enable_device_io(struct pci_dev *dev)
2022 : {
2023 0 : return pci_enable_device_flags(dev, IORESOURCE_IO);
2024 : }
2025 : EXPORT_SYMBOL(pci_enable_device_io);
2026 :
2027 : /**
2028 : * pci_enable_device_mem - Initialize a device for use with Memory space
2029 : * @dev: PCI device to be initialized
2030 : *
2031 : * Initialize device before it's used by a driver. Ask low-level code
2032 : * to enable Memory resources. Wake up the device if it was suspended.
2033 : * Beware, this function can fail.
2034 : */
2035 0 : int pci_enable_device_mem(struct pci_dev *dev)
2036 : {
2037 0 : return pci_enable_device_flags(dev, IORESOURCE_MEM);
2038 : }
2039 : EXPORT_SYMBOL(pci_enable_device_mem);
2040 :
2041 : /**
2042 : * pci_enable_device - Initialize device before it's used by a driver.
2043 : * @dev: PCI device to be initialized
2044 : *
2045 : * Initialize device before it's used by a driver. Ask low-level code
2046 : * to enable I/O and memory. Wake up the device if it was suspended.
2047 : * Beware, this function can fail.
2048 : *
2049 : * Note we don't actually enable the device many times if we call
2050 : * this function repeatedly (we just increment the count).
2051 : */
2052 0 : int pci_enable_device(struct pci_dev *dev)
2053 : {
2054 0 : return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
2055 : }
2056 : EXPORT_SYMBOL(pci_enable_device);
2057 :
2058 : /*
2059 : * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2060 : * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2061 : * there's no need to track it separately. pci_devres is initialized
2062 : * when a device is enabled using managed PCI device enable interface.
2063 : */
2064 : struct pci_devres {
2065 : unsigned int enabled:1;
2066 : unsigned int pinned:1;
2067 : unsigned int orig_intx:1;
2068 : unsigned int restore_intx:1;
2069 : unsigned int mwi:1;
2070 : u32 region_mask;
2071 : };
2072 :
2073 0 : static void pcim_release(struct device *gendev, void *res)
2074 : {
2075 0 : struct pci_dev *dev = to_pci_dev(gendev);
2076 0 : struct pci_devres *this = res;
2077 : int i;
2078 :
2079 0 : for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2080 0 : if (this->region_mask & (1 << i))
2081 0 : pci_release_region(dev, i);
2082 :
2083 0 : if (this->mwi)
2084 0 : pci_clear_mwi(dev);
2085 :
2086 0 : if (this->restore_intx)
2087 0 : pci_intx(dev, this->orig_intx);
2088 :
2089 0 : if (this->enabled && !this->pinned)
2090 0 : pci_disable_device(dev);
2091 0 : }
2092 :
2093 0 : static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2094 : {
2095 : struct pci_devres *dr, *new_dr;
2096 :
2097 0 : dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2098 0 : if (dr)
2099 : return dr;
2100 :
2101 0 : new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2102 0 : if (!new_dr)
2103 : return NULL;
2104 0 : return devres_get(&pdev->dev, new_dr, NULL, NULL);
2105 : }
2106 :
2107 : static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2108 : {
2109 0 : if (pci_is_managed(pdev))
2110 0 : return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2111 : return NULL;
2112 : }
2113 :
2114 : /**
2115 : * pcim_enable_device - Managed pci_enable_device()
2116 : * @pdev: PCI device to be initialized
2117 : *
2118 : * Managed pci_enable_device().
2119 : */
2120 0 : int pcim_enable_device(struct pci_dev *pdev)
2121 : {
2122 : struct pci_devres *dr;
2123 : int rc;
2124 :
2125 0 : dr = get_pci_dr(pdev);
2126 0 : if (unlikely(!dr))
2127 : return -ENOMEM;
2128 0 : if (dr->enabled)
2129 : return 0;
2130 :
2131 0 : rc = pci_enable_device(pdev);
2132 0 : if (!rc) {
2133 0 : pdev->is_managed = 1;
2134 0 : dr->enabled = 1;
2135 : }
2136 : return rc;
2137 : }
2138 : EXPORT_SYMBOL(pcim_enable_device);
2139 :
2140 : /**
2141 : * pcim_pin_device - Pin managed PCI device
2142 : * @pdev: PCI device to pin
2143 : *
2144 : * Pin managed PCI device @pdev. Pinned device won't be disabled on
2145 : * driver detach. @pdev must have been enabled with
2146 : * pcim_enable_device().
2147 : */
2148 0 : void pcim_pin_device(struct pci_dev *pdev)
2149 : {
2150 : struct pci_devres *dr;
2151 :
2152 0 : dr = find_pci_dr(pdev);
2153 0 : WARN_ON(!dr || !dr->enabled);
2154 0 : if (dr)
2155 0 : dr->pinned = 1;
2156 0 : }
2157 : EXPORT_SYMBOL(pcim_pin_device);
2158 :
2159 : /*
2160 : * pcibios_device_add - provide arch specific hooks when adding device dev
2161 : * @dev: the PCI device being added
2162 : *
2163 : * Permits the platform to provide architecture specific functionality when
2164 : * devices are added. This is the default implementation. Architecture
2165 : * implementations can override this.
2166 : */
2167 0 : int __weak pcibios_device_add(struct pci_dev *dev)
2168 : {
2169 0 : return 0;
2170 : }
2171 :
2172 : /**
2173 : * pcibios_release_device - provide arch specific hooks when releasing
2174 : * device dev
2175 : * @dev: the PCI device being released
2176 : *
2177 : * Permits the platform to provide architecture specific functionality when
2178 : * devices are released. This is the default implementation. Architecture
2179 : * implementations can override this.
2180 : */
2181 0 : void __weak pcibios_release_device(struct pci_dev *dev) {}
2182 :
2183 : /**
2184 : * pcibios_disable_device - disable arch specific PCI resources for device dev
2185 : * @dev: the PCI device to disable
2186 : *
2187 : * Disables architecture specific PCI resources for the device. This
2188 : * is the default implementation. Architecture implementations can
2189 : * override this.
2190 : */
2191 0 : void __weak pcibios_disable_device(struct pci_dev *dev) {}
2192 :
2193 : /**
2194 : * pcibios_penalize_isa_irq - penalize an ISA IRQ
2195 : * @irq: ISA IRQ to penalize
2196 : * @active: IRQ active or not
2197 : *
2198 : * Permits the platform to provide architecture-specific functionality when
2199 : * penalizing ISA IRQs. This is the default implementation. Architecture
2200 : * implementations can override this.
2201 : */
2202 0 : void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2203 :
2204 0 : static void do_pci_disable_device(struct pci_dev *dev)
2205 : {
2206 : u16 pci_command;
2207 :
2208 0 : pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2209 0 : if (pci_command & PCI_COMMAND_MASTER) {
2210 0 : pci_command &= ~PCI_COMMAND_MASTER;
2211 0 : pci_write_config_word(dev, PCI_COMMAND, pci_command);
2212 : }
2213 :
2214 0 : pcibios_disable_device(dev);
2215 0 : }
2216 :
2217 : /**
2218 : * pci_disable_enabled_device - Disable device without updating enable_cnt
2219 : * @dev: PCI device to disable
2220 : *
2221 : * NOTE: This function is a backend of PCI power management routines and is
2222 : * not supposed to be called drivers.
2223 : */
2224 0 : void pci_disable_enabled_device(struct pci_dev *dev)
2225 : {
2226 0 : if (pci_is_enabled(dev))
2227 0 : do_pci_disable_device(dev);
2228 0 : }
2229 :
2230 : /**
2231 : * pci_disable_device - Disable PCI device after use
2232 : * @dev: PCI device to be disabled
2233 : *
2234 : * Signal to the system that the PCI device is not in use by the system
2235 : * anymore. This only involves disabling PCI bus-mastering, if active.
2236 : *
2237 : * Note we don't actually disable the device until all callers of
2238 : * pci_enable_device() have called pci_disable_device().
2239 : */
2240 0 : void pci_disable_device(struct pci_dev *dev)
2241 : {
2242 : struct pci_devres *dr;
2243 :
2244 0 : dr = find_pci_dr(dev);
2245 0 : if (dr)
2246 0 : dr->enabled = 0;
2247 :
2248 0 : dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2249 : "disabling already-disabled device");
2250 :
2251 0 : if (atomic_dec_return(&dev->enable_cnt) != 0)
2252 : return;
2253 :
2254 0 : do_pci_disable_device(dev);
2255 :
2256 0 : dev->is_busmaster = 0;
2257 : }
2258 : EXPORT_SYMBOL(pci_disable_device);
2259 :
2260 : /**
2261 : * pcibios_set_pcie_reset_state - set reset state for device dev
2262 : * @dev: the PCIe device reset
2263 : * @state: Reset state to enter into
2264 : *
2265 : * Set the PCIe reset state for the device. This is the default
2266 : * implementation. Architecture implementations can override this.
2267 : */
2268 0 : int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2269 : enum pcie_reset_state state)
2270 : {
2271 0 : return -EINVAL;
2272 : }
2273 :
2274 : /**
2275 : * pci_set_pcie_reset_state - set reset state for device dev
2276 : * @dev: the PCIe device reset
2277 : * @state: Reset state to enter into
2278 : *
2279 : * Sets the PCI reset state for the device.
2280 : */
2281 0 : int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2282 : {
2283 0 : return pcibios_set_pcie_reset_state(dev, state);
2284 : }
2285 : EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2286 :
2287 : #ifdef CONFIG_PCIEAER
2288 : void pcie_clear_device_status(struct pci_dev *dev)
2289 : {
2290 : u16 sta;
2291 :
2292 : pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2293 : pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2294 : }
2295 : #endif
2296 :
2297 : /**
2298 : * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2299 : * @dev: PCIe root port or event collector.
2300 : */
2301 0 : void pcie_clear_root_pme_status(struct pci_dev *dev)
2302 : {
2303 0 : pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2304 0 : }
2305 :
2306 : /**
2307 : * pci_check_pme_status - Check if given device has generated PME.
2308 : * @dev: Device to check.
2309 : *
2310 : * Check the PME status of the device and if set, clear it and clear PME enable
2311 : * (if set). Return 'true' if PME status and PME enable were both set or
2312 : * 'false' otherwise.
2313 : */
2314 0 : bool pci_check_pme_status(struct pci_dev *dev)
2315 : {
2316 : int pmcsr_pos;
2317 : u16 pmcsr;
2318 0 : bool ret = false;
2319 :
2320 0 : if (!dev->pm_cap)
2321 : return false;
2322 :
2323 0 : pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2324 0 : pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2325 0 : if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2326 : return false;
2327 :
2328 : /* Clear PME status. */
2329 0 : pmcsr |= PCI_PM_CTRL_PME_STATUS;
2330 0 : if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2331 : /* Disable PME to avoid interrupt flood. */
2332 0 : pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2333 0 : ret = true;
2334 : }
2335 :
2336 0 : pci_write_config_word(dev, pmcsr_pos, pmcsr);
2337 :
2338 0 : return ret;
2339 : }
2340 :
2341 : /**
2342 : * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2343 : * @dev: Device to handle.
2344 : * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2345 : *
2346 : * Check if @dev has generated PME and queue a resume request for it in that
2347 : * case.
2348 : */
2349 0 : static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2350 : {
2351 0 : if (pme_poll_reset && dev->pme_poll)
2352 0 : dev->pme_poll = false;
2353 :
2354 0 : if (pci_check_pme_status(dev)) {
2355 0 : pci_wakeup_event(dev);
2356 0 : pm_request_resume(&dev->dev);
2357 : }
2358 0 : return 0;
2359 : }
2360 :
2361 : /**
2362 : * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2363 : * @bus: Top bus of the subtree to walk.
2364 : */
2365 0 : void pci_pme_wakeup_bus(struct pci_bus *bus)
2366 : {
2367 0 : if (bus)
2368 0 : pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2369 0 : }
2370 :
2371 :
2372 : /**
2373 : * pci_pme_capable - check the capability of PCI device to generate PME#
2374 : * @dev: PCI device to handle.
2375 : * @state: PCI state from which device will issue PME#.
2376 : */
2377 0 : bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2378 : {
2379 0 : if (!dev->pm_cap)
2380 : return false;
2381 :
2382 0 : return !!(dev->pme_support & (1 << state));
2383 : }
2384 : EXPORT_SYMBOL(pci_pme_capable);
2385 :
2386 0 : static void pci_pme_list_scan(struct work_struct *work)
2387 : {
2388 : struct pci_pme_device *pme_dev, *n;
2389 :
2390 0 : mutex_lock(&pci_pme_list_mutex);
2391 0 : list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2392 0 : if (pme_dev->dev->pme_poll) {
2393 : struct pci_dev *bridge;
2394 :
2395 0 : bridge = pme_dev->dev->bus->self;
2396 : /*
2397 : * If bridge is in low power state, the
2398 : * configuration space of subordinate devices
2399 : * may be not accessible
2400 : */
2401 0 : if (bridge && bridge->current_state != PCI_D0)
2402 0 : continue;
2403 : /*
2404 : * If the device is in D3cold it should not be
2405 : * polled either.
2406 : */
2407 0 : if (pme_dev->dev->current_state == PCI_D3cold)
2408 0 : continue;
2409 :
2410 0 : pci_pme_wakeup(pme_dev->dev, NULL);
2411 : } else {
2412 0 : list_del(&pme_dev->list);
2413 0 : kfree(pme_dev);
2414 : }
2415 : }
2416 0 : if (!list_empty(&pci_pme_list))
2417 0 : queue_delayed_work(system_freezable_wq, &pci_pme_work,
2418 : msecs_to_jiffies(PME_TIMEOUT));
2419 0 : mutex_unlock(&pci_pme_list_mutex);
2420 0 : }
2421 :
2422 0 : static void __pci_pme_active(struct pci_dev *dev, bool enable)
2423 : {
2424 : u16 pmcsr;
2425 :
2426 0 : if (!dev->pme_support)
2427 0 : return;
2428 :
2429 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2430 : /* Clear PME_Status by writing 1 to it and enable PME# */
2431 0 : pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2432 0 : if (!enable)
2433 0 : pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2434 :
2435 0 : pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2436 : }
2437 :
2438 : /**
2439 : * pci_pme_restore - Restore PME configuration after config space restore.
2440 : * @dev: PCI device to update.
2441 : */
2442 0 : void pci_pme_restore(struct pci_dev *dev)
2443 : {
2444 : u16 pmcsr;
2445 :
2446 0 : if (!dev->pme_support)
2447 0 : return;
2448 :
2449 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2450 0 : if (dev->wakeup_prepared) {
2451 0 : pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2452 0 : pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2453 : } else {
2454 0 : pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2455 0 : pmcsr |= PCI_PM_CTRL_PME_STATUS;
2456 : }
2457 0 : pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2458 : }
2459 :
2460 : /**
2461 : * pci_pme_active - enable or disable PCI device's PME# function
2462 : * @dev: PCI device to handle.
2463 : * @enable: 'true' to enable PME# generation; 'false' to disable it.
2464 : *
2465 : * The caller must verify that the device is capable of generating PME# before
2466 : * calling this function with @enable equal to 'true'.
2467 : */
2468 0 : void pci_pme_active(struct pci_dev *dev, bool enable)
2469 : {
2470 0 : __pci_pme_active(dev, enable);
2471 :
2472 : /*
2473 : * PCI (as opposed to PCIe) PME requires that the device have
2474 : * its PME# line hooked up correctly. Not all hardware vendors
2475 : * do this, so the PME never gets delivered and the device
2476 : * remains asleep. The easiest way around this is to
2477 : * periodically walk the list of suspended devices and check
2478 : * whether any have their PME flag set. The assumption is that
2479 : * we'll wake up often enough anyway that this won't be a huge
2480 : * hit, and the power savings from the devices will still be a
2481 : * win.
2482 : *
2483 : * Although PCIe uses in-band PME message instead of PME# line
2484 : * to report PME, PME does not work for some PCIe devices in
2485 : * reality. For example, there are devices that set their PME
2486 : * status bits, but don't really bother to send a PME message;
2487 : * there are PCI Express Root Ports that don't bother to
2488 : * trigger interrupts when they receive PME messages from the
2489 : * devices below. So PME poll is used for PCIe devices too.
2490 : */
2491 :
2492 0 : if (dev->pme_poll) {
2493 : struct pci_pme_device *pme_dev;
2494 0 : if (enable) {
2495 0 : pme_dev = kmalloc(sizeof(struct pci_pme_device),
2496 : GFP_KERNEL);
2497 0 : if (!pme_dev) {
2498 0 : pci_warn(dev, "can't enable PME#\n");
2499 0 : return;
2500 : }
2501 0 : pme_dev->dev = dev;
2502 0 : mutex_lock(&pci_pme_list_mutex);
2503 0 : list_add(&pme_dev->list, &pci_pme_list);
2504 0 : if (list_is_singular(&pci_pme_list))
2505 0 : queue_delayed_work(system_freezable_wq,
2506 : &pci_pme_work,
2507 : msecs_to_jiffies(PME_TIMEOUT));
2508 0 : mutex_unlock(&pci_pme_list_mutex);
2509 : } else {
2510 0 : mutex_lock(&pci_pme_list_mutex);
2511 0 : list_for_each_entry(pme_dev, &pci_pme_list, list) {
2512 0 : if (pme_dev->dev == dev) {
2513 0 : list_del(&pme_dev->list);
2514 0 : kfree(pme_dev);
2515 0 : break;
2516 : }
2517 : }
2518 0 : mutex_unlock(&pci_pme_list_mutex);
2519 : }
2520 : }
2521 :
2522 : pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2523 : }
2524 : EXPORT_SYMBOL(pci_pme_active);
2525 :
2526 : /**
2527 : * __pci_enable_wake - enable PCI device as wakeup event source
2528 : * @dev: PCI device affected
2529 : * @state: PCI state from which device will issue wakeup events
2530 : * @enable: True to enable event generation; false to disable
2531 : *
2532 : * This enables the device as a wakeup event source, or disables it.
2533 : * When such events involves platform-specific hooks, those hooks are
2534 : * called automatically by this routine.
2535 : *
2536 : * Devices with legacy power management (no standard PCI PM capabilities)
2537 : * always require such platform hooks.
2538 : *
2539 : * RETURN VALUE:
2540 : * 0 is returned on success
2541 : * -EINVAL is returned if device is not supposed to wake up the system
2542 : * Error code depending on the platform is returned if both the platform and
2543 : * the native mechanism fail to enable the generation of wake-up events
2544 : */
2545 0 : static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2546 : {
2547 0 : int ret = 0;
2548 :
2549 : /*
2550 : * Bridges that are not power-manageable directly only signal
2551 : * wakeup on behalf of subordinate devices which is set up
2552 : * elsewhere, so skip them. However, bridges that are
2553 : * power-manageable may signal wakeup for themselves (for example,
2554 : * on a hotplug event) and they need to be covered here.
2555 : */
2556 0 : if (!pci_power_manageable(dev))
2557 : return 0;
2558 :
2559 : /* Don't do the same thing twice in a row for one device. */
2560 0 : if (!!enable == !!dev->wakeup_prepared)
2561 : return 0;
2562 :
2563 : /*
2564 : * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2565 : * Anderson we should be doing PME# wake enable followed by ACPI wake
2566 : * enable. To disable wake-up we call the platform first, for symmetry.
2567 : */
2568 :
2569 0 : if (enable) {
2570 : int error;
2571 :
2572 : /*
2573 : * Enable PME signaling if the device can signal PME from
2574 : * D3cold regardless of whether or not it can signal PME from
2575 : * the current target state, because that will allow it to
2576 : * signal PME when the hierarchy above it goes into D3cold and
2577 : * the device itself ends up in D3cold as a result of that.
2578 : */
2579 0 : if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2580 0 : pci_pme_active(dev, true);
2581 : else
2582 : ret = 1;
2583 0 : error = platform_pci_set_wakeup(dev, true);
2584 0 : if (ret)
2585 0 : ret = error;
2586 0 : if (!ret)
2587 0 : dev->wakeup_prepared = true;
2588 : } else {
2589 0 : platform_pci_set_wakeup(dev, false);
2590 0 : pci_pme_active(dev, false);
2591 0 : dev->wakeup_prepared = false;
2592 : }
2593 :
2594 : return ret;
2595 : }
2596 :
2597 : /**
2598 : * pci_enable_wake - change wakeup settings for a PCI device
2599 : * @pci_dev: Target device
2600 : * @state: PCI state from which device will issue wakeup events
2601 : * @enable: Whether or not to enable event generation
2602 : *
2603 : * If @enable is set, check device_may_wakeup() for the device before calling
2604 : * __pci_enable_wake() for it.
2605 : */
2606 0 : int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2607 : {
2608 0 : if (enable && !device_may_wakeup(&pci_dev->dev))
2609 : return -EINVAL;
2610 :
2611 0 : return __pci_enable_wake(pci_dev, state, enable);
2612 : }
2613 : EXPORT_SYMBOL(pci_enable_wake);
2614 :
2615 : /**
2616 : * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2617 : * @dev: PCI device to prepare
2618 : * @enable: True to enable wake-up event generation; false to disable
2619 : *
2620 : * Many drivers want the device to wake up the system from D3_hot or D3_cold
2621 : * and this function allows them to set that up cleanly - pci_enable_wake()
2622 : * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2623 : * ordering constraints.
2624 : *
2625 : * This function only returns error code if the device is not allowed to wake
2626 : * up the system from sleep or it is not capable of generating PME# from both
2627 : * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2628 : */
2629 0 : int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2630 : {
2631 0 : return pci_pme_capable(dev, PCI_D3cold) ?
2632 0 : pci_enable_wake(dev, PCI_D3cold, enable) :
2633 0 : pci_enable_wake(dev, PCI_D3hot, enable);
2634 : }
2635 : EXPORT_SYMBOL(pci_wake_from_d3);
2636 :
2637 : /**
2638 : * pci_target_state - find an appropriate low power state for a given PCI dev
2639 : * @dev: PCI device
2640 : * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2641 : *
2642 : * Use underlying platform code to find a supported low power state for @dev.
2643 : * If the platform can't manage @dev, return the deepest state from which it
2644 : * can generate wake events, based on any available PME info.
2645 : */
2646 0 : static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2647 : {
2648 0 : if (platform_pci_power_manageable(dev)) {
2649 : /*
2650 : * Call the platform to find the target state for the device.
2651 : */
2652 : pci_power_t state = platform_pci_choose_state(dev);
2653 :
2654 : switch (state) {
2655 : case PCI_POWER_ERROR:
2656 : case PCI_UNKNOWN:
2657 : return PCI_D3hot;
2658 :
2659 : case PCI_D1:
2660 : case PCI_D2:
2661 : if (pci_no_d1d2(dev))
2662 : return PCI_D3hot;
2663 : }
2664 :
2665 : return state;
2666 : }
2667 :
2668 : /*
2669 : * If the device is in D3cold even though it's not power-manageable by
2670 : * the platform, it may have been powered down by non-standard means.
2671 : * Best to let it slumber.
2672 : */
2673 0 : if (dev->current_state == PCI_D3cold)
2674 : return PCI_D3cold;
2675 0 : else if (!dev->pm_cap)
2676 : return PCI_D0;
2677 :
2678 0 : if (wakeup && dev->pme_support) {
2679 : pci_power_t state = PCI_D3hot;
2680 :
2681 : /*
2682 : * Find the deepest state from which the device can generate
2683 : * PME#.
2684 : */
2685 0 : while (state && !(dev->pme_support & (1 << state)))
2686 0 : state--;
2687 :
2688 0 : if (state)
2689 : return state;
2690 0 : else if (dev->pme_support & 1)
2691 : return PCI_D0;
2692 : }
2693 :
2694 0 : return PCI_D3hot;
2695 : }
2696 :
2697 : /**
2698 : * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2699 : * into a sleep state
2700 : * @dev: Device to handle.
2701 : *
2702 : * Choose the power state appropriate for the device depending on whether
2703 : * it can wake up the system and/or is power manageable by the platform
2704 : * (PCI_D3hot is the default) and put the device into that state.
2705 : */
2706 0 : int pci_prepare_to_sleep(struct pci_dev *dev)
2707 : {
2708 0 : bool wakeup = device_may_wakeup(&dev->dev);
2709 0 : pci_power_t target_state = pci_target_state(dev, wakeup);
2710 : int error;
2711 :
2712 0 : if (target_state == PCI_POWER_ERROR)
2713 : return -EIO;
2714 :
2715 0 : pci_enable_wake(dev, target_state, wakeup);
2716 :
2717 0 : error = pci_set_power_state(dev, target_state);
2718 :
2719 0 : if (error)
2720 0 : pci_enable_wake(dev, target_state, false);
2721 :
2722 : return error;
2723 : }
2724 : EXPORT_SYMBOL(pci_prepare_to_sleep);
2725 :
2726 : /**
2727 : * pci_back_from_sleep - turn PCI device on during system-wide transition
2728 : * into working state
2729 : * @dev: Device to handle.
2730 : *
2731 : * Disable device's system wake-up capability and put it into D0.
2732 : */
2733 0 : int pci_back_from_sleep(struct pci_dev *dev)
2734 : {
2735 0 : int ret = pci_set_power_state(dev, PCI_D0);
2736 :
2737 0 : if (ret)
2738 : return ret;
2739 :
2740 0 : pci_enable_wake(dev, PCI_D0, false);
2741 0 : return 0;
2742 : }
2743 : EXPORT_SYMBOL(pci_back_from_sleep);
2744 :
2745 : /**
2746 : * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2747 : * @dev: PCI device being suspended.
2748 : *
2749 : * Prepare @dev to generate wake-up events at run time and put it into a low
2750 : * power state.
2751 : */
2752 0 : int pci_finish_runtime_suspend(struct pci_dev *dev)
2753 : {
2754 : pci_power_t target_state;
2755 : int error;
2756 :
2757 0 : target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2758 0 : if (target_state == PCI_POWER_ERROR)
2759 : return -EIO;
2760 :
2761 0 : __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2762 :
2763 0 : error = pci_set_power_state(dev, target_state);
2764 :
2765 0 : if (error)
2766 0 : pci_enable_wake(dev, target_state, false);
2767 :
2768 : return error;
2769 : }
2770 :
2771 : /**
2772 : * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2773 : * @dev: Device to check.
2774 : *
2775 : * Return true if the device itself is capable of generating wake-up events
2776 : * (through the platform or using the native PCIe PME) or if the device supports
2777 : * PME and one of its upstream bridges can generate wake-up events.
2778 : */
2779 0 : bool pci_dev_run_wake(struct pci_dev *dev)
2780 : {
2781 0 : struct pci_bus *bus = dev->bus;
2782 :
2783 0 : if (!dev->pme_support)
2784 : return false;
2785 :
2786 : /* PME-capable in principle, but not from the target power state */
2787 0 : if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2788 : return false;
2789 :
2790 0 : if (device_can_wakeup(&dev->dev))
2791 : return true;
2792 :
2793 0 : while (bus->parent) {
2794 0 : struct pci_dev *bridge = bus->self;
2795 :
2796 0 : if (device_can_wakeup(&bridge->dev))
2797 : return true;
2798 :
2799 : bus = bus->parent;
2800 : }
2801 :
2802 : /* We have reached the root bus. */
2803 0 : if (bus->bridge)
2804 0 : return device_can_wakeup(bus->bridge);
2805 :
2806 : return false;
2807 : }
2808 : EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2809 :
2810 : /**
2811 : * pci_dev_need_resume - Check if it is necessary to resume the device.
2812 : * @pci_dev: Device to check.
2813 : *
2814 : * Return 'true' if the device is not runtime-suspended or it has to be
2815 : * reconfigured due to wakeup settings difference between system and runtime
2816 : * suspend, or the current power state of it is not suitable for the upcoming
2817 : * (system-wide) transition.
2818 : */
2819 0 : bool pci_dev_need_resume(struct pci_dev *pci_dev)
2820 : {
2821 0 : struct device *dev = &pci_dev->dev;
2822 : pci_power_t target_state;
2823 :
2824 0 : if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2825 : return true;
2826 :
2827 0 : target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2828 :
2829 : /*
2830 : * If the earlier platform check has not triggered, D3cold is just power
2831 : * removal on top of D3hot, so no need to resume the device in that
2832 : * case.
2833 : */
2834 0 : return target_state != pci_dev->current_state &&
2835 0 : target_state != PCI_D3cold &&
2836 : pci_dev->current_state != PCI_D3hot;
2837 : }
2838 :
2839 : /**
2840 : * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2841 : * @pci_dev: Device to check.
2842 : *
2843 : * If the device is suspended and it is not configured for system wakeup,
2844 : * disable PME for it to prevent it from waking up the system unnecessarily.
2845 : *
2846 : * Note that if the device's power state is D3cold and the platform check in
2847 : * pci_dev_need_resume() has not triggered, the device's configuration need not
2848 : * be changed.
2849 : */
2850 0 : void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2851 : {
2852 0 : struct device *dev = &pci_dev->dev;
2853 :
2854 0 : spin_lock_irq(&dev->power.lock);
2855 :
2856 0 : if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2857 0 : pci_dev->current_state < PCI_D3cold)
2858 0 : __pci_pme_active(pci_dev, false);
2859 :
2860 0 : spin_unlock_irq(&dev->power.lock);
2861 0 : }
2862 :
2863 : /**
2864 : * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2865 : * @pci_dev: Device to handle.
2866 : *
2867 : * If the device is runtime suspended and wakeup-capable, enable PME for it as
2868 : * it might have been disabled during the prepare phase of system suspend if
2869 : * the device was not configured for system wakeup.
2870 : */
2871 0 : void pci_dev_complete_resume(struct pci_dev *pci_dev)
2872 : {
2873 0 : struct device *dev = &pci_dev->dev;
2874 :
2875 0 : if (!pci_dev_run_wake(pci_dev))
2876 : return;
2877 :
2878 0 : spin_lock_irq(&dev->power.lock);
2879 :
2880 0 : if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2881 0 : __pci_pme_active(pci_dev, true);
2882 :
2883 0 : spin_unlock_irq(&dev->power.lock);
2884 : }
2885 :
2886 : /**
2887 : * pci_choose_state - Choose the power state of a PCI device.
2888 : * @dev: Target PCI device.
2889 : * @state: Target state for the whole system.
2890 : *
2891 : * Returns PCI power state suitable for @dev and @state.
2892 : */
2893 0 : pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
2894 : {
2895 0 : if (state.event == PM_EVENT_ON)
2896 : return PCI_D0;
2897 :
2898 0 : return pci_target_state(dev, false);
2899 : }
2900 : EXPORT_SYMBOL(pci_choose_state);
2901 :
2902 0 : void pci_config_pm_runtime_get(struct pci_dev *pdev)
2903 : {
2904 0 : struct device *dev = &pdev->dev;
2905 0 : struct device *parent = dev->parent;
2906 :
2907 0 : if (parent)
2908 : pm_runtime_get_sync(parent);
2909 0 : pm_runtime_get_noresume(dev);
2910 : /*
2911 : * pdev->current_state is set to PCI_D3cold during suspending,
2912 : * so wait until suspending completes
2913 : */
2914 0 : pm_runtime_barrier(dev);
2915 : /*
2916 : * Only need to resume devices in D3cold, because config
2917 : * registers are still accessible for devices suspended but
2918 : * not in D3cold.
2919 : */
2920 0 : if (pdev->current_state == PCI_D3cold)
2921 : pm_runtime_resume(dev);
2922 0 : }
2923 :
2924 0 : void pci_config_pm_runtime_put(struct pci_dev *pdev)
2925 : {
2926 0 : struct device *dev = &pdev->dev;
2927 0 : struct device *parent = dev->parent;
2928 :
2929 0 : pm_runtime_put(dev);
2930 0 : if (parent)
2931 : pm_runtime_put_sync(parent);
2932 0 : }
2933 :
2934 : static const struct dmi_system_id bridge_d3_blacklist[] = {
2935 : #ifdef CONFIG_X86
2936 : {
2937 : /*
2938 : * Gigabyte X299 root port is not marked as hotplug capable
2939 : * which allows Linux to power manage it. However, this
2940 : * confuses the BIOS SMI handler so don't power manage root
2941 : * ports on that system.
2942 : */
2943 : .ident = "X299 DESIGNARE EX-CF",
2944 : .matches = {
2945 : DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2946 : DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2947 : },
2948 : },
2949 : {
2950 : /*
2951 : * Downstream device is not accessible after putting a root port
2952 : * into D3cold and back into D0 on Elo i2.
2953 : */
2954 : .ident = "Elo i2",
2955 : .matches = {
2956 : DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"),
2957 : DMI_MATCH(DMI_PRODUCT_NAME, "Elo i2"),
2958 : DMI_MATCH(DMI_PRODUCT_VERSION, "RevB"),
2959 : },
2960 : },
2961 : #endif
2962 : { }
2963 : };
2964 :
2965 : /**
2966 : * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2967 : * @bridge: Bridge to check
2968 : *
2969 : * This function checks if it is possible to move the bridge to D3.
2970 : * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2971 : */
2972 0 : bool pci_bridge_d3_possible(struct pci_dev *bridge)
2973 : {
2974 0 : if (!pci_is_pcie(bridge))
2975 : return false;
2976 :
2977 0 : switch (pci_pcie_type(bridge)) {
2978 : case PCI_EXP_TYPE_ROOT_PORT:
2979 : case PCI_EXP_TYPE_UPSTREAM:
2980 : case PCI_EXP_TYPE_DOWNSTREAM:
2981 0 : if (pci_bridge_d3_disable)
2982 : return false;
2983 :
2984 : /*
2985 : * Hotplug ports handled by firmware in System Management Mode
2986 : * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2987 : */
2988 0 : if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2989 : return false;
2990 :
2991 0 : if (pci_bridge_d3_force)
2992 : return true;
2993 :
2994 : /* Even the oldest 2010 Thunderbolt controller supports D3. */
2995 0 : if (bridge->is_thunderbolt)
2996 : return true;
2997 :
2998 : /* Platform might know better if the bridge supports D3 */
2999 0 : if (platform_pci_bridge_d3(bridge))
3000 : return true;
3001 :
3002 : /*
3003 : * Hotplug ports handled natively by the OS were not validated
3004 : * by vendors for runtime D3 at least until 2018 because there
3005 : * was no OS support.
3006 : */
3007 : if (bridge->is_hotplug_bridge)
3008 : return false;
3009 :
3010 : if (dmi_check_system(bridge_d3_blacklist))
3011 : return false;
3012 :
3013 : /*
3014 : * It should be safe to put PCIe ports from 2015 or newer
3015 : * to D3.
3016 : */
3017 : if (dmi_get_bios_year() >= 2015)
3018 : return true;
3019 : break;
3020 : }
3021 :
3022 : return false;
3023 : }
3024 :
3025 0 : static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
3026 : {
3027 0 : bool *d3cold_ok = data;
3028 :
3029 0 : if (/* The device needs to be allowed to go D3cold ... */
3030 0 : dev->no_d3cold || !dev->d3cold_allowed ||
3031 :
3032 : /* ... and if it is wakeup capable to do so from D3cold. */
3033 0 : (device_may_wakeup(&dev->dev) &&
3034 0 : !pci_pme_capable(dev, PCI_D3cold)) ||
3035 :
3036 : /* If it is a bridge it must be allowed to go to D3. */
3037 0 : !pci_power_manageable(dev))
3038 :
3039 0 : *d3cold_ok = false;
3040 :
3041 0 : return !*d3cold_ok;
3042 : }
3043 :
3044 : /*
3045 : * pci_bridge_d3_update - Update bridge D3 capabilities
3046 : * @dev: PCI device which is changed
3047 : *
3048 : * Update upstream bridge PM capabilities accordingly depending on if the
3049 : * device PM configuration was changed or the device is being removed. The
3050 : * change is also propagated upstream.
3051 : */
3052 0 : void pci_bridge_d3_update(struct pci_dev *dev)
3053 : {
3054 0 : bool remove = !device_is_registered(&dev->dev);
3055 : struct pci_dev *bridge;
3056 0 : bool d3cold_ok = true;
3057 :
3058 0 : bridge = pci_upstream_bridge(dev);
3059 0 : if (!bridge || !pci_bridge_d3_possible(bridge))
3060 0 : return;
3061 :
3062 : /*
3063 : * If D3 is currently allowed for the bridge, removing one of its
3064 : * children won't change that.
3065 : */
3066 0 : if (remove && bridge->bridge_d3)
3067 : return;
3068 :
3069 : /*
3070 : * If D3 is currently allowed for the bridge and a child is added or
3071 : * changed, disallowance of D3 can only be caused by that child, so
3072 : * we only need to check that single device, not any of its siblings.
3073 : *
3074 : * If D3 is currently not allowed for the bridge, checking the device
3075 : * first may allow us to skip checking its siblings.
3076 : */
3077 0 : if (!remove)
3078 0 : pci_dev_check_d3cold(dev, &d3cold_ok);
3079 :
3080 : /*
3081 : * If D3 is currently not allowed for the bridge, this may be caused
3082 : * either by the device being changed/removed or any of its siblings,
3083 : * so we need to go through all children to find out if one of them
3084 : * continues to block D3.
3085 : */
3086 0 : if (d3cold_ok && !bridge->bridge_d3)
3087 0 : pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3088 : &d3cold_ok);
3089 :
3090 0 : if (bridge->bridge_d3 != d3cold_ok) {
3091 0 : bridge->bridge_d3 = d3cold_ok;
3092 : /* Propagate change to upstream bridges */
3093 0 : pci_bridge_d3_update(bridge);
3094 : }
3095 : }
3096 :
3097 : /**
3098 : * pci_d3cold_enable - Enable D3cold for device
3099 : * @dev: PCI device to handle
3100 : *
3101 : * This function can be used in drivers to enable D3cold from the device
3102 : * they handle. It also updates upstream PCI bridge PM capabilities
3103 : * accordingly.
3104 : */
3105 0 : void pci_d3cold_enable(struct pci_dev *dev)
3106 : {
3107 0 : if (dev->no_d3cold) {
3108 0 : dev->no_d3cold = false;
3109 0 : pci_bridge_d3_update(dev);
3110 : }
3111 0 : }
3112 : EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3113 :
3114 : /**
3115 : * pci_d3cold_disable - Disable D3cold for device
3116 : * @dev: PCI device to handle
3117 : *
3118 : * This function can be used in drivers to disable D3cold from the device
3119 : * they handle. It also updates upstream PCI bridge PM capabilities
3120 : * accordingly.
3121 : */
3122 0 : void pci_d3cold_disable(struct pci_dev *dev)
3123 : {
3124 0 : if (!dev->no_d3cold) {
3125 0 : dev->no_d3cold = true;
3126 0 : pci_bridge_d3_update(dev);
3127 : }
3128 0 : }
3129 : EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3130 :
3131 : /**
3132 : * pci_pm_init - Initialize PM functions of given PCI device
3133 : * @dev: PCI device to handle.
3134 : */
3135 0 : void pci_pm_init(struct pci_dev *dev)
3136 : {
3137 : int pm;
3138 : u16 status;
3139 : u16 pmc;
3140 :
3141 0 : pm_runtime_forbid(&dev->dev);
3142 0 : pm_runtime_set_active(&dev->dev);
3143 0 : pm_runtime_enable(&dev->dev);
3144 0 : device_enable_async_suspend(&dev->dev);
3145 0 : dev->wakeup_prepared = false;
3146 :
3147 0 : dev->pm_cap = 0;
3148 0 : dev->pme_support = 0;
3149 :
3150 : /* find PCI PM capability in list */
3151 0 : pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3152 0 : if (!pm)
3153 0 : return;
3154 : /* Check device's ability to generate PME# */
3155 0 : pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3156 :
3157 0 : if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3158 0 : pci_err(dev, "unsupported PM cap regs version (%u)\n",
3159 : pmc & PCI_PM_CAP_VER_MASK);
3160 0 : return;
3161 : }
3162 :
3163 0 : dev->pm_cap = pm;
3164 0 : dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3165 0 : dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3166 0 : dev->bridge_d3 = pci_bridge_d3_possible(dev);
3167 0 : dev->d3cold_allowed = true;
3168 :
3169 0 : dev->d1_support = false;
3170 0 : dev->d2_support = false;
3171 0 : if (!pci_no_d1d2(dev)) {
3172 0 : if (pmc & PCI_PM_CAP_D1)
3173 0 : dev->d1_support = true;
3174 0 : if (pmc & PCI_PM_CAP_D2)
3175 0 : dev->d2_support = true;
3176 :
3177 0 : if (dev->d1_support || dev->d2_support)
3178 0 : pci_info(dev, "supports%s%s\n",
3179 : dev->d1_support ? " D1" : "",
3180 : dev->d2_support ? " D2" : "");
3181 : }
3182 :
3183 0 : pmc &= PCI_PM_CAP_PME_MASK;
3184 0 : if (pmc) {
3185 0 : pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3186 : (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3187 : (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3188 : (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3189 : (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3190 : (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3191 0 : dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3192 0 : dev->pme_poll = true;
3193 : /*
3194 : * Make device's PM flags reflect the wake-up capability, but
3195 : * let the user space enable it to wake up the system as needed.
3196 : */
3197 0 : device_set_wakeup_capable(&dev->dev, true);
3198 : /* Disable the PME# generation functionality */
3199 0 : pci_pme_active(dev, false);
3200 : }
3201 :
3202 0 : pci_read_config_word(dev, PCI_STATUS, &status);
3203 0 : if (status & PCI_STATUS_IMM_READY)
3204 0 : dev->imm_ready = 1;
3205 : }
3206 :
3207 : static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3208 : {
3209 0 : unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3210 :
3211 : switch (prop) {
3212 : case PCI_EA_P_MEM:
3213 : case PCI_EA_P_VF_MEM:
3214 : flags |= IORESOURCE_MEM;
3215 : break;
3216 : case PCI_EA_P_MEM_PREFETCH:
3217 : case PCI_EA_P_VF_MEM_PREFETCH:
3218 : flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3219 : break;
3220 : case PCI_EA_P_IO:
3221 : flags |= IORESOURCE_IO;
3222 : break;
3223 : default:
3224 : return 0;
3225 : }
3226 :
3227 : return flags;
3228 : }
3229 :
3230 : static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3231 : u8 prop)
3232 : {
3233 0 : if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3234 0 : return &dev->resource[bei];
3235 : #ifdef CONFIG_PCI_IOV
3236 : else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3237 : (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3238 : return &dev->resource[PCI_IOV_RESOURCES +
3239 : bei - PCI_EA_BEI_VF_BAR0];
3240 : #endif
3241 0 : else if (bei == PCI_EA_BEI_ROM)
3242 0 : return &dev->resource[PCI_ROM_RESOURCE];
3243 : else
3244 : return NULL;
3245 : }
3246 :
3247 : /* Read an Enhanced Allocation (EA) entry */
3248 0 : static int pci_ea_read(struct pci_dev *dev, int offset)
3249 : {
3250 : struct resource *res;
3251 0 : int ent_size, ent_offset = offset;
3252 : resource_size_t start, end;
3253 : unsigned long flags;
3254 : u32 dw0, bei, base, max_offset;
3255 : u8 prop;
3256 0 : bool support_64 = (sizeof(resource_size_t) >= 8);
3257 :
3258 0 : pci_read_config_dword(dev, ent_offset, &dw0);
3259 0 : ent_offset += 4;
3260 :
3261 : /* Entry size field indicates DWORDs after 1st */
3262 0 : ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3263 :
3264 0 : if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3265 : goto out;
3266 :
3267 0 : bei = (dw0 & PCI_EA_BEI) >> 4;
3268 0 : prop = (dw0 & PCI_EA_PP) >> 8;
3269 :
3270 : /*
3271 : * If the Property is in the reserved range, try the Secondary
3272 : * Property instead.
3273 : */
3274 0 : if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3275 0 : prop = (dw0 & PCI_EA_SP) >> 16;
3276 0 : if (prop > PCI_EA_P_BRIDGE_IO)
3277 : goto out;
3278 :
3279 0 : res = pci_ea_get_resource(dev, bei, prop);
3280 0 : if (!res) {
3281 0 : pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3282 0 : goto out;
3283 : }
3284 :
3285 0 : flags = pci_ea_flags(dev, prop);
3286 0 : if (!flags) {
3287 0 : pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3288 0 : goto out;
3289 : }
3290 :
3291 : /* Read Base */
3292 0 : pci_read_config_dword(dev, ent_offset, &base);
3293 0 : start = (base & PCI_EA_FIELD_MASK);
3294 0 : ent_offset += 4;
3295 :
3296 : /* Read MaxOffset */
3297 0 : pci_read_config_dword(dev, ent_offset, &max_offset);
3298 0 : ent_offset += 4;
3299 :
3300 : /* Read Base MSBs (if 64-bit entry) */
3301 0 : if (base & PCI_EA_IS_64) {
3302 : u32 base_upper;
3303 :
3304 0 : pci_read_config_dword(dev, ent_offset, &base_upper);
3305 0 : ent_offset += 4;
3306 :
3307 0 : flags |= IORESOURCE_MEM_64;
3308 :
3309 : /* entry starts above 32-bit boundary, can't use */
3310 : if (!support_64 && base_upper)
3311 : goto out;
3312 :
3313 : if (support_64)
3314 0 : start |= ((u64)base_upper << 32);
3315 : }
3316 :
3317 0 : end = start + (max_offset | 0x03);
3318 :
3319 : /* Read MaxOffset MSBs (if 64-bit entry) */
3320 0 : if (max_offset & PCI_EA_IS_64) {
3321 : u32 max_offset_upper;
3322 :
3323 0 : pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3324 0 : ent_offset += 4;
3325 :
3326 0 : flags |= IORESOURCE_MEM_64;
3327 :
3328 : /* entry too big, can't use */
3329 : if (!support_64 && max_offset_upper)
3330 : goto out;
3331 :
3332 : if (support_64)
3333 0 : end += ((u64)max_offset_upper << 32);
3334 : }
3335 :
3336 0 : if (end < start) {
3337 0 : pci_err(dev, "EA Entry crosses address boundary\n");
3338 0 : goto out;
3339 : }
3340 :
3341 0 : if (ent_size != ent_offset - offset) {
3342 0 : pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3343 : ent_size, ent_offset - offset);
3344 0 : goto out;
3345 : }
3346 :
3347 0 : res->name = pci_name(dev);
3348 0 : res->start = start;
3349 0 : res->end = end;
3350 0 : res->flags = flags;
3351 :
3352 0 : if (bei <= PCI_EA_BEI_BAR5)
3353 0 : pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3354 : bei, res, prop);
3355 0 : else if (bei == PCI_EA_BEI_ROM)
3356 0 : pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3357 : res, prop);
3358 0 : else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3359 0 : pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3360 : bei - PCI_EA_BEI_VF_BAR0, res, prop);
3361 : else
3362 0 : pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3363 : bei, res, prop);
3364 :
3365 : out:
3366 0 : return offset + ent_size;
3367 : }
3368 :
3369 : /* Enhanced Allocation Initialization */
3370 0 : void pci_ea_init(struct pci_dev *dev)
3371 : {
3372 : int ea;
3373 : u8 num_ent;
3374 : int offset;
3375 : int i;
3376 :
3377 : /* find PCI EA capability in list */
3378 0 : ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3379 0 : if (!ea)
3380 0 : return;
3381 :
3382 : /* determine the number of entries */
3383 0 : pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3384 : &num_ent);
3385 0 : num_ent &= PCI_EA_NUM_ENT_MASK;
3386 :
3387 0 : offset = ea + PCI_EA_FIRST_ENT;
3388 :
3389 : /* Skip DWORD 2 for type 1 functions */
3390 0 : if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3391 0 : offset += 4;
3392 :
3393 : /* parse each EA entry */
3394 0 : for (i = 0; i < num_ent; ++i)
3395 0 : offset = pci_ea_read(dev, offset);
3396 : }
3397 :
3398 : static void pci_add_saved_cap(struct pci_dev *pci_dev,
3399 : struct pci_cap_saved_state *new_cap)
3400 : {
3401 0 : hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3402 : }
3403 :
3404 : /**
3405 : * _pci_add_cap_save_buffer - allocate buffer for saving given
3406 : * capability registers
3407 : * @dev: the PCI device
3408 : * @cap: the capability to allocate the buffer for
3409 : * @extended: Standard or Extended capability ID
3410 : * @size: requested size of the buffer
3411 : */
3412 0 : static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3413 : bool extended, unsigned int size)
3414 : {
3415 : int pos;
3416 : struct pci_cap_saved_state *save_state;
3417 :
3418 0 : if (extended)
3419 0 : pos = pci_find_ext_capability(dev, cap);
3420 : else
3421 0 : pos = pci_find_capability(dev, cap);
3422 :
3423 0 : if (!pos)
3424 : return 0;
3425 :
3426 0 : save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3427 0 : if (!save_state)
3428 : return -ENOMEM;
3429 :
3430 0 : save_state->cap.cap_nr = cap;
3431 0 : save_state->cap.cap_extended = extended;
3432 0 : save_state->cap.size = size;
3433 0 : pci_add_saved_cap(dev, save_state);
3434 :
3435 0 : return 0;
3436 : }
3437 :
3438 0 : int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3439 : {
3440 0 : return _pci_add_cap_save_buffer(dev, cap, false, size);
3441 : }
3442 :
3443 0 : int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3444 : {
3445 0 : return _pci_add_cap_save_buffer(dev, cap, true, size);
3446 : }
3447 :
3448 : /**
3449 : * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3450 : * @dev: the PCI device
3451 : */
3452 0 : void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3453 : {
3454 : int error;
3455 :
3456 0 : error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3457 : PCI_EXP_SAVE_REGS * sizeof(u16));
3458 0 : if (error)
3459 0 : pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3460 :
3461 0 : error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3462 0 : if (error)
3463 0 : pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3464 :
3465 0 : error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3466 : 2 * sizeof(u16));
3467 0 : if (error)
3468 0 : pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3469 :
3470 0 : pci_allocate_vc_save_buffers(dev);
3471 0 : }
3472 :
3473 0 : void pci_free_cap_save_buffers(struct pci_dev *dev)
3474 : {
3475 : struct pci_cap_saved_state *tmp;
3476 : struct hlist_node *n;
3477 :
3478 0 : hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3479 0 : kfree(tmp);
3480 0 : }
3481 :
3482 : /**
3483 : * pci_configure_ari - enable or disable ARI forwarding
3484 : * @dev: the PCI device
3485 : *
3486 : * If @dev and its upstream bridge both support ARI, enable ARI in the
3487 : * bridge. Otherwise, disable ARI in the bridge.
3488 : */
3489 0 : void pci_configure_ari(struct pci_dev *dev)
3490 : {
3491 : u32 cap;
3492 : struct pci_dev *bridge;
3493 :
3494 0 : if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3495 0 : return;
3496 :
3497 0 : bridge = dev->bus->self;
3498 0 : if (!bridge)
3499 : return;
3500 :
3501 0 : pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3502 0 : if (!(cap & PCI_EXP_DEVCAP2_ARI))
3503 : return;
3504 :
3505 0 : if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3506 0 : pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3507 : PCI_EXP_DEVCTL2_ARI);
3508 0 : bridge->ari_enabled = 1;
3509 : } else {
3510 0 : pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3511 : PCI_EXP_DEVCTL2_ARI);
3512 0 : bridge->ari_enabled = 0;
3513 : }
3514 : }
3515 :
3516 0 : static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3517 : {
3518 : int pos;
3519 : u16 cap, ctrl;
3520 :
3521 0 : pos = pdev->acs_cap;
3522 0 : if (!pos)
3523 : return false;
3524 :
3525 : /*
3526 : * Except for egress control, capabilities are either required
3527 : * or only required if controllable. Features missing from the
3528 : * capability field can therefore be assumed as hard-wired enabled.
3529 : */
3530 0 : pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3531 0 : acs_flags &= (cap | PCI_ACS_EC);
3532 :
3533 0 : pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3534 0 : return (ctrl & acs_flags) == acs_flags;
3535 : }
3536 :
3537 : /**
3538 : * pci_acs_enabled - test ACS against required flags for a given device
3539 : * @pdev: device to test
3540 : * @acs_flags: required PCI ACS flags
3541 : *
3542 : * Return true if the device supports the provided flags. Automatically
3543 : * filters out flags that are not implemented on multifunction devices.
3544 : *
3545 : * Note that this interface checks the effective ACS capabilities of the
3546 : * device rather than the actual capabilities. For instance, most single
3547 : * function endpoints are not required to support ACS because they have no
3548 : * opportunity for peer-to-peer access. We therefore return 'true'
3549 : * regardless of whether the device exposes an ACS capability. This makes
3550 : * it much easier for callers of this function to ignore the actual type
3551 : * or topology of the device when testing ACS support.
3552 : */
3553 0 : bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3554 : {
3555 : int ret;
3556 :
3557 0 : ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3558 0 : if (ret >= 0)
3559 0 : return ret > 0;
3560 :
3561 : /*
3562 : * Conventional PCI and PCI-X devices never support ACS, either
3563 : * effectively or actually. The shared bus topology implies that
3564 : * any device on the bus can receive or snoop DMA.
3565 : */
3566 0 : if (!pci_is_pcie(pdev))
3567 : return false;
3568 :
3569 0 : switch (pci_pcie_type(pdev)) {
3570 : /*
3571 : * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3572 : * but since their primary interface is PCI/X, we conservatively
3573 : * handle them as we would a non-PCIe device.
3574 : */
3575 : case PCI_EXP_TYPE_PCIE_BRIDGE:
3576 : /*
3577 : * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3578 : * applicable... must never implement an ACS Extended Capability...".
3579 : * This seems arbitrary, but we take a conservative interpretation
3580 : * of this statement.
3581 : */
3582 : case PCI_EXP_TYPE_PCI_BRIDGE:
3583 : case PCI_EXP_TYPE_RC_EC:
3584 : return false;
3585 : /*
3586 : * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3587 : * implement ACS in order to indicate their peer-to-peer capabilities,
3588 : * regardless of whether they are single- or multi-function devices.
3589 : */
3590 : case PCI_EXP_TYPE_DOWNSTREAM:
3591 : case PCI_EXP_TYPE_ROOT_PORT:
3592 0 : return pci_acs_flags_enabled(pdev, acs_flags);
3593 : /*
3594 : * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3595 : * implemented by the remaining PCIe types to indicate peer-to-peer
3596 : * capabilities, but only when they are part of a multifunction
3597 : * device. The footnote for section 6.12 indicates the specific
3598 : * PCIe types included here.
3599 : */
3600 : case PCI_EXP_TYPE_ENDPOINT:
3601 : case PCI_EXP_TYPE_UPSTREAM:
3602 : case PCI_EXP_TYPE_LEG_END:
3603 : case PCI_EXP_TYPE_RC_END:
3604 0 : if (!pdev->multifunction)
3605 : break;
3606 :
3607 0 : return pci_acs_flags_enabled(pdev, acs_flags);
3608 : }
3609 :
3610 : /*
3611 : * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3612 : * to single function devices with the exception of downstream ports.
3613 : */
3614 0 : return true;
3615 : }
3616 :
3617 : /**
3618 : * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3619 : * @start: starting downstream device
3620 : * @end: ending upstream device or NULL to search to the root bus
3621 : * @acs_flags: required flags
3622 : *
3623 : * Walk up a device tree from start to end testing PCI ACS support. If
3624 : * any step along the way does not support the required flags, return false.
3625 : */
3626 0 : bool pci_acs_path_enabled(struct pci_dev *start,
3627 : struct pci_dev *end, u16 acs_flags)
3628 : {
3629 0 : struct pci_dev *pdev, *parent = start;
3630 :
3631 : do {
3632 0 : pdev = parent;
3633 :
3634 0 : if (!pci_acs_enabled(pdev, acs_flags))
3635 : return false;
3636 :
3637 0 : if (pci_is_root_bus(pdev->bus))
3638 0 : return (end == NULL);
3639 :
3640 0 : parent = pdev->bus->self;
3641 0 : } while (pdev != end);
3642 :
3643 : return true;
3644 : }
3645 :
3646 : /**
3647 : * pci_acs_init - Initialize ACS if hardware supports it
3648 : * @dev: the PCI device
3649 : */
3650 0 : void pci_acs_init(struct pci_dev *dev)
3651 : {
3652 0 : dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3653 :
3654 : /*
3655 : * Attempt to enable ACS regardless of capability because some Root
3656 : * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3657 : * the standard ACS capability but still support ACS via those
3658 : * quirks.
3659 : */
3660 0 : pci_enable_acs(dev);
3661 0 : }
3662 :
3663 : /**
3664 : * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3665 : * @pdev: PCI device
3666 : * @bar: BAR to find
3667 : *
3668 : * Helper to find the position of the ctrl register for a BAR.
3669 : * Returns -ENOTSUPP if resizable BARs are not supported at all.
3670 : * Returns -ENOENT if no ctrl register for the BAR could be found.
3671 : */
3672 0 : static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3673 : {
3674 : unsigned int pos, nbars, i;
3675 : u32 ctrl;
3676 :
3677 0 : pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3678 0 : if (!pos)
3679 : return -ENOTSUPP;
3680 :
3681 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3682 0 : nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3683 : PCI_REBAR_CTRL_NBAR_SHIFT;
3684 :
3685 0 : for (i = 0; i < nbars; i++, pos += 8) {
3686 : int bar_idx;
3687 :
3688 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3689 0 : bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3690 0 : if (bar_idx == bar)
3691 0 : return pos;
3692 : }
3693 :
3694 : return -ENOENT;
3695 : }
3696 :
3697 : /**
3698 : * pci_rebar_get_possible_sizes - get possible sizes for BAR
3699 : * @pdev: PCI device
3700 : * @bar: BAR to query
3701 : *
3702 : * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3703 : * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3704 : */
3705 0 : u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3706 : {
3707 : int pos;
3708 : u32 cap;
3709 :
3710 0 : pos = pci_rebar_find_pos(pdev, bar);
3711 0 : if (pos < 0)
3712 : return 0;
3713 :
3714 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3715 0 : cap &= PCI_REBAR_CAP_SIZES;
3716 :
3717 : /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3718 0 : if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3719 0 : bar == 0 && cap == 0x7000)
3720 0 : cap = 0x3f000;
3721 :
3722 0 : return cap >> 4;
3723 : }
3724 : EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3725 :
3726 : /**
3727 : * pci_rebar_get_current_size - get the current size of a BAR
3728 : * @pdev: PCI device
3729 : * @bar: BAR to set size to
3730 : *
3731 : * Read the size of a BAR from the resizable BAR config.
3732 : * Returns size if found or negative error code.
3733 : */
3734 0 : int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3735 : {
3736 : int pos;
3737 : u32 ctrl;
3738 :
3739 0 : pos = pci_rebar_find_pos(pdev, bar);
3740 0 : if (pos < 0)
3741 : return pos;
3742 :
3743 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3744 0 : return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3745 : }
3746 :
3747 : /**
3748 : * pci_rebar_set_size - set a new size for a BAR
3749 : * @pdev: PCI device
3750 : * @bar: BAR to set size to
3751 : * @size: new size as defined in the spec (0=1MB, 19=512GB)
3752 : *
3753 : * Set the new size of a BAR as defined in the spec.
3754 : * Returns zero if resizing was successful, error code otherwise.
3755 : */
3756 0 : int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3757 : {
3758 : int pos;
3759 : u32 ctrl;
3760 :
3761 0 : pos = pci_rebar_find_pos(pdev, bar);
3762 0 : if (pos < 0)
3763 : return pos;
3764 :
3765 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3766 0 : ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3767 0 : ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3768 0 : pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3769 0 : return 0;
3770 : }
3771 :
3772 : /**
3773 : * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3774 : * @dev: the PCI device
3775 : * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3776 : * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3777 : * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3778 : * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3779 : *
3780 : * Return 0 if all upstream bridges support AtomicOp routing, egress
3781 : * blocking is disabled on all upstream ports, and the root port supports
3782 : * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3783 : * AtomicOp completion), or negative otherwise.
3784 : */
3785 0 : int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3786 : {
3787 0 : struct pci_bus *bus = dev->bus;
3788 : struct pci_dev *bridge;
3789 : u32 cap, ctl2;
3790 :
3791 : /*
3792 : * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3793 : * in Device Control 2 is reserved in VFs and the PF value applies
3794 : * to all associated VFs.
3795 : */
3796 0 : if (dev->is_virtfn)
3797 : return -EINVAL;
3798 :
3799 0 : if (!pci_is_pcie(dev))
3800 : return -EINVAL;
3801 :
3802 : /*
3803 : * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3804 : * AtomicOp requesters. For now, we only support endpoints as
3805 : * requesters and root ports as completers. No endpoints as
3806 : * completers, and no peer-to-peer.
3807 : */
3808 :
3809 0 : switch (pci_pcie_type(dev)) {
3810 : case PCI_EXP_TYPE_ENDPOINT:
3811 : case PCI_EXP_TYPE_LEG_END:
3812 : case PCI_EXP_TYPE_RC_END:
3813 : break;
3814 : default:
3815 : return -EINVAL;
3816 : }
3817 :
3818 0 : while (bus->parent) {
3819 0 : bridge = bus->self;
3820 :
3821 0 : pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3822 :
3823 0 : switch (pci_pcie_type(bridge)) {
3824 : /* Ensure switch ports support AtomicOp routing */
3825 : case PCI_EXP_TYPE_UPSTREAM:
3826 : case PCI_EXP_TYPE_DOWNSTREAM:
3827 0 : if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3828 : return -EINVAL;
3829 : break;
3830 :
3831 : /* Ensure root port supports all the sizes we care about */
3832 : case PCI_EXP_TYPE_ROOT_PORT:
3833 0 : if ((cap & cap_mask) != cap_mask)
3834 : return -EINVAL;
3835 : break;
3836 : }
3837 :
3838 : /* Ensure upstream ports don't block AtomicOps on egress */
3839 0 : if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3840 0 : pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3841 : &ctl2);
3842 0 : if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3843 : return -EINVAL;
3844 : }
3845 :
3846 0 : bus = bus->parent;
3847 : }
3848 :
3849 0 : pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3850 : PCI_EXP_DEVCTL2_ATOMIC_REQ);
3851 0 : return 0;
3852 : }
3853 : EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3854 :
3855 : /**
3856 : * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3857 : * @dev: the PCI device
3858 : * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3859 : *
3860 : * Perform INTx swizzling for a device behind one level of bridge. This is
3861 : * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3862 : * behind bridges on add-in cards. For devices with ARI enabled, the slot
3863 : * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3864 : * the PCI Express Base Specification, Revision 2.1)
3865 : */
3866 0 : u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3867 : {
3868 : int slot;
3869 :
3870 0 : if (pci_ari_enabled(dev->bus))
3871 : slot = 0;
3872 : else
3873 0 : slot = PCI_SLOT(dev->devfn);
3874 :
3875 0 : return (((pin - 1) + slot) % 4) + 1;
3876 : }
3877 :
3878 0 : int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3879 : {
3880 : u8 pin;
3881 :
3882 0 : pin = dev->pin;
3883 0 : if (!pin)
3884 : return -1;
3885 :
3886 0 : while (!pci_is_root_bus(dev->bus)) {
3887 0 : pin = pci_swizzle_interrupt_pin(dev, pin);
3888 0 : dev = dev->bus->self;
3889 : }
3890 0 : *bridge = dev;
3891 0 : return pin;
3892 : }
3893 :
3894 : /**
3895 : * pci_common_swizzle - swizzle INTx all the way to root bridge
3896 : * @dev: the PCI device
3897 : * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3898 : *
3899 : * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3900 : * bridges all the way up to a PCI root bus.
3901 : */
3902 0 : u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3903 : {
3904 0 : u8 pin = *pinp;
3905 :
3906 0 : while (!pci_is_root_bus(dev->bus)) {
3907 0 : pin = pci_swizzle_interrupt_pin(dev, pin);
3908 0 : dev = dev->bus->self;
3909 : }
3910 0 : *pinp = pin;
3911 0 : return PCI_SLOT(dev->devfn);
3912 : }
3913 : EXPORT_SYMBOL_GPL(pci_common_swizzle);
3914 :
3915 : /**
3916 : * pci_release_region - Release a PCI bar
3917 : * @pdev: PCI device whose resources were previously reserved by
3918 : * pci_request_region()
3919 : * @bar: BAR to release
3920 : *
3921 : * Releases the PCI I/O and memory resources previously reserved by a
3922 : * successful call to pci_request_region(). Call this function only
3923 : * after all use of the PCI regions has ceased.
3924 : */
3925 0 : void pci_release_region(struct pci_dev *pdev, int bar)
3926 : {
3927 : struct pci_devres *dr;
3928 :
3929 0 : if (pci_resource_len(pdev, bar) == 0)
3930 : return;
3931 0 : if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3932 0 : release_region(pci_resource_start(pdev, bar),
3933 : pci_resource_len(pdev, bar));
3934 0 : else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3935 0 : release_mem_region(pci_resource_start(pdev, bar),
3936 : pci_resource_len(pdev, bar));
3937 :
3938 0 : dr = find_pci_dr(pdev);
3939 0 : if (dr)
3940 0 : dr->region_mask &= ~(1 << bar);
3941 : }
3942 : EXPORT_SYMBOL(pci_release_region);
3943 :
3944 : /**
3945 : * __pci_request_region - Reserved PCI I/O and memory resource
3946 : * @pdev: PCI device whose resources are to be reserved
3947 : * @bar: BAR to be reserved
3948 : * @res_name: Name to be associated with resource.
3949 : * @exclusive: whether the region access is exclusive or not
3950 : *
3951 : * Mark the PCI region associated with PCI device @pdev BAR @bar as
3952 : * being reserved by owner @res_name. Do not access any
3953 : * address inside the PCI regions unless this call returns
3954 : * successfully.
3955 : *
3956 : * If @exclusive is set, then the region is marked so that userspace
3957 : * is explicitly not allowed to map the resource via /dev/mem or
3958 : * sysfs MMIO access.
3959 : *
3960 : * Returns 0 on success, or %EBUSY on error. A warning
3961 : * message is also printed on failure.
3962 : */
3963 0 : static int __pci_request_region(struct pci_dev *pdev, int bar,
3964 : const char *res_name, int exclusive)
3965 : {
3966 : struct pci_devres *dr;
3967 :
3968 0 : if (pci_resource_len(pdev, bar) == 0)
3969 : return 0;
3970 :
3971 0 : if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3972 0 : if (!request_region(pci_resource_start(pdev, bar),
3973 : pci_resource_len(pdev, bar), res_name))
3974 : goto err_out;
3975 0 : } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3976 0 : if (!__request_mem_region(pci_resource_start(pdev, bar),
3977 : pci_resource_len(pdev, bar), res_name,
3978 : exclusive))
3979 : goto err_out;
3980 : }
3981 :
3982 0 : dr = find_pci_dr(pdev);
3983 0 : if (dr)
3984 0 : dr->region_mask |= 1 << bar;
3985 :
3986 : return 0;
3987 :
3988 : err_out:
3989 0 : pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3990 : &pdev->resource[bar]);
3991 0 : return -EBUSY;
3992 : }
3993 :
3994 : /**
3995 : * pci_request_region - Reserve PCI I/O and memory resource
3996 : * @pdev: PCI device whose resources are to be reserved
3997 : * @bar: BAR to be reserved
3998 : * @res_name: Name to be associated with resource
3999 : *
4000 : * Mark the PCI region associated with PCI device @pdev BAR @bar as
4001 : * being reserved by owner @res_name. Do not access any
4002 : * address inside the PCI regions unless this call returns
4003 : * successfully.
4004 : *
4005 : * Returns 0 on success, or %EBUSY on error. A warning
4006 : * message is also printed on failure.
4007 : */
4008 0 : int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
4009 : {
4010 0 : return __pci_request_region(pdev, bar, res_name, 0);
4011 : }
4012 : EXPORT_SYMBOL(pci_request_region);
4013 :
4014 : /**
4015 : * pci_release_selected_regions - Release selected PCI I/O and memory resources
4016 : * @pdev: PCI device whose resources were previously reserved
4017 : * @bars: Bitmask of BARs to be released
4018 : *
4019 : * Release selected PCI I/O and memory resources previously reserved.
4020 : * Call this function only after all use of the PCI regions has ceased.
4021 : */
4022 0 : void pci_release_selected_regions(struct pci_dev *pdev, int bars)
4023 : {
4024 : int i;
4025 :
4026 0 : for (i = 0; i < PCI_STD_NUM_BARS; i++)
4027 0 : if (bars & (1 << i))
4028 0 : pci_release_region(pdev, i);
4029 0 : }
4030 : EXPORT_SYMBOL(pci_release_selected_regions);
4031 :
4032 0 : static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
4033 : const char *res_name, int excl)
4034 : {
4035 : int i;
4036 :
4037 0 : for (i = 0; i < PCI_STD_NUM_BARS; i++)
4038 0 : if (bars & (1 << i))
4039 0 : if (__pci_request_region(pdev, i, res_name, excl))
4040 : goto err_out;
4041 : return 0;
4042 :
4043 : err_out:
4044 0 : while (--i >= 0)
4045 0 : if (bars & (1 << i))
4046 0 : pci_release_region(pdev, i);
4047 :
4048 : return -EBUSY;
4049 : }
4050 :
4051 :
4052 : /**
4053 : * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4054 : * @pdev: PCI device whose resources are to be reserved
4055 : * @bars: Bitmask of BARs to be requested
4056 : * @res_name: Name to be associated with resource
4057 : */
4058 0 : int pci_request_selected_regions(struct pci_dev *pdev, int bars,
4059 : const char *res_name)
4060 : {
4061 0 : return __pci_request_selected_regions(pdev, bars, res_name, 0);
4062 : }
4063 : EXPORT_SYMBOL(pci_request_selected_regions);
4064 :
4065 0 : int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
4066 : const char *res_name)
4067 : {
4068 0 : return __pci_request_selected_regions(pdev, bars, res_name,
4069 : IORESOURCE_EXCLUSIVE);
4070 : }
4071 : EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4072 :
4073 : /**
4074 : * pci_release_regions - Release reserved PCI I/O and memory resources
4075 : * @pdev: PCI device whose resources were previously reserved by
4076 : * pci_request_regions()
4077 : *
4078 : * Releases all PCI I/O and memory resources previously reserved by a
4079 : * successful call to pci_request_regions(). Call this function only
4080 : * after all use of the PCI regions has ceased.
4081 : */
4082 :
4083 0 : void pci_release_regions(struct pci_dev *pdev)
4084 : {
4085 0 : pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
4086 0 : }
4087 : EXPORT_SYMBOL(pci_release_regions);
4088 :
4089 : /**
4090 : * pci_request_regions - Reserve PCI I/O and memory resources
4091 : * @pdev: PCI device whose resources are to be reserved
4092 : * @res_name: Name to be associated with resource.
4093 : *
4094 : * Mark all PCI regions associated with PCI device @pdev as
4095 : * being reserved by owner @res_name. Do not access any
4096 : * address inside the PCI regions unless this call returns
4097 : * successfully.
4098 : *
4099 : * Returns 0 on success, or %EBUSY on error. A warning
4100 : * message is also printed on failure.
4101 : */
4102 0 : int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4103 : {
4104 0 : return pci_request_selected_regions(pdev,
4105 : ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4106 : }
4107 : EXPORT_SYMBOL(pci_request_regions);
4108 :
4109 : /**
4110 : * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4111 : * @pdev: PCI device whose resources are to be reserved
4112 : * @res_name: Name to be associated with resource.
4113 : *
4114 : * Mark all PCI regions associated with PCI device @pdev as being reserved
4115 : * by owner @res_name. Do not access any address inside the PCI regions
4116 : * unless this call returns successfully.
4117 : *
4118 : * pci_request_regions_exclusive() will mark the region so that /dev/mem
4119 : * and the sysfs MMIO access will not be allowed.
4120 : *
4121 : * Returns 0 on success, or %EBUSY on error. A warning message is also
4122 : * printed on failure.
4123 : */
4124 0 : int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4125 : {
4126 0 : return pci_request_selected_regions_exclusive(pdev,
4127 : ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4128 : }
4129 : EXPORT_SYMBOL(pci_request_regions_exclusive);
4130 :
4131 : /*
4132 : * Record the PCI IO range (expressed as CPU physical address + size).
4133 : * Return a negative value if an error has occurred, zero otherwise
4134 : */
4135 0 : int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4136 : resource_size_t size)
4137 : {
4138 0 : int ret = 0;
4139 : #ifdef PCI_IOBASE
4140 : struct logic_pio_hwaddr *range;
4141 :
4142 0 : if (!size || addr + size < addr)
4143 : return -EINVAL;
4144 :
4145 0 : range = kzalloc(sizeof(*range), GFP_ATOMIC);
4146 0 : if (!range)
4147 : return -ENOMEM;
4148 :
4149 0 : range->fwnode = fwnode;
4150 0 : range->size = size;
4151 0 : range->hw_start = addr;
4152 0 : range->flags = LOGIC_PIO_CPU_MMIO;
4153 :
4154 0 : ret = logic_pio_register_range(range);
4155 0 : if (ret)
4156 0 : kfree(range);
4157 :
4158 : /* Ignore duplicates due to deferred probing */
4159 0 : if (ret == -EEXIST)
4160 0 : ret = 0;
4161 : #endif
4162 :
4163 : return ret;
4164 : }
4165 :
4166 0 : phys_addr_t pci_pio_to_address(unsigned long pio)
4167 : {
4168 0 : phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
4169 :
4170 : #ifdef PCI_IOBASE
4171 0 : if (pio >= MMIO_UPPER_LIMIT)
4172 : return address;
4173 :
4174 0 : address = logic_pio_to_hwaddr(pio);
4175 : #endif
4176 :
4177 0 : return address;
4178 : }
4179 : EXPORT_SYMBOL_GPL(pci_pio_to_address);
4180 :
4181 0 : unsigned long __weak pci_address_to_pio(phys_addr_t address)
4182 : {
4183 : #ifdef PCI_IOBASE
4184 0 : return logic_pio_trans_cpuaddr(address);
4185 : #else
4186 : if (address > IO_SPACE_LIMIT)
4187 : return (unsigned long)-1;
4188 :
4189 : return (unsigned long) address;
4190 : #endif
4191 : }
4192 :
4193 : /**
4194 : * pci_remap_iospace - Remap the memory mapped I/O space
4195 : * @res: Resource describing the I/O space
4196 : * @phys_addr: physical address of range to be mapped
4197 : *
4198 : * Remap the memory mapped I/O space described by the @res and the CPU
4199 : * physical address @phys_addr into virtual address space. Only
4200 : * architectures that have memory mapped IO functions defined (and the
4201 : * PCI_IOBASE value defined) should call this function.
4202 : */
4203 : #ifndef pci_remap_iospace
4204 0 : int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4205 : {
4206 : #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4207 0 : unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4208 :
4209 0 : if (!(res->flags & IORESOURCE_IO))
4210 : return -EINVAL;
4211 :
4212 0 : if (res->end > IO_SPACE_LIMIT)
4213 : return -EINVAL;
4214 :
4215 0 : return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4216 0 : pgprot_device(PAGE_KERNEL));
4217 : #else
4218 : /*
4219 : * This architecture does not have memory mapped I/O space,
4220 : * so this function should never be called
4221 : */
4222 : WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4223 : return -ENODEV;
4224 : #endif
4225 : }
4226 : EXPORT_SYMBOL(pci_remap_iospace);
4227 : #endif
4228 :
4229 : /**
4230 : * pci_unmap_iospace - Unmap the memory mapped I/O space
4231 : * @res: resource to be unmapped
4232 : *
4233 : * Unmap the CPU virtual address @res from virtual address space. Only
4234 : * architectures that have memory mapped IO functions defined (and the
4235 : * PCI_IOBASE value defined) should call this function.
4236 : */
4237 0 : void pci_unmap_iospace(struct resource *res)
4238 : {
4239 : #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4240 0 : unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4241 :
4242 0 : vunmap_range(vaddr, vaddr + resource_size(res));
4243 : #endif
4244 0 : }
4245 : EXPORT_SYMBOL(pci_unmap_iospace);
4246 :
4247 0 : static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4248 : {
4249 0 : struct resource **res = ptr;
4250 :
4251 0 : pci_unmap_iospace(*res);
4252 0 : }
4253 :
4254 : /**
4255 : * devm_pci_remap_iospace - Managed pci_remap_iospace()
4256 : * @dev: Generic device to remap IO address for
4257 : * @res: Resource describing the I/O space
4258 : * @phys_addr: physical address of range to be mapped
4259 : *
4260 : * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4261 : * detach.
4262 : */
4263 0 : int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4264 : phys_addr_t phys_addr)
4265 : {
4266 : const struct resource **ptr;
4267 : int error;
4268 :
4269 0 : ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4270 0 : if (!ptr)
4271 : return -ENOMEM;
4272 :
4273 0 : error = pci_remap_iospace(res, phys_addr);
4274 0 : if (error) {
4275 0 : devres_free(ptr);
4276 : } else {
4277 0 : *ptr = res;
4278 0 : devres_add(dev, ptr);
4279 : }
4280 :
4281 : return error;
4282 : }
4283 : EXPORT_SYMBOL(devm_pci_remap_iospace);
4284 :
4285 : /**
4286 : * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4287 : * @dev: Generic device to remap IO address for
4288 : * @offset: Resource address to map
4289 : * @size: Size of map
4290 : *
4291 : * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4292 : * detach.
4293 : */
4294 0 : void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4295 : resource_size_t offset,
4296 : resource_size_t size)
4297 : {
4298 : void __iomem **ptr, *addr;
4299 :
4300 0 : ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4301 0 : if (!ptr)
4302 : return NULL;
4303 :
4304 0 : addr = pci_remap_cfgspace(offset, size);
4305 0 : if (addr) {
4306 0 : *ptr = addr;
4307 0 : devres_add(dev, ptr);
4308 : } else
4309 0 : devres_free(ptr);
4310 :
4311 : return addr;
4312 : }
4313 : EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4314 :
4315 : /**
4316 : * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4317 : * @dev: generic device to handle the resource for
4318 : * @res: configuration space resource to be handled
4319 : *
4320 : * Checks that a resource is a valid memory region, requests the memory
4321 : * region and ioremaps with pci_remap_cfgspace() API that ensures the
4322 : * proper PCI configuration space memory attributes are guaranteed.
4323 : *
4324 : * All operations are managed and will be undone on driver detach.
4325 : *
4326 : * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4327 : * on failure. Usage example::
4328 : *
4329 : * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4330 : * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4331 : * if (IS_ERR(base))
4332 : * return PTR_ERR(base);
4333 : */
4334 0 : void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4335 : struct resource *res)
4336 : {
4337 : resource_size_t size;
4338 : const char *name;
4339 : void __iomem *dest_ptr;
4340 :
4341 0 : BUG_ON(!dev);
4342 :
4343 0 : if (!res || resource_type(res) != IORESOURCE_MEM) {
4344 0 : dev_err(dev, "invalid resource\n");
4345 0 : return IOMEM_ERR_PTR(-EINVAL);
4346 : }
4347 :
4348 0 : size = resource_size(res);
4349 :
4350 0 : if (res->name)
4351 0 : name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4352 : res->name);
4353 : else
4354 0 : name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4355 0 : if (!name)
4356 : return IOMEM_ERR_PTR(-ENOMEM);
4357 :
4358 0 : if (!devm_request_mem_region(dev, res->start, size, name)) {
4359 0 : dev_err(dev, "can't request region for resource %pR\n", res);
4360 0 : return IOMEM_ERR_PTR(-EBUSY);
4361 : }
4362 :
4363 0 : dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4364 0 : if (!dest_ptr) {
4365 0 : dev_err(dev, "ioremap failed for resource %pR\n", res);
4366 0 : devm_release_mem_region(dev, res->start, size);
4367 0 : dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4368 : }
4369 :
4370 : return dest_ptr;
4371 : }
4372 : EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4373 :
4374 0 : static void __pci_set_master(struct pci_dev *dev, bool enable)
4375 : {
4376 : u16 old_cmd, cmd;
4377 :
4378 0 : pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4379 0 : if (enable)
4380 0 : cmd = old_cmd | PCI_COMMAND_MASTER;
4381 : else
4382 0 : cmd = old_cmd & ~PCI_COMMAND_MASTER;
4383 0 : if (cmd != old_cmd) {
4384 : pci_dbg(dev, "%s bus mastering\n",
4385 : enable ? "enabling" : "disabling");
4386 0 : pci_write_config_word(dev, PCI_COMMAND, cmd);
4387 : }
4388 0 : dev->is_busmaster = enable;
4389 0 : }
4390 :
4391 : /**
4392 : * pcibios_setup - process "pci=" kernel boot arguments
4393 : * @str: string used to pass in "pci=" kernel boot arguments
4394 : *
4395 : * Process kernel boot arguments. This is the default implementation.
4396 : * Architecture specific implementations can override this as necessary.
4397 : */
4398 0 : char * __weak __init pcibios_setup(char *str)
4399 : {
4400 0 : return str;
4401 : }
4402 :
4403 : /**
4404 : * pcibios_set_master - enable PCI bus-mastering for device dev
4405 : * @dev: the PCI device to enable
4406 : *
4407 : * Enables PCI bus-mastering for the device. This is the default
4408 : * implementation. Architecture specific implementations can override
4409 : * this if necessary.
4410 : */
4411 0 : void __weak pcibios_set_master(struct pci_dev *dev)
4412 : {
4413 : u8 lat;
4414 :
4415 : /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4416 0 : if (pci_is_pcie(dev))
4417 0 : return;
4418 :
4419 0 : pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4420 0 : if (lat < 16)
4421 0 : lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4422 0 : else if (lat > pcibios_max_latency)
4423 0 : lat = pcibios_max_latency;
4424 : else
4425 : return;
4426 :
4427 0 : pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4428 : }
4429 :
4430 : /**
4431 : * pci_set_master - enables bus-mastering for device dev
4432 : * @dev: the PCI device to enable
4433 : *
4434 : * Enables bus-mastering on the device and calls pcibios_set_master()
4435 : * to do the needed arch specific settings.
4436 : */
4437 0 : void pci_set_master(struct pci_dev *dev)
4438 : {
4439 0 : __pci_set_master(dev, true);
4440 0 : pcibios_set_master(dev);
4441 0 : }
4442 : EXPORT_SYMBOL(pci_set_master);
4443 :
4444 : /**
4445 : * pci_clear_master - disables bus-mastering for device dev
4446 : * @dev: the PCI device to disable
4447 : */
4448 0 : void pci_clear_master(struct pci_dev *dev)
4449 : {
4450 0 : __pci_set_master(dev, false);
4451 0 : }
4452 : EXPORT_SYMBOL(pci_clear_master);
4453 :
4454 : /**
4455 : * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4456 : * @dev: the PCI device for which MWI is to be enabled
4457 : *
4458 : * Helper function for pci_set_mwi.
4459 : * Originally copied from drivers/net/acenic.c.
4460 : * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4461 : *
4462 : * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4463 : */
4464 0 : int pci_set_cacheline_size(struct pci_dev *dev)
4465 : {
4466 : u8 cacheline_size;
4467 :
4468 0 : if (!pci_cache_line_size)
4469 : return -EINVAL;
4470 :
4471 : /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4472 : equal to or multiple of the right value. */
4473 0 : pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4474 0 : if (cacheline_size >= pci_cache_line_size &&
4475 0 : (cacheline_size % pci_cache_line_size) == 0)
4476 : return 0;
4477 :
4478 : /* Write the correct value. */
4479 0 : pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4480 : /* Read it back. */
4481 0 : pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4482 0 : if (cacheline_size == pci_cache_line_size)
4483 : return 0;
4484 :
4485 : pci_dbg(dev, "cache line size of %d is not supported\n",
4486 : pci_cache_line_size << 2);
4487 :
4488 0 : return -EINVAL;
4489 : }
4490 : EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4491 :
4492 : /**
4493 : * pci_set_mwi - enables memory-write-invalidate PCI transaction
4494 : * @dev: the PCI device for which MWI is enabled
4495 : *
4496 : * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4497 : *
4498 : * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4499 : */
4500 0 : int pci_set_mwi(struct pci_dev *dev)
4501 : {
4502 : #ifdef PCI_DISABLE_MWI
4503 : return 0;
4504 : #else
4505 : int rc;
4506 : u16 cmd;
4507 :
4508 0 : rc = pci_set_cacheline_size(dev);
4509 0 : if (rc)
4510 : return rc;
4511 :
4512 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
4513 0 : if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4514 : pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4515 0 : cmd |= PCI_COMMAND_INVALIDATE;
4516 0 : pci_write_config_word(dev, PCI_COMMAND, cmd);
4517 : }
4518 : return 0;
4519 : #endif
4520 : }
4521 : EXPORT_SYMBOL(pci_set_mwi);
4522 :
4523 : /**
4524 : * pcim_set_mwi - a device-managed pci_set_mwi()
4525 : * @dev: the PCI device for which MWI is enabled
4526 : *
4527 : * Managed pci_set_mwi().
4528 : *
4529 : * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4530 : */
4531 0 : int pcim_set_mwi(struct pci_dev *dev)
4532 : {
4533 : struct pci_devres *dr;
4534 :
4535 0 : dr = find_pci_dr(dev);
4536 0 : if (!dr)
4537 : return -ENOMEM;
4538 :
4539 0 : dr->mwi = 1;
4540 0 : return pci_set_mwi(dev);
4541 : }
4542 : EXPORT_SYMBOL(pcim_set_mwi);
4543 :
4544 : /**
4545 : * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4546 : * @dev: the PCI device for which MWI is enabled
4547 : *
4548 : * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4549 : * Callers are not required to check the return value.
4550 : *
4551 : * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4552 : */
4553 0 : int pci_try_set_mwi(struct pci_dev *dev)
4554 : {
4555 : #ifdef PCI_DISABLE_MWI
4556 : return 0;
4557 : #else
4558 0 : return pci_set_mwi(dev);
4559 : #endif
4560 : }
4561 : EXPORT_SYMBOL(pci_try_set_mwi);
4562 :
4563 : /**
4564 : * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4565 : * @dev: the PCI device to disable
4566 : *
4567 : * Disables PCI Memory-Write-Invalidate transaction on the device
4568 : */
4569 0 : void pci_clear_mwi(struct pci_dev *dev)
4570 : {
4571 : #ifndef PCI_DISABLE_MWI
4572 : u16 cmd;
4573 :
4574 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
4575 0 : if (cmd & PCI_COMMAND_INVALIDATE) {
4576 0 : cmd &= ~PCI_COMMAND_INVALIDATE;
4577 0 : pci_write_config_word(dev, PCI_COMMAND, cmd);
4578 : }
4579 : #endif
4580 0 : }
4581 : EXPORT_SYMBOL(pci_clear_mwi);
4582 :
4583 : /**
4584 : * pci_disable_parity - disable parity checking for device
4585 : * @dev: the PCI device to operate on
4586 : *
4587 : * Disable parity checking for device @dev
4588 : */
4589 0 : void pci_disable_parity(struct pci_dev *dev)
4590 : {
4591 : u16 cmd;
4592 :
4593 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
4594 0 : if (cmd & PCI_COMMAND_PARITY) {
4595 0 : cmd &= ~PCI_COMMAND_PARITY;
4596 0 : pci_write_config_word(dev, PCI_COMMAND, cmd);
4597 : }
4598 0 : }
4599 :
4600 : /**
4601 : * pci_intx - enables/disables PCI INTx for device dev
4602 : * @pdev: the PCI device to operate on
4603 : * @enable: boolean: whether to enable or disable PCI INTx
4604 : *
4605 : * Enables/disables PCI INTx for device @pdev
4606 : */
4607 0 : void pci_intx(struct pci_dev *pdev, int enable)
4608 : {
4609 : u16 pci_command, new;
4610 :
4611 0 : pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4612 :
4613 0 : if (enable)
4614 0 : new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4615 : else
4616 0 : new = pci_command | PCI_COMMAND_INTX_DISABLE;
4617 :
4618 0 : if (new != pci_command) {
4619 : struct pci_devres *dr;
4620 :
4621 0 : pci_write_config_word(pdev, PCI_COMMAND, new);
4622 :
4623 0 : dr = find_pci_dr(pdev);
4624 0 : if (dr && !dr->restore_intx) {
4625 0 : dr->restore_intx = 1;
4626 0 : dr->orig_intx = !enable;
4627 : }
4628 : }
4629 0 : }
4630 : EXPORT_SYMBOL_GPL(pci_intx);
4631 :
4632 0 : static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4633 : {
4634 0 : struct pci_bus *bus = dev->bus;
4635 0 : bool mask_updated = true;
4636 : u32 cmd_status_dword;
4637 : u16 origcmd, newcmd;
4638 : unsigned long flags;
4639 : bool irq_pending;
4640 :
4641 : /*
4642 : * We do a single dword read to retrieve both command and status.
4643 : * Document assumptions that make this possible.
4644 : */
4645 : BUILD_BUG_ON(PCI_COMMAND % 4);
4646 : BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4647 :
4648 0 : raw_spin_lock_irqsave(&pci_lock, flags);
4649 :
4650 0 : bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4651 :
4652 0 : irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4653 :
4654 : /*
4655 : * Check interrupt status register to see whether our device
4656 : * triggered the interrupt (when masking) or the next IRQ is
4657 : * already pending (when unmasking).
4658 : */
4659 0 : if (mask != irq_pending) {
4660 : mask_updated = false;
4661 : goto done;
4662 : }
4663 :
4664 0 : origcmd = cmd_status_dword;
4665 0 : newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4666 0 : if (mask)
4667 0 : newcmd |= PCI_COMMAND_INTX_DISABLE;
4668 0 : if (newcmd != origcmd)
4669 0 : bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4670 :
4671 : done:
4672 0 : raw_spin_unlock_irqrestore(&pci_lock, flags);
4673 :
4674 0 : return mask_updated;
4675 : }
4676 :
4677 : /**
4678 : * pci_check_and_mask_intx - mask INTx on pending interrupt
4679 : * @dev: the PCI device to operate on
4680 : *
4681 : * Check if the device dev has its INTx line asserted, mask it and return
4682 : * true in that case. False is returned if no interrupt was pending.
4683 : */
4684 0 : bool pci_check_and_mask_intx(struct pci_dev *dev)
4685 : {
4686 0 : return pci_check_and_set_intx_mask(dev, true);
4687 : }
4688 : EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4689 :
4690 : /**
4691 : * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4692 : * @dev: the PCI device to operate on
4693 : *
4694 : * Check if the device dev has its INTx line asserted, unmask it if not and
4695 : * return true. False is returned and the mask remains active if there was
4696 : * still an interrupt pending.
4697 : */
4698 0 : bool pci_check_and_unmask_intx(struct pci_dev *dev)
4699 : {
4700 0 : return pci_check_and_set_intx_mask(dev, false);
4701 : }
4702 : EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4703 :
4704 : /**
4705 : * pci_wait_for_pending_transaction - wait for pending transaction
4706 : * @dev: the PCI device to operate on
4707 : *
4708 : * Return 0 if transaction is pending 1 otherwise.
4709 : */
4710 0 : int pci_wait_for_pending_transaction(struct pci_dev *dev)
4711 : {
4712 0 : if (!pci_is_pcie(dev))
4713 : return 1;
4714 :
4715 0 : return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4716 : PCI_EXP_DEVSTA_TRPND);
4717 : }
4718 : EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4719 :
4720 : /**
4721 : * pcie_flr - initiate a PCIe function level reset
4722 : * @dev: device to reset
4723 : *
4724 : * Initiate a function level reset unconditionally on @dev without
4725 : * checking any flags and DEVCAP
4726 : */
4727 0 : int pcie_flr(struct pci_dev *dev)
4728 : {
4729 0 : if (!pci_wait_for_pending_transaction(dev))
4730 0 : pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4731 :
4732 0 : pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4733 :
4734 0 : if (dev->imm_ready)
4735 : return 0;
4736 :
4737 : /*
4738 : * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4739 : * 100ms, but may silently discard requests while the FLR is in
4740 : * progress. Wait 100ms before trying to access the device.
4741 : */
4742 0 : msleep(100);
4743 :
4744 0 : return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4745 : }
4746 : EXPORT_SYMBOL_GPL(pcie_flr);
4747 :
4748 : /**
4749 : * pcie_reset_flr - initiate a PCIe function level reset
4750 : * @dev: device to reset
4751 : * @probe: if true, return 0 if device can be reset this way
4752 : *
4753 : * Initiate a function level reset on @dev.
4754 : */
4755 0 : int pcie_reset_flr(struct pci_dev *dev, bool probe)
4756 : {
4757 0 : if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4758 : return -ENOTTY;
4759 :
4760 0 : if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))
4761 : return -ENOTTY;
4762 :
4763 0 : if (probe)
4764 : return 0;
4765 :
4766 0 : return pcie_flr(dev);
4767 : }
4768 : EXPORT_SYMBOL_GPL(pcie_reset_flr);
4769 :
4770 0 : static int pci_af_flr(struct pci_dev *dev, bool probe)
4771 : {
4772 : int pos;
4773 : u8 cap;
4774 :
4775 0 : pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4776 0 : if (!pos)
4777 : return -ENOTTY;
4778 :
4779 0 : if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4780 : return -ENOTTY;
4781 :
4782 0 : pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4783 0 : if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4784 : return -ENOTTY;
4785 :
4786 0 : if (probe)
4787 : return 0;
4788 :
4789 : /*
4790 : * Wait for Transaction Pending bit to clear. A word-aligned test
4791 : * is used, so we use the control offset rather than status and shift
4792 : * the test bit to match.
4793 : */
4794 0 : if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4795 : PCI_AF_STATUS_TP << 8))
4796 0 : pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4797 :
4798 0 : pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4799 :
4800 0 : if (dev->imm_ready)
4801 : return 0;
4802 :
4803 : /*
4804 : * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4805 : * updated 27 July 2006; a device must complete an FLR within
4806 : * 100ms, but may silently discard requests while the FLR is in
4807 : * progress. Wait 100ms before trying to access the device.
4808 : */
4809 0 : msleep(100);
4810 :
4811 0 : return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4812 : }
4813 :
4814 : /**
4815 : * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4816 : * @dev: Device to reset.
4817 : * @probe: if true, return 0 if the device can be reset this way.
4818 : *
4819 : * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4820 : * unset, it will be reinitialized internally when going from PCI_D3hot to
4821 : * PCI_D0. If that's the case and the device is not in a low-power state
4822 : * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4823 : *
4824 : * NOTE: This causes the caller to sleep for twice the device power transition
4825 : * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4826 : * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4827 : * Moreover, only devices in D0 can be reset by this function.
4828 : */
4829 0 : static int pci_pm_reset(struct pci_dev *dev, bool probe)
4830 : {
4831 : u16 csr;
4832 :
4833 0 : if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4834 : return -ENOTTY;
4835 :
4836 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4837 0 : if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4838 : return -ENOTTY;
4839 :
4840 0 : if (probe)
4841 : return 0;
4842 :
4843 0 : if (dev->current_state != PCI_D0)
4844 : return -EINVAL;
4845 :
4846 0 : csr &= ~PCI_PM_CTRL_STATE_MASK;
4847 0 : csr |= PCI_D3hot;
4848 0 : pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4849 0 : pci_dev_d3_sleep(dev);
4850 :
4851 0 : csr &= ~PCI_PM_CTRL_STATE_MASK;
4852 : csr |= PCI_D0;
4853 0 : pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4854 0 : pci_dev_d3_sleep(dev);
4855 :
4856 0 : return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4857 : }
4858 :
4859 : /**
4860 : * pcie_wait_for_link_delay - Wait until link is active or inactive
4861 : * @pdev: Bridge device
4862 : * @active: waiting for active or inactive?
4863 : * @delay: Delay to wait after link has become active (in ms)
4864 : *
4865 : * Use this to wait till link becomes active or inactive.
4866 : */
4867 0 : static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4868 : int delay)
4869 : {
4870 0 : int timeout = 1000;
4871 : bool ret;
4872 : u16 lnk_status;
4873 :
4874 : /*
4875 : * Some controllers might not implement link active reporting. In this
4876 : * case, we wait for 1000 ms + any delay requested by the caller.
4877 : */
4878 0 : if (!pdev->link_active_reporting) {
4879 0 : msleep(timeout + delay);
4880 0 : return true;
4881 : }
4882 :
4883 : /*
4884 : * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4885 : * after which we should expect an link active if the reset was
4886 : * successful. If so, software must wait a minimum 100ms before sending
4887 : * configuration requests to devices downstream this port.
4888 : *
4889 : * If the link fails to activate, either the device was physically
4890 : * removed or the link is permanently failed.
4891 : */
4892 0 : if (active)
4893 0 : msleep(20);
4894 : for (;;) {
4895 0 : pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4896 0 : ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4897 0 : if (ret == active)
4898 : break;
4899 0 : if (timeout <= 0)
4900 : break;
4901 0 : msleep(10);
4902 0 : timeout -= 10;
4903 : }
4904 0 : if (active && ret)
4905 0 : msleep(delay);
4906 :
4907 0 : return ret == active;
4908 : }
4909 :
4910 : /**
4911 : * pcie_wait_for_link - Wait until link is active or inactive
4912 : * @pdev: Bridge device
4913 : * @active: waiting for active or inactive?
4914 : *
4915 : * Use this to wait till link becomes active or inactive.
4916 : */
4917 0 : bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4918 : {
4919 0 : return pcie_wait_for_link_delay(pdev, active, 100);
4920 : }
4921 :
4922 : /*
4923 : * Find maximum D3cold delay required by all the devices on the bus. The
4924 : * spec says 100 ms, but firmware can lower it and we allow drivers to
4925 : * increase it as well.
4926 : *
4927 : * Called with @pci_bus_sem locked for reading.
4928 : */
4929 : static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4930 : {
4931 : const struct pci_dev *pdev;
4932 0 : int min_delay = 100;
4933 0 : int max_delay = 0;
4934 :
4935 0 : list_for_each_entry(pdev, &bus->devices, bus_list) {
4936 0 : if (pdev->d3cold_delay < min_delay)
4937 0 : min_delay = pdev->d3cold_delay;
4938 0 : if (pdev->d3cold_delay > max_delay)
4939 0 : max_delay = pdev->d3cold_delay;
4940 : }
4941 :
4942 0 : return max(min_delay, max_delay);
4943 : }
4944 :
4945 : /**
4946 : * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4947 : * @dev: PCI bridge
4948 : * @reset_type: reset type in human-readable form
4949 : *
4950 : * Handle necessary delays before access to the devices on the secondary
4951 : * side of the bridge are permitted after D3cold to D0 transition
4952 : * or Conventional Reset.
4953 : *
4954 : * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4955 : * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4956 : * 4.3.2.
4957 : *
4958 : * Return 0 on success or -ENOTTY if the first device on the secondary bus
4959 : * failed to become accessible.
4960 : */
4961 0 : int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type)
4962 : {
4963 : struct pci_dev *child;
4964 : int delay;
4965 :
4966 0 : if (pci_dev_is_disconnected(dev))
4967 : return 0;
4968 :
4969 0 : if (!pci_is_bridge(dev))
4970 : return 0;
4971 :
4972 0 : down_read(&pci_bus_sem);
4973 :
4974 : /*
4975 : * We only deal with devices that are present currently on the bus.
4976 : * For any hot-added devices the access delay is handled in pciehp
4977 : * board_added(). In case of ACPI hotplug the firmware is expected
4978 : * to configure the devices before OS is notified.
4979 : */
4980 0 : if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4981 0 : up_read(&pci_bus_sem);
4982 0 : return 0;
4983 : }
4984 :
4985 : /* Take d3cold_delay requirements into account */
4986 0 : delay = pci_bus_max_d3cold_delay(dev->subordinate);
4987 0 : if (!delay) {
4988 0 : up_read(&pci_bus_sem);
4989 0 : return 0;
4990 : }
4991 :
4992 0 : child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4993 : bus_list);
4994 0 : up_read(&pci_bus_sem);
4995 :
4996 : /*
4997 : * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4998 : * accessing the device after reset (that is 1000 ms + 100 ms).
4999 : */
5000 0 : if (!pci_is_pcie(dev)) {
5001 : pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
5002 0 : msleep(1000 + delay);
5003 0 : return 0;
5004 : }
5005 :
5006 : /*
5007 : * For PCIe downstream and root ports that do not support speeds
5008 : * greater than 5 GT/s need to wait minimum 100 ms. For higher
5009 : * speeds (gen3) we need to wait first for the data link layer to
5010 : * become active.
5011 : *
5012 : * However, 100 ms is the minimum and the PCIe spec says the
5013 : * software must allow at least 1s before it can determine that the
5014 : * device that did not respond is a broken device. There is
5015 : * evidence that 100 ms is not always enough, for example certain
5016 : * Titan Ridge xHCI controller does not always respond to
5017 : * configuration requests if we only wait for 100 ms (see
5018 : * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
5019 : *
5020 : * Therefore we wait for 100 ms and check for the device presence
5021 : * until the timeout expires.
5022 : */
5023 0 : if (!pcie_downstream_port(dev))
5024 : return 0;
5025 :
5026 0 : if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
5027 : pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
5028 0 : msleep(delay);
5029 : } else {
5030 : pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
5031 : delay);
5032 0 : if (!pcie_wait_for_link_delay(dev, true, delay)) {
5033 : /* Did not train, no need to wait any further */
5034 0 : pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
5035 0 : return -ENOTTY;
5036 : }
5037 : }
5038 :
5039 0 : return pci_dev_wait(child, reset_type,
5040 : PCIE_RESET_READY_POLL_MS - delay);
5041 : }
5042 :
5043 0 : void pci_reset_secondary_bus(struct pci_dev *dev)
5044 : {
5045 : u16 ctrl;
5046 :
5047 0 : pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
5048 0 : ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
5049 0 : pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5050 :
5051 : /*
5052 : * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
5053 : * this to 2ms to ensure that we meet the minimum requirement.
5054 : */
5055 0 : msleep(2);
5056 :
5057 0 : ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
5058 0 : pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5059 0 : }
5060 :
5061 0 : void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
5062 : {
5063 0 : pci_reset_secondary_bus(dev);
5064 0 : }
5065 :
5066 : /**
5067 : * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5068 : * @dev: Bridge device
5069 : *
5070 : * Use the bridge control register to assert reset on the secondary bus.
5071 : * Devices on the secondary bus are left in power-on state.
5072 : */
5073 0 : int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
5074 : {
5075 0 : pcibios_reset_secondary_bus(dev);
5076 :
5077 0 : return pci_bridge_wait_for_secondary_bus(dev, "bus reset");
5078 : }
5079 : EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
5080 :
5081 0 : static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)
5082 : {
5083 : struct pci_dev *pdev;
5084 :
5085 0 : if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5086 0 : !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5087 : return -ENOTTY;
5088 :
5089 0 : list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5090 0 : if (pdev != dev)
5091 : return -ENOTTY;
5092 :
5093 0 : if (probe)
5094 : return 0;
5095 :
5096 0 : return pci_bridge_secondary_bus_reset(dev->bus->self);
5097 : }
5098 :
5099 : static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe)
5100 : {
5101 0 : int rc = -ENOTTY;
5102 :
5103 0 : if (!hotplug || !try_module_get(hotplug->owner))
5104 : return rc;
5105 :
5106 0 : if (hotplug->ops->reset_slot)
5107 0 : rc = hotplug->ops->reset_slot(hotplug, probe);
5108 :
5109 : module_put(hotplug->owner);
5110 :
5111 : return rc;
5112 : }
5113 :
5114 0 : static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
5115 : {
5116 0 : if (dev->multifunction || dev->subordinate || !dev->slot ||
5117 0 : dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5118 : return -ENOTTY;
5119 :
5120 0 : return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5121 : }
5122 :
5123 0 : static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
5124 : {
5125 : int rc;
5126 :
5127 0 : rc = pci_dev_reset_slot_function(dev, probe);
5128 0 : if (rc != -ENOTTY)
5129 : return rc;
5130 0 : return pci_parent_bus_reset(dev, probe);
5131 : }
5132 :
5133 0 : void pci_dev_lock(struct pci_dev *dev)
5134 : {
5135 : /* block PM suspend, driver probe, etc. */
5136 0 : device_lock(&dev->dev);
5137 0 : pci_cfg_access_lock(dev);
5138 0 : }
5139 : EXPORT_SYMBOL_GPL(pci_dev_lock);
5140 :
5141 : /* Return 1 on successful lock, 0 on contention */
5142 0 : int pci_dev_trylock(struct pci_dev *dev)
5143 : {
5144 0 : if (device_trylock(&dev->dev)) {
5145 0 : if (pci_cfg_access_trylock(dev))
5146 : return 1;
5147 0 : device_unlock(&dev->dev);
5148 : }
5149 :
5150 : return 0;
5151 : }
5152 : EXPORT_SYMBOL_GPL(pci_dev_trylock);
5153 :
5154 0 : void pci_dev_unlock(struct pci_dev *dev)
5155 : {
5156 0 : pci_cfg_access_unlock(dev);
5157 0 : device_unlock(&dev->dev);
5158 0 : }
5159 : EXPORT_SYMBOL_GPL(pci_dev_unlock);
5160 :
5161 0 : static void pci_dev_save_and_disable(struct pci_dev *dev)
5162 : {
5163 0 : const struct pci_error_handlers *err_handler =
5164 0 : dev->driver ? dev->driver->err_handler : NULL;
5165 :
5166 : /*
5167 : * dev->driver->err_handler->reset_prepare() is protected against
5168 : * races with ->remove() by the device lock, which must be held by
5169 : * the caller.
5170 : */
5171 0 : if (err_handler && err_handler->reset_prepare)
5172 0 : err_handler->reset_prepare(dev);
5173 :
5174 : /*
5175 : * Wake-up device prior to save. PM registers default to D0 after
5176 : * reset and a simple register restore doesn't reliably return
5177 : * to a non-D0 state anyway.
5178 : */
5179 0 : pci_set_power_state(dev, PCI_D0);
5180 :
5181 0 : pci_save_state(dev);
5182 : /*
5183 : * Disable the device by clearing the Command register, except for
5184 : * INTx-disable which is set. This not only disables MMIO and I/O port
5185 : * BARs, but also prevents the device from being Bus Master, preventing
5186 : * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5187 : * compliant devices, INTx-disable prevents legacy interrupts.
5188 : */
5189 0 : pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5190 0 : }
5191 :
5192 0 : static void pci_dev_restore(struct pci_dev *dev)
5193 : {
5194 0 : const struct pci_error_handlers *err_handler =
5195 0 : dev->driver ? dev->driver->err_handler : NULL;
5196 :
5197 0 : pci_restore_state(dev);
5198 :
5199 : /*
5200 : * dev->driver->err_handler->reset_done() is protected against
5201 : * races with ->remove() by the device lock, which must be held by
5202 : * the caller.
5203 : */
5204 0 : if (err_handler && err_handler->reset_done)
5205 0 : err_handler->reset_done(dev);
5206 0 : }
5207 :
5208 : /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5209 : static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
5210 : { },
5211 : { pci_dev_specific_reset, .name = "device_specific" },
5212 : { pci_dev_acpi_reset, .name = "acpi" },
5213 : { pcie_reset_flr, .name = "flr" },
5214 : { pci_af_flr, .name = "af_flr" },
5215 : { pci_pm_reset, .name = "pm" },
5216 : { pci_reset_bus_function, .name = "bus" },
5217 : };
5218 :
5219 0 : static ssize_t reset_method_show(struct device *dev,
5220 : struct device_attribute *attr, char *buf)
5221 : {
5222 0 : struct pci_dev *pdev = to_pci_dev(dev);
5223 0 : ssize_t len = 0;
5224 : int i, m;
5225 :
5226 0 : for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5227 0 : m = pdev->reset_methods[i];
5228 0 : if (!m)
5229 : break;
5230 :
5231 0 : len += sysfs_emit_at(buf, len, "%s%s", len ? " " : "",
5232 : pci_reset_fn_methods[m].name);
5233 : }
5234 :
5235 0 : if (len)
5236 0 : len += sysfs_emit_at(buf, len, "\n");
5237 :
5238 0 : return len;
5239 : }
5240 :
5241 : static int reset_method_lookup(const char *name)
5242 : {
5243 : int m;
5244 :
5245 0 : for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5246 0 : if (sysfs_streq(name, pci_reset_fn_methods[m].name))
5247 : return m;
5248 : }
5249 :
5250 : return 0; /* not found */
5251 : }
5252 :
5253 0 : static ssize_t reset_method_store(struct device *dev,
5254 : struct device_attribute *attr,
5255 : const char *buf, size_t count)
5256 : {
5257 0 : struct pci_dev *pdev = to_pci_dev(dev);
5258 : char *options, *name;
5259 : int m, n;
5260 0 : u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 };
5261 :
5262 0 : if (sysfs_streq(buf, "")) {
5263 0 : pdev->reset_methods[0] = 0;
5264 0 : pci_warn(pdev, "All device reset methods disabled by user");
5265 0 : return count;
5266 : }
5267 :
5268 0 : if (sysfs_streq(buf, "default")) {
5269 0 : pci_init_reset_methods(pdev);
5270 0 : return count;
5271 : }
5272 :
5273 0 : options = kstrndup(buf, count, GFP_KERNEL);
5274 0 : if (!options)
5275 : return -ENOMEM;
5276 :
5277 : n = 0;
5278 0 : while ((name = strsep(&options, " ")) != NULL) {
5279 0 : if (sysfs_streq(name, ""))
5280 0 : continue;
5281 :
5282 0 : name = strim(name);
5283 :
5284 0 : m = reset_method_lookup(name);
5285 0 : if (!m) {
5286 0 : pci_err(pdev, "Invalid reset method '%s'", name);
5287 0 : goto error;
5288 : }
5289 :
5290 0 : if (pci_reset_fn_methods[m].reset_fn(pdev, PCI_RESET_PROBE)) {
5291 0 : pci_err(pdev, "Unsupported reset method '%s'", name);
5292 0 : goto error;
5293 : }
5294 :
5295 0 : if (n == PCI_NUM_RESET_METHODS - 1) {
5296 0 : pci_err(pdev, "Too many reset methods\n");
5297 0 : goto error;
5298 : }
5299 :
5300 0 : reset_methods[n++] = m;
5301 : }
5302 :
5303 0 : reset_methods[n] = 0;
5304 :
5305 : /* Warn if dev-specific supported but not highest priority */
5306 0 : if (pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) == 0 &&
5307 0 : reset_methods[0] != 1)
5308 0 : pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user");
5309 0 : memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods));
5310 0 : kfree(options);
5311 0 : return count;
5312 :
5313 : error:
5314 : /* Leave previous methods unchanged */
5315 0 : kfree(options);
5316 0 : return -EINVAL;
5317 : }
5318 : static DEVICE_ATTR_RW(reset_method);
5319 :
5320 : static struct attribute *pci_dev_reset_method_attrs[] = {
5321 : &dev_attr_reset_method.attr,
5322 : NULL,
5323 : };
5324 :
5325 0 : static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj,
5326 : struct attribute *a, int n)
5327 : {
5328 0 : struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
5329 :
5330 0 : if (!pci_reset_supported(pdev))
5331 : return 0;
5332 :
5333 0 : return a->mode;
5334 : }
5335 :
5336 : const struct attribute_group pci_dev_reset_method_attr_group = {
5337 : .attrs = pci_dev_reset_method_attrs,
5338 : .is_visible = pci_dev_reset_method_attr_is_visible,
5339 : };
5340 :
5341 : /**
5342 : * __pci_reset_function_locked - reset a PCI device function while holding
5343 : * the @dev mutex lock.
5344 : * @dev: PCI device to reset
5345 : *
5346 : * Some devices allow an individual function to be reset without affecting
5347 : * other functions in the same device. The PCI device must be responsive
5348 : * to PCI config space in order to use this function.
5349 : *
5350 : * The device function is presumed to be unused and the caller is holding
5351 : * the device mutex lock when this function is called.
5352 : *
5353 : * Resetting the device will make the contents of PCI configuration space
5354 : * random, so any caller of this must be prepared to reinitialise the
5355 : * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5356 : * etc.
5357 : *
5358 : * Returns 0 if the device function was successfully reset or negative if the
5359 : * device doesn't support resetting a single function.
5360 : */
5361 0 : int __pci_reset_function_locked(struct pci_dev *dev)
5362 : {
5363 : int i, m, rc;
5364 :
5365 : might_sleep();
5366 :
5367 : /*
5368 : * A reset method returns -ENOTTY if it doesn't support this device and
5369 : * we should try the next method.
5370 : *
5371 : * If it returns 0 (success), we're finished. If it returns any other
5372 : * error, we're also finished: this indicates that further reset
5373 : * mechanisms might be broken on the device.
5374 : */
5375 0 : for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5376 0 : m = dev->reset_methods[i];
5377 0 : if (!m)
5378 : return -ENOTTY;
5379 :
5380 0 : rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5381 0 : if (!rc)
5382 : return 0;
5383 0 : if (rc != -ENOTTY)
5384 : return rc;
5385 : }
5386 :
5387 : return -ENOTTY;
5388 : }
5389 : EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5390 :
5391 : /**
5392 : * pci_init_reset_methods - check whether device can be safely reset
5393 : * and store supported reset mechanisms.
5394 : * @dev: PCI device to check for reset mechanisms
5395 : *
5396 : * Some devices allow an individual function to be reset without affecting
5397 : * other functions in the same device. The PCI device must be in D0-D3hot
5398 : * state.
5399 : *
5400 : * Stores reset mechanisms supported by device in reset_methods byte array
5401 : * which is a member of struct pci_dev.
5402 : */
5403 0 : void pci_init_reset_methods(struct pci_dev *dev)
5404 : {
5405 : int m, i, rc;
5406 :
5407 : BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS);
5408 :
5409 : might_sleep();
5410 :
5411 0 : i = 0;
5412 0 : for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5413 0 : rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);
5414 0 : if (!rc)
5415 0 : dev->reset_methods[i++] = m;
5416 0 : else if (rc != -ENOTTY)
5417 : break;
5418 : }
5419 :
5420 0 : dev->reset_methods[i] = 0;
5421 0 : }
5422 :
5423 : /**
5424 : * pci_reset_function - quiesce and reset a PCI device function
5425 : * @dev: PCI device to reset
5426 : *
5427 : * Some devices allow an individual function to be reset without affecting
5428 : * other functions in the same device. The PCI device must be responsive
5429 : * to PCI config space in order to use this function.
5430 : *
5431 : * This function does not just reset the PCI portion of a device, but
5432 : * clears all the state associated with the device. This function differs
5433 : * from __pci_reset_function_locked() in that it saves and restores device state
5434 : * over the reset and takes the PCI device lock.
5435 : *
5436 : * Returns 0 if the device function was successfully reset or negative if the
5437 : * device doesn't support resetting a single function.
5438 : */
5439 0 : int pci_reset_function(struct pci_dev *dev)
5440 : {
5441 : int rc;
5442 :
5443 0 : if (!pci_reset_supported(dev))
5444 : return -ENOTTY;
5445 :
5446 0 : pci_dev_lock(dev);
5447 0 : pci_dev_save_and_disable(dev);
5448 :
5449 0 : rc = __pci_reset_function_locked(dev);
5450 :
5451 0 : pci_dev_restore(dev);
5452 0 : pci_dev_unlock(dev);
5453 :
5454 0 : return rc;
5455 : }
5456 : EXPORT_SYMBOL_GPL(pci_reset_function);
5457 :
5458 : /**
5459 : * pci_reset_function_locked - quiesce and reset a PCI device function
5460 : * @dev: PCI device to reset
5461 : *
5462 : * Some devices allow an individual function to be reset without affecting
5463 : * other functions in the same device. The PCI device must be responsive
5464 : * to PCI config space in order to use this function.
5465 : *
5466 : * This function does not just reset the PCI portion of a device, but
5467 : * clears all the state associated with the device. This function differs
5468 : * from __pci_reset_function_locked() in that it saves and restores device state
5469 : * over the reset. It also differs from pci_reset_function() in that it
5470 : * requires the PCI device lock to be held.
5471 : *
5472 : * Returns 0 if the device function was successfully reset or negative if the
5473 : * device doesn't support resetting a single function.
5474 : */
5475 0 : int pci_reset_function_locked(struct pci_dev *dev)
5476 : {
5477 : int rc;
5478 :
5479 0 : if (!pci_reset_supported(dev))
5480 : return -ENOTTY;
5481 :
5482 0 : pci_dev_save_and_disable(dev);
5483 :
5484 0 : rc = __pci_reset_function_locked(dev);
5485 :
5486 0 : pci_dev_restore(dev);
5487 :
5488 0 : return rc;
5489 : }
5490 : EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5491 :
5492 : /**
5493 : * pci_try_reset_function - quiesce and reset a PCI device function
5494 : * @dev: PCI device to reset
5495 : *
5496 : * Same as above, except return -EAGAIN if unable to lock device.
5497 : */
5498 0 : int pci_try_reset_function(struct pci_dev *dev)
5499 : {
5500 : int rc;
5501 :
5502 0 : if (!pci_reset_supported(dev))
5503 : return -ENOTTY;
5504 :
5505 0 : if (!pci_dev_trylock(dev))
5506 : return -EAGAIN;
5507 :
5508 0 : pci_dev_save_and_disable(dev);
5509 0 : rc = __pci_reset_function_locked(dev);
5510 0 : pci_dev_restore(dev);
5511 0 : pci_dev_unlock(dev);
5512 :
5513 0 : return rc;
5514 : }
5515 : EXPORT_SYMBOL_GPL(pci_try_reset_function);
5516 :
5517 : /* Do any devices on or below this bus prevent a bus reset? */
5518 0 : static bool pci_bus_resetable(struct pci_bus *bus)
5519 : {
5520 : struct pci_dev *dev;
5521 :
5522 :
5523 0 : if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5524 : return false;
5525 :
5526 0 : list_for_each_entry(dev, &bus->devices, bus_list) {
5527 0 : if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5528 0 : (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5529 : return false;
5530 : }
5531 :
5532 : return true;
5533 : }
5534 :
5535 : /* Lock devices from the top of the tree down */
5536 0 : static void pci_bus_lock(struct pci_bus *bus)
5537 : {
5538 : struct pci_dev *dev;
5539 :
5540 0 : list_for_each_entry(dev, &bus->devices, bus_list) {
5541 0 : pci_dev_lock(dev);
5542 0 : if (dev->subordinate)
5543 0 : pci_bus_lock(dev->subordinate);
5544 : }
5545 0 : }
5546 :
5547 : /* Unlock devices from the bottom of the tree up */
5548 0 : static void pci_bus_unlock(struct pci_bus *bus)
5549 : {
5550 : struct pci_dev *dev;
5551 :
5552 0 : list_for_each_entry(dev, &bus->devices, bus_list) {
5553 0 : if (dev->subordinate)
5554 0 : pci_bus_unlock(dev->subordinate);
5555 0 : pci_dev_unlock(dev);
5556 : }
5557 0 : }
5558 :
5559 : /* Return 1 on successful lock, 0 on contention */
5560 0 : static int pci_bus_trylock(struct pci_bus *bus)
5561 : {
5562 : struct pci_dev *dev;
5563 :
5564 0 : list_for_each_entry(dev, &bus->devices, bus_list) {
5565 0 : if (!pci_dev_trylock(dev))
5566 : goto unlock;
5567 0 : if (dev->subordinate) {
5568 0 : if (!pci_bus_trylock(dev->subordinate)) {
5569 : pci_dev_unlock(dev);
5570 : goto unlock;
5571 : }
5572 : }
5573 : }
5574 : return 1;
5575 :
5576 : unlock:
5577 0 : list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5578 0 : if (dev->subordinate)
5579 0 : pci_bus_unlock(dev->subordinate);
5580 0 : pci_dev_unlock(dev);
5581 : }
5582 : return 0;
5583 : }
5584 :
5585 : /* Do any devices on or below this slot prevent a bus reset? */
5586 0 : static bool pci_slot_resetable(struct pci_slot *slot)
5587 : {
5588 : struct pci_dev *dev;
5589 :
5590 0 : if (slot->bus->self &&
5591 0 : (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5592 : return false;
5593 :
5594 0 : list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5595 0 : if (!dev->slot || dev->slot != slot)
5596 0 : continue;
5597 0 : if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5598 0 : (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5599 : return false;
5600 : }
5601 :
5602 : return true;
5603 : }
5604 :
5605 : /* Lock devices from the top of the tree down */
5606 0 : static void pci_slot_lock(struct pci_slot *slot)
5607 : {
5608 : struct pci_dev *dev;
5609 :
5610 0 : list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5611 0 : if (!dev->slot || dev->slot != slot)
5612 0 : continue;
5613 0 : pci_dev_lock(dev);
5614 0 : if (dev->subordinate)
5615 0 : pci_bus_lock(dev->subordinate);
5616 : }
5617 0 : }
5618 :
5619 : /* Unlock devices from the bottom of the tree up */
5620 0 : static void pci_slot_unlock(struct pci_slot *slot)
5621 : {
5622 : struct pci_dev *dev;
5623 :
5624 0 : list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5625 0 : if (!dev->slot || dev->slot != slot)
5626 0 : continue;
5627 0 : if (dev->subordinate)
5628 0 : pci_bus_unlock(dev->subordinate);
5629 : pci_dev_unlock(dev);
5630 : }
5631 0 : }
5632 :
5633 : /* Return 1 on successful lock, 0 on contention */
5634 0 : static int pci_slot_trylock(struct pci_slot *slot)
5635 : {
5636 : struct pci_dev *dev;
5637 :
5638 0 : list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5639 0 : if (!dev->slot || dev->slot != slot)
5640 0 : continue;
5641 0 : if (!pci_dev_trylock(dev))
5642 : goto unlock;
5643 0 : if (dev->subordinate) {
5644 0 : if (!pci_bus_trylock(dev->subordinate)) {
5645 : pci_dev_unlock(dev);
5646 : goto unlock;
5647 : }
5648 : }
5649 : }
5650 : return 1;
5651 :
5652 : unlock:
5653 0 : list_for_each_entry_continue_reverse(dev,
5654 : &slot->bus->devices, bus_list) {
5655 0 : if (!dev->slot || dev->slot != slot)
5656 0 : continue;
5657 0 : if (dev->subordinate)
5658 0 : pci_bus_unlock(dev->subordinate);
5659 : pci_dev_unlock(dev);
5660 : }
5661 : return 0;
5662 : }
5663 :
5664 : /*
5665 : * Save and disable devices from the top of the tree down while holding
5666 : * the @dev mutex lock for the entire tree.
5667 : */
5668 0 : static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5669 : {
5670 : struct pci_dev *dev;
5671 :
5672 0 : list_for_each_entry(dev, &bus->devices, bus_list) {
5673 0 : pci_dev_save_and_disable(dev);
5674 0 : if (dev->subordinate)
5675 0 : pci_bus_save_and_disable_locked(dev->subordinate);
5676 : }
5677 0 : }
5678 :
5679 : /*
5680 : * Restore devices from top of the tree down while holding @dev mutex lock
5681 : * for the entire tree. Parent bridges need to be restored before we can
5682 : * get to subordinate devices.
5683 : */
5684 0 : static void pci_bus_restore_locked(struct pci_bus *bus)
5685 : {
5686 : struct pci_dev *dev;
5687 :
5688 0 : list_for_each_entry(dev, &bus->devices, bus_list) {
5689 0 : pci_dev_restore(dev);
5690 0 : if (dev->subordinate)
5691 0 : pci_bus_restore_locked(dev->subordinate);
5692 : }
5693 0 : }
5694 :
5695 : /*
5696 : * Save and disable devices from the top of the tree down while holding
5697 : * the @dev mutex lock for the entire tree.
5698 : */
5699 0 : static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5700 : {
5701 : struct pci_dev *dev;
5702 :
5703 0 : list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5704 0 : if (!dev->slot || dev->slot != slot)
5705 0 : continue;
5706 0 : pci_dev_save_and_disable(dev);
5707 0 : if (dev->subordinate)
5708 0 : pci_bus_save_and_disable_locked(dev->subordinate);
5709 : }
5710 0 : }
5711 :
5712 : /*
5713 : * Restore devices from top of the tree down while holding @dev mutex lock
5714 : * for the entire tree. Parent bridges need to be restored before we can
5715 : * get to subordinate devices.
5716 : */
5717 0 : static void pci_slot_restore_locked(struct pci_slot *slot)
5718 : {
5719 : struct pci_dev *dev;
5720 :
5721 0 : list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5722 0 : if (!dev->slot || dev->slot != slot)
5723 0 : continue;
5724 0 : pci_dev_restore(dev);
5725 0 : if (dev->subordinate)
5726 0 : pci_bus_restore_locked(dev->subordinate);
5727 : }
5728 0 : }
5729 :
5730 0 : static int pci_slot_reset(struct pci_slot *slot, bool probe)
5731 : {
5732 : int rc;
5733 :
5734 0 : if (!slot || !pci_slot_resetable(slot))
5735 : return -ENOTTY;
5736 :
5737 0 : if (!probe)
5738 0 : pci_slot_lock(slot);
5739 :
5740 : might_sleep();
5741 :
5742 0 : rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5743 :
5744 0 : if (!probe)
5745 0 : pci_slot_unlock(slot);
5746 :
5747 : return rc;
5748 : }
5749 :
5750 : /**
5751 : * pci_probe_reset_slot - probe whether a PCI slot can be reset
5752 : * @slot: PCI slot to probe
5753 : *
5754 : * Return 0 if slot can be reset, negative if a slot reset is not supported.
5755 : */
5756 0 : int pci_probe_reset_slot(struct pci_slot *slot)
5757 : {
5758 0 : return pci_slot_reset(slot, PCI_RESET_PROBE);
5759 : }
5760 : EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5761 :
5762 : /**
5763 : * __pci_reset_slot - Try to reset a PCI slot
5764 : * @slot: PCI slot to reset
5765 : *
5766 : * A PCI bus may host multiple slots, each slot may support a reset mechanism
5767 : * independent of other slots. For instance, some slots may support slot power
5768 : * control. In the case of a 1:1 bus to slot architecture, this function may
5769 : * wrap the bus reset to avoid spurious slot related events such as hotplug.
5770 : * Generally a slot reset should be attempted before a bus reset. All of the
5771 : * function of the slot and any subordinate buses behind the slot are reset
5772 : * through this function. PCI config space of all devices in the slot and
5773 : * behind the slot is saved before and restored after reset.
5774 : *
5775 : * Same as above except return -EAGAIN if the slot cannot be locked
5776 : */
5777 0 : static int __pci_reset_slot(struct pci_slot *slot)
5778 : {
5779 : int rc;
5780 :
5781 0 : rc = pci_slot_reset(slot, PCI_RESET_PROBE);
5782 0 : if (rc)
5783 : return rc;
5784 :
5785 0 : if (pci_slot_trylock(slot)) {
5786 0 : pci_slot_save_and_disable_locked(slot);
5787 : might_sleep();
5788 0 : rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET);
5789 0 : pci_slot_restore_locked(slot);
5790 0 : pci_slot_unlock(slot);
5791 : } else
5792 : rc = -EAGAIN;
5793 :
5794 : return rc;
5795 : }
5796 :
5797 0 : static int pci_bus_reset(struct pci_bus *bus, bool probe)
5798 : {
5799 : int ret;
5800 :
5801 0 : if (!bus->self || !pci_bus_resetable(bus))
5802 : return -ENOTTY;
5803 :
5804 0 : if (probe)
5805 : return 0;
5806 :
5807 0 : pci_bus_lock(bus);
5808 :
5809 : might_sleep();
5810 :
5811 0 : ret = pci_bridge_secondary_bus_reset(bus->self);
5812 :
5813 0 : pci_bus_unlock(bus);
5814 :
5815 0 : return ret;
5816 : }
5817 :
5818 : /**
5819 : * pci_bus_error_reset - reset the bridge's subordinate bus
5820 : * @bridge: The parent device that connects to the bus to reset
5821 : *
5822 : * This function will first try to reset the slots on this bus if the method is
5823 : * available. If slot reset fails or is not available, this will fall back to a
5824 : * secondary bus reset.
5825 : */
5826 0 : int pci_bus_error_reset(struct pci_dev *bridge)
5827 : {
5828 0 : struct pci_bus *bus = bridge->subordinate;
5829 : struct pci_slot *slot;
5830 :
5831 0 : if (!bus)
5832 : return -ENOTTY;
5833 :
5834 0 : mutex_lock(&pci_slot_mutex);
5835 0 : if (list_empty(&bus->slots))
5836 : goto bus_reset;
5837 :
5838 0 : list_for_each_entry(slot, &bus->slots, list)
5839 0 : if (pci_probe_reset_slot(slot))
5840 : goto bus_reset;
5841 :
5842 0 : list_for_each_entry(slot, &bus->slots, list)
5843 0 : if (pci_slot_reset(slot, PCI_RESET_DO_RESET))
5844 : goto bus_reset;
5845 :
5846 0 : mutex_unlock(&pci_slot_mutex);
5847 0 : return 0;
5848 : bus_reset:
5849 0 : mutex_unlock(&pci_slot_mutex);
5850 0 : return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);
5851 : }
5852 :
5853 : /**
5854 : * pci_probe_reset_bus - probe whether a PCI bus can be reset
5855 : * @bus: PCI bus to probe
5856 : *
5857 : * Return 0 if bus can be reset, negative if a bus reset is not supported.
5858 : */
5859 0 : int pci_probe_reset_bus(struct pci_bus *bus)
5860 : {
5861 0 : return pci_bus_reset(bus, PCI_RESET_PROBE);
5862 : }
5863 : EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5864 :
5865 : /**
5866 : * __pci_reset_bus - Try to reset a PCI bus
5867 : * @bus: top level PCI bus to reset
5868 : *
5869 : * Same as above except return -EAGAIN if the bus cannot be locked
5870 : */
5871 0 : static int __pci_reset_bus(struct pci_bus *bus)
5872 : {
5873 : int rc;
5874 :
5875 0 : rc = pci_bus_reset(bus, PCI_RESET_PROBE);
5876 0 : if (rc)
5877 : return rc;
5878 :
5879 0 : if (pci_bus_trylock(bus)) {
5880 0 : pci_bus_save_and_disable_locked(bus);
5881 : might_sleep();
5882 0 : rc = pci_bridge_secondary_bus_reset(bus->self);
5883 0 : pci_bus_restore_locked(bus);
5884 0 : pci_bus_unlock(bus);
5885 : } else
5886 : rc = -EAGAIN;
5887 :
5888 : return rc;
5889 : }
5890 :
5891 : /**
5892 : * pci_reset_bus - Try to reset a PCI bus
5893 : * @pdev: top level PCI device to reset via slot/bus
5894 : *
5895 : * Same as above except return -EAGAIN if the bus cannot be locked
5896 : */
5897 0 : int pci_reset_bus(struct pci_dev *pdev)
5898 : {
5899 0 : return (!pci_probe_reset_slot(pdev->slot)) ?
5900 0 : __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5901 : }
5902 : EXPORT_SYMBOL_GPL(pci_reset_bus);
5903 :
5904 : /**
5905 : * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5906 : * @dev: PCI device to query
5907 : *
5908 : * Returns mmrbc: maximum designed memory read count in bytes or
5909 : * appropriate error value.
5910 : */
5911 0 : int pcix_get_max_mmrbc(struct pci_dev *dev)
5912 : {
5913 : int cap;
5914 : u32 stat;
5915 :
5916 0 : cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5917 0 : if (!cap)
5918 : return -EINVAL;
5919 :
5920 0 : if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5921 : return -EINVAL;
5922 :
5923 0 : return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5924 : }
5925 : EXPORT_SYMBOL(pcix_get_max_mmrbc);
5926 :
5927 : /**
5928 : * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5929 : * @dev: PCI device to query
5930 : *
5931 : * Returns mmrbc: maximum memory read count in bytes or appropriate error
5932 : * value.
5933 : */
5934 0 : int pcix_get_mmrbc(struct pci_dev *dev)
5935 : {
5936 : int cap;
5937 : u16 cmd;
5938 :
5939 0 : cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5940 0 : if (!cap)
5941 : return -EINVAL;
5942 :
5943 0 : if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5944 : return -EINVAL;
5945 :
5946 0 : return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5947 : }
5948 : EXPORT_SYMBOL(pcix_get_mmrbc);
5949 :
5950 : /**
5951 : * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5952 : * @dev: PCI device to query
5953 : * @mmrbc: maximum memory read count in bytes
5954 : * valid values are 512, 1024, 2048, 4096
5955 : *
5956 : * If possible sets maximum memory read byte count, some bridges have errata
5957 : * that prevent this.
5958 : */
5959 0 : int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5960 : {
5961 : int cap;
5962 : u32 stat, v, o;
5963 : u16 cmd;
5964 :
5965 0 : if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5966 : return -EINVAL;
5967 :
5968 0 : v = ffs(mmrbc) - 10;
5969 :
5970 0 : cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5971 0 : if (!cap)
5972 : return -EINVAL;
5973 :
5974 0 : if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5975 : return -EINVAL;
5976 :
5977 0 : if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5978 : return -E2BIG;
5979 :
5980 0 : if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5981 : return -EINVAL;
5982 :
5983 0 : o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5984 0 : if (o != v) {
5985 0 : if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5986 : return -EIO;
5987 :
5988 0 : cmd &= ~PCI_X_CMD_MAX_READ;
5989 0 : cmd |= v << 2;
5990 0 : if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5991 : return -EIO;
5992 : }
5993 : return 0;
5994 : }
5995 : EXPORT_SYMBOL(pcix_set_mmrbc);
5996 :
5997 : /**
5998 : * pcie_get_readrq - get PCI Express read request size
5999 : * @dev: PCI device to query
6000 : *
6001 : * Returns maximum memory read request in bytes or appropriate error value.
6002 : */
6003 0 : int pcie_get_readrq(struct pci_dev *dev)
6004 : {
6005 : u16 ctl;
6006 :
6007 0 : pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6008 :
6009 0 : return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6010 : }
6011 : EXPORT_SYMBOL(pcie_get_readrq);
6012 :
6013 : /**
6014 : * pcie_set_readrq - set PCI Express maximum memory read request
6015 : * @dev: PCI device to query
6016 : * @rq: maximum memory read count in bytes
6017 : * valid values are 128, 256, 512, 1024, 2048, 4096
6018 : *
6019 : * If possible sets maximum memory read request in bytes
6020 : */
6021 0 : int pcie_set_readrq(struct pci_dev *dev, int rq)
6022 : {
6023 : u16 v;
6024 : int ret;
6025 0 : struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
6026 :
6027 0 : if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
6028 : return -EINVAL;
6029 :
6030 : /*
6031 : * If using the "performance" PCIe config, we clamp the read rq
6032 : * size to the max packet size to keep the host bridge from
6033 : * generating requests larger than we can cope with.
6034 : */
6035 0 : if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
6036 0 : int mps = pcie_get_mps(dev);
6037 :
6038 0 : if (mps < rq)
6039 0 : rq = mps;
6040 : }
6041 :
6042 0 : v = (ffs(rq) - 8) << 12;
6043 :
6044 0 : if (bridge->no_inc_mrrs) {
6045 0 : int max_mrrs = pcie_get_readrq(dev);
6046 :
6047 0 : if (rq > max_mrrs) {
6048 0 : pci_info(dev, "can't set Max_Read_Request_Size to %d; max is %d\n", rq, max_mrrs);
6049 0 : return -EINVAL;
6050 : }
6051 : }
6052 :
6053 0 : ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6054 : PCI_EXP_DEVCTL_READRQ, v);
6055 :
6056 : return pcibios_err_to_errno(ret);
6057 : }
6058 : EXPORT_SYMBOL(pcie_set_readrq);
6059 :
6060 : /**
6061 : * pcie_get_mps - get PCI Express maximum payload size
6062 : * @dev: PCI device to query
6063 : *
6064 : * Returns maximum payload size in bytes
6065 : */
6066 0 : int pcie_get_mps(struct pci_dev *dev)
6067 : {
6068 : u16 ctl;
6069 :
6070 0 : pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6071 :
6072 0 : return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6073 : }
6074 : EXPORT_SYMBOL(pcie_get_mps);
6075 :
6076 : /**
6077 : * pcie_set_mps - set PCI Express maximum payload size
6078 : * @dev: PCI device to query
6079 : * @mps: maximum payload size in bytes
6080 : * valid values are 128, 256, 512, 1024, 2048, 4096
6081 : *
6082 : * If possible sets maximum payload size
6083 : */
6084 0 : int pcie_set_mps(struct pci_dev *dev, int mps)
6085 : {
6086 : u16 v;
6087 : int ret;
6088 :
6089 0 : if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
6090 : return -EINVAL;
6091 :
6092 0 : v = ffs(mps) - 8;
6093 0 : if (v > dev->pcie_mpss)
6094 : return -EINVAL;
6095 0 : v <<= 5;
6096 :
6097 0 : ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6098 : PCI_EXP_DEVCTL_PAYLOAD, v);
6099 :
6100 : return pcibios_err_to_errno(ret);
6101 : }
6102 : EXPORT_SYMBOL(pcie_set_mps);
6103 :
6104 : /**
6105 : * pcie_bandwidth_available - determine minimum link settings of a PCIe
6106 : * device and its bandwidth limitation
6107 : * @dev: PCI device to query
6108 : * @limiting_dev: storage for device causing the bandwidth limitation
6109 : * @speed: storage for speed of limiting device
6110 : * @width: storage for width of limiting device
6111 : *
6112 : * Walk up the PCI device chain and find the point where the minimum
6113 : * bandwidth is available. Return the bandwidth available there and (if
6114 : * limiting_dev, speed, and width pointers are supplied) information about
6115 : * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6116 : * raw bandwidth.
6117 : */
6118 0 : u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
6119 : enum pci_bus_speed *speed,
6120 : enum pcie_link_width *width)
6121 : {
6122 : u16 lnksta;
6123 : enum pci_bus_speed next_speed;
6124 : enum pcie_link_width next_width;
6125 : u32 bw, next_bw;
6126 :
6127 0 : if (speed)
6128 0 : *speed = PCI_SPEED_UNKNOWN;
6129 0 : if (width)
6130 0 : *width = PCIE_LNK_WIDTH_UNKNOWN;
6131 :
6132 : bw = 0;
6133 :
6134 0 : while (dev) {
6135 0 : pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
6136 :
6137 0 : next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
6138 0 : next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
6139 : PCI_EXP_LNKSTA_NLW_SHIFT;
6140 :
6141 0 : next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
6142 :
6143 : /* Check if current device limits the total bandwidth */
6144 0 : if (!bw || next_bw <= bw) {
6145 0 : bw = next_bw;
6146 :
6147 0 : if (limiting_dev)
6148 0 : *limiting_dev = dev;
6149 0 : if (speed)
6150 0 : *speed = next_speed;
6151 0 : if (width)
6152 0 : *width = next_width;
6153 : }
6154 :
6155 0 : dev = pci_upstream_bridge(dev);
6156 : }
6157 :
6158 0 : return bw;
6159 : }
6160 : EXPORT_SYMBOL(pcie_bandwidth_available);
6161 :
6162 : /**
6163 : * pcie_get_speed_cap - query for the PCI device's link speed capability
6164 : * @dev: PCI device to query
6165 : *
6166 : * Query the PCI device speed capability. Return the maximum link speed
6167 : * supported by the device.
6168 : */
6169 0 : enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6170 : {
6171 : u32 lnkcap2, lnkcap;
6172 :
6173 : /*
6174 : * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6175 : * implementation note there recommends using the Supported Link
6176 : * Speeds Vector in Link Capabilities 2 when supported.
6177 : *
6178 : * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6179 : * should use the Supported Link Speeds field in Link Capabilities,
6180 : * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6181 : */
6182 0 : pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6183 :
6184 : /* PCIe r3.0-compliant */
6185 0 : if (lnkcap2)
6186 0 : return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
6187 :
6188 0 : pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6189 0 : if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6190 : return PCIE_SPEED_5_0GT;
6191 0 : else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6192 : return PCIE_SPEED_2_5GT;
6193 :
6194 0 : return PCI_SPEED_UNKNOWN;
6195 : }
6196 : EXPORT_SYMBOL(pcie_get_speed_cap);
6197 :
6198 : /**
6199 : * pcie_get_width_cap - query for the PCI device's link width capability
6200 : * @dev: PCI device to query
6201 : *
6202 : * Query the PCI device width capability. Return the maximum link width
6203 : * supported by the device.
6204 : */
6205 0 : enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
6206 : {
6207 : u32 lnkcap;
6208 :
6209 0 : pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6210 0 : if (lnkcap)
6211 0 : return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
6212 :
6213 : return PCIE_LNK_WIDTH_UNKNOWN;
6214 : }
6215 : EXPORT_SYMBOL(pcie_get_width_cap);
6216 :
6217 : /**
6218 : * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6219 : * @dev: PCI device
6220 : * @speed: storage for link speed
6221 : * @width: storage for link width
6222 : *
6223 : * Calculate a PCI device's link bandwidth by querying for its link speed
6224 : * and width, multiplying them, and applying encoding overhead. The result
6225 : * is in Mb/s, i.e., megabits/second of raw bandwidth.
6226 : */
6227 0 : u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6228 : enum pcie_link_width *width)
6229 : {
6230 0 : *speed = pcie_get_speed_cap(dev);
6231 0 : *width = pcie_get_width_cap(dev);
6232 :
6233 0 : if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6234 : return 0;
6235 :
6236 0 : return *width * PCIE_SPEED2MBS_ENC(*speed);
6237 : }
6238 :
6239 : /**
6240 : * __pcie_print_link_status - Report the PCI device's link speed and width
6241 : * @dev: PCI device to query
6242 : * @verbose: Print info even when enough bandwidth is available
6243 : *
6244 : * If the available bandwidth at the device is less than the device is
6245 : * capable of, report the device's maximum possible bandwidth and the
6246 : * upstream link that limits its performance. If @verbose, always print
6247 : * the available bandwidth, even if the device isn't constrained.
6248 : */
6249 0 : void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6250 : {
6251 : enum pcie_link_width width, width_cap;
6252 : enum pci_bus_speed speed, speed_cap;
6253 0 : struct pci_dev *limiting_dev = NULL;
6254 : u32 bw_avail, bw_cap;
6255 :
6256 0 : bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6257 0 : bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6258 :
6259 0 : if (bw_avail >= bw_cap && verbose)
6260 0 : pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6261 : bw_cap / 1000, bw_cap % 1000,
6262 : pci_speed_string(speed_cap), width_cap);
6263 0 : else if (bw_avail < bw_cap)
6264 0 : pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6265 : bw_avail / 1000, bw_avail % 1000,
6266 : pci_speed_string(speed), width,
6267 : limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6268 : bw_cap / 1000, bw_cap % 1000,
6269 : pci_speed_string(speed_cap), width_cap);
6270 0 : }
6271 :
6272 : /**
6273 : * pcie_print_link_status - Report the PCI device's link speed and width
6274 : * @dev: PCI device to query
6275 : *
6276 : * Report the available bandwidth at the device.
6277 : */
6278 0 : void pcie_print_link_status(struct pci_dev *dev)
6279 : {
6280 0 : __pcie_print_link_status(dev, true);
6281 0 : }
6282 : EXPORT_SYMBOL(pcie_print_link_status);
6283 :
6284 : /**
6285 : * pci_select_bars - Make BAR mask from the type of resource
6286 : * @dev: the PCI device for which BAR mask is made
6287 : * @flags: resource type mask to be selected
6288 : *
6289 : * This helper routine makes bar mask from the type of resource.
6290 : */
6291 0 : int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6292 : {
6293 0 : int i, bars = 0;
6294 0 : for (i = 0; i < PCI_NUM_RESOURCES; i++)
6295 0 : if (pci_resource_flags(dev, i) & flags)
6296 0 : bars |= (1 << i);
6297 0 : return bars;
6298 : }
6299 : EXPORT_SYMBOL(pci_select_bars);
6300 :
6301 : /* Some architectures require additional programming to enable VGA */
6302 : static arch_set_vga_state_t arch_set_vga_state;
6303 :
6304 0 : void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6305 : {
6306 0 : arch_set_vga_state = func; /* NULL disables */
6307 0 : }
6308 :
6309 : static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6310 : unsigned int command_bits, u32 flags)
6311 : {
6312 0 : if (arch_set_vga_state)
6313 0 : return arch_set_vga_state(dev, decode, command_bits,
6314 : flags);
6315 : return 0;
6316 : }
6317 :
6318 : /**
6319 : * pci_set_vga_state - set VGA decode state on device and parents if requested
6320 : * @dev: the PCI device
6321 : * @decode: true = enable decoding, false = disable decoding
6322 : * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6323 : * @flags: traverse ancestors and change bridges
6324 : * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6325 : */
6326 0 : int pci_set_vga_state(struct pci_dev *dev, bool decode,
6327 : unsigned int command_bits, u32 flags)
6328 : {
6329 : struct pci_bus *bus;
6330 : struct pci_dev *bridge;
6331 : u16 cmd;
6332 : int rc;
6333 :
6334 0 : WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6335 :
6336 : /* ARCH specific VGA enables */
6337 0 : rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6338 0 : if (rc)
6339 : return rc;
6340 :
6341 0 : if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6342 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
6343 0 : if (decode)
6344 0 : cmd |= command_bits;
6345 : else
6346 0 : cmd &= ~command_bits;
6347 0 : pci_write_config_word(dev, PCI_COMMAND, cmd);
6348 : }
6349 :
6350 0 : if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6351 : return 0;
6352 :
6353 0 : bus = dev->bus;
6354 0 : while (bus) {
6355 0 : bridge = bus->self;
6356 0 : if (bridge) {
6357 0 : pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6358 : &cmd);
6359 0 : if (decode)
6360 0 : cmd |= PCI_BRIDGE_CTL_VGA;
6361 : else
6362 0 : cmd &= ~PCI_BRIDGE_CTL_VGA;
6363 0 : pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6364 : cmd);
6365 : }
6366 0 : bus = bus->parent;
6367 : }
6368 : return 0;
6369 : }
6370 :
6371 : #ifdef CONFIG_ACPI
6372 : bool pci_pr3_present(struct pci_dev *pdev)
6373 : {
6374 : struct acpi_device *adev;
6375 :
6376 : if (acpi_disabled)
6377 : return false;
6378 :
6379 : adev = ACPI_COMPANION(&pdev->dev);
6380 : if (!adev)
6381 : return false;
6382 :
6383 : return adev->power.flags.power_resources &&
6384 : acpi_has_method(adev->handle, "_PR3");
6385 : }
6386 : EXPORT_SYMBOL_GPL(pci_pr3_present);
6387 : #endif
6388 :
6389 : /**
6390 : * pci_add_dma_alias - Add a DMA devfn alias for a device
6391 : * @dev: the PCI device for which alias is added
6392 : * @devfn_from: alias slot and function
6393 : * @nr_devfns: number of subsequent devfns to alias
6394 : *
6395 : * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6396 : * which is used to program permissible bus-devfn source addresses for DMA
6397 : * requests in an IOMMU. These aliases factor into IOMMU group creation
6398 : * and are useful for devices generating DMA requests beyond or different
6399 : * from their logical bus-devfn. Examples include device quirks where the
6400 : * device simply uses the wrong devfn, as well as non-transparent bridges
6401 : * where the alias may be a proxy for devices in another domain.
6402 : *
6403 : * IOMMU group creation is performed during device discovery or addition,
6404 : * prior to any potential DMA mapping and therefore prior to driver probing
6405 : * (especially for userspace assigned devices where IOMMU group definition
6406 : * cannot be left as a userspace activity). DMA aliases should therefore
6407 : * be configured via quirks, such as the PCI fixup header quirk.
6408 : */
6409 0 : void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from,
6410 : unsigned int nr_devfns)
6411 : {
6412 : int devfn_to;
6413 :
6414 0 : nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from);
6415 0 : devfn_to = devfn_from + nr_devfns - 1;
6416 :
6417 0 : if (!dev->dma_alias_mask)
6418 0 : dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6419 0 : if (!dev->dma_alias_mask) {
6420 0 : pci_warn(dev, "Unable to allocate DMA alias mask\n");
6421 0 : return;
6422 : }
6423 :
6424 0 : bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6425 :
6426 0 : if (nr_devfns == 1)
6427 0 : pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6428 : PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6429 0 : else if (nr_devfns > 1)
6430 0 : pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6431 : PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6432 : PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6433 : }
6434 :
6435 0 : bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6436 : {
6437 0 : return (dev1->dma_alias_mask &&
6438 0 : test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6439 0 : (dev2->dma_alias_mask &&
6440 0 : test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6441 0 : pci_real_dma_dev(dev1) == dev2 ||
6442 0 : pci_real_dma_dev(dev2) == dev1;
6443 : }
6444 :
6445 0 : bool pci_device_is_present(struct pci_dev *pdev)
6446 : {
6447 : u32 v;
6448 :
6449 : /* Check PF if pdev is a VF, since VF Vendor/Device IDs are 0xffff */
6450 0 : pdev = pci_physfn(pdev);
6451 0 : if (pci_dev_is_disconnected(pdev))
6452 : return false;
6453 0 : return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6454 : }
6455 : EXPORT_SYMBOL_GPL(pci_device_is_present);
6456 :
6457 0 : void pci_ignore_hotplug(struct pci_dev *dev)
6458 : {
6459 0 : struct pci_dev *bridge = dev->bus->self;
6460 :
6461 0 : dev->ignore_hotplug = 1;
6462 : /* Propagate the "ignore hotplug" setting to the parent bridge. */
6463 0 : if (bridge)
6464 0 : bridge->ignore_hotplug = 1;
6465 0 : }
6466 : EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6467 :
6468 : /**
6469 : * pci_real_dma_dev - Get PCI DMA device for PCI device
6470 : * @dev: the PCI device that may have a PCI DMA alias
6471 : *
6472 : * Permits the platform to provide architecture-specific functionality to
6473 : * devices needing to alias DMA to another PCI device on another PCI bus. If
6474 : * the PCI device is on the same bus, it is recommended to use
6475 : * pci_add_dma_alias(). This is the default implementation. Architecture
6476 : * implementations can override this.
6477 : */
6478 0 : struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6479 : {
6480 0 : return dev;
6481 : }
6482 :
6483 0 : resource_size_t __weak pcibios_default_alignment(void)
6484 : {
6485 0 : return 0;
6486 : }
6487 :
6488 : /*
6489 : * Arches that don't want to expose struct resource to userland as-is in
6490 : * sysfs and /proc can implement their own pci_resource_to_user().
6491 : */
6492 0 : void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6493 : const struct resource *rsrc,
6494 : resource_size_t *start, resource_size_t *end)
6495 : {
6496 0 : *start = rsrc->start;
6497 0 : *end = rsrc->end;
6498 0 : }
6499 :
6500 : static char *resource_alignment_param;
6501 : static DEFINE_SPINLOCK(resource_alignment_lock);
6502 :
6503 : /**
6504 : * pci_specified_resource_alignment - get resource alignment specified by user.
6505 : * @dev: the PCI device to get
6506 : * @resize: whether or not to change resources' size when reassigning alignment
6507 : *
6508 : * RETURNS: Resource alignment if it is specified.
6509 : * Zero if it is not specified.
6510 : */
6511 0 : static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6512 : bool *resize)
6513 : {
6514 : int align_order, count;
6515 0 : resource_size_t align = pcibios_default_alignment();
6516 : const char *p;
6517 : int ret;
6518 :
6519 0 : spin_lock(&resource_alignment_lock);
6520 0 : p = resource_alignment_param;
6521 0 : if (!p || !*p)
6522 : goto out;
6523 0 : if (pci_has_flag(PCI_PROBE_ONLY)) {
6524 0 : align = 0;
6525 0 : pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6526 : goto out;
6527 : }
6528 :
6529 0 : while (*p) {
6530 0 : count = 0;
6531 0 : if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6532 0 : p[count] == '@') {
6533 0 : p += count + 1;
6534 0 : if (align_order > 63) {
6535 0 : pr_err("PCI: Invalid requested alignment (order %d)\n",
6536 : align_order);
6537 0 : align_order = PAGE_SHIFT;
6538 : }
6539 : } else {
6540 0 : align_order = PAGE_SHIFT;
6541 : }
6542 :
6543 0 : ret = pci_dev_str_match(dev, p, &p);
6544 0 : if (ret == 1) {
6545 0 : *resize = true;
6546 0 : align = 1ULL << align_order;
6547 0 : break;
6548 0 : } else if (ret < 0) {
6549 0 : pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6550 : p);
6551 0 : break;
6552 : }
6553 :
6554 0 : if (*p != ';' && *p != ',') {
6555 : /* End of param or invalid format */
6556 : break;
6557 : }
6558 0 : p++;
6559 : }
6560 : out:
6561 0 : spin_unlock(&resource_alignment_lock);
6562 0 : return align;
6563 : }
6564 :
6565 0 : static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6566 : resource_size_t align, bool resize)
6567 : {
6568 0 : struct resource *r = &dev->resource[bar];
6569 : resource_size_t size;
6570 :
6571 0 : if (!(r->flags & IORESOURCE_MEM))
6572 : return;
6573 :
6574 0 : if (r->flags & IORESOURCE_PCI_FIXED) {
6575 0 : pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6576 : bar, r, (unsigned long long)align);
6577 0 : return;
6578 : }
6579 :
6580 0 : size = resource_size(r);
6581 0 : if (size >= align)
6582 : return;
6583 :
6584 : /*
6585 : * Increase the alignment of the resource. There are two ways we
6586 : * can do this:
6587 : *
6588 : * 1) Increase the size of the resource. BARs are aligned on their
6589 : * size, so when we reallocate space for this resource, we'll
6590 : * allocate it with the larger alignment. This also prevents
6591 : * assignment of any other BARs inside the alignment region, so
6592 : * if we're requesting page alignment, this means no other BARs
6593 : * will share the page.
6594 : *
6595 : * The disadvantage is that this makes the resource larger than
6596 : * the hardware BAR, which may break drivers that compute things
6597 : * based on the resource size, e.g., to find registers at a
6598 : * fixed offset before the end of the BAR.
6599 : *
6600 : * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6601 : * set r->start to the desired alignment. By itself this
6602 : * doesn't prevent other BARs being put inside the alignment
6603 : * region, but if we realign *every* resource of every device in
6604 : * the system, none of them will share an alignment region.
6605 : *
6606 : * When the user has requested alignment for only some devices via
6607 : * the "pci=resource_alignment" argument, "resize" is true and we
6608 : * use the first method. Otherwise we assume we're aligning all
6609 : * devices and we use the second.
6610 : */
6611 :
6612 0 : pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6613 : bar, r, (unsigned long long)align);
6614 :
6615 0 : if (resize) {
6616 0 : r->start = 0;
6617 0 : r->end = align - 1;
6618 : } else {
6619 0 : r->flags &= ~IORESOURCE_SIZEALIGN;
6620 0 : r->flags |= IORESOURCE_STARTALIGN;
6621 0 : r->start = align;
6622 0 : r->end = r->start + size - 1;
6623 : }
6624 0 : r->flags |= IORESOURCE_UNSET;
6625 : }
6626 :
6627 : /*
6628 : * This function disables memory decoding and releases memory resources
6629 : * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6630 : * It also rounds up size to specified alignment.
6631 : * Later on, the kernel will assign page-aligned memory resource back
6632 : * to the device.
6633 : */
6634 0 : void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6635 : {
6636 : int i;
6637 : struct resource *r;
6638 : resource_size_t align;
6639 : u16 command;
6640 0 : bool resize = false;
6641 :
6642 : /*
6643 : * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6644 : * 3.4.1.11. Their resources are allocated from the space
6645 : * described by the VF BARx register in the PF's SR-IOV capability.
6646 : * We can't influence their alignment here.
6647 : */
6648 0 : if (dev->is_virtfn)
6649 0 : return;
6650 :
6651 : /* check if specified PCI is target device to reassign */
6652 0 : align = pci_specified_resource_alignment(dev, &resize);
6653 0 : if (!align)
6654 : return;
6655 :
6656 0 : if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6657 0 : (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6658 0 : pci_warn(dev, "Can't reassign resources to host bridge\n");
6659 0 : return;
6660 : }
6661 :
6662 0 : pci_read_config_word(dev, PCI_COMMAND, &command);
6663 0 : command &= ~PCI_COMMAND_MEMORY;
6664 0 : pci_write_config_word(dev, PCI_COMMAND, command);
6665 :
6666 0 : for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6667 0 : pci_request_resource_alignment(dev, i, align, resize);
6668 :
6669 : /*
6670 : * Need to disable bridge's resource window,
6671 : * to enable the kernel to reassign new resource
6672 : * window later on.
6673 : */
6674 0 : if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6675 0 : for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6676 0 : r = &dev->resource[i];
6677 0 : if (!(r->flags & IORESOURCE_MEM))
6678 0 : continue;
6679 0 : r->flags |= IORESOURCE_UNSET;
6680 0 : r->end = resource_size(r) - 1;
6681 0 : r->start = 0;
6682 : }
6683 0 : pci_disable_bridge_window(dev);
6684 : }
6685 : }
6686 :
6687 0 : static ssize_t resource_alignment_show(const struct bus_type *bus, char *buf)
6688 : {
6689 0 : size_t count = 0;
6690 :
6691 0 : spin_lock(&resource_alignment_lock);
6692 0 : if (resource_alignment_param)
6693 0 : count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6694 0 : spin_unlock(&resource_alignment_lock);
6695 :
6696 0 : return count;
6697 : }
6698 :
6699 0 : static ssize_t resource_alignment_store(const struct bus_type *bus,
6700 : const char *buf, size_t count)
6701 : {
6702 : char *param, *old, *end;
6703 :
6704 0 : if (count >= (PAGE_SIZE - 1))
6705 : return -EINVAL;
6706 :
6707 0 : param = kstrndup(buf, count, GFP_KERNEL);
6708 0 : if (!param)
6709 : return -ENOMEM;
6710 :
6711 0 : end = strchr(param, '\n');
6712 0 : if (end)
6713 0 : *end = '\0';
6714 :
6715 0 : spin_lock(&resource_alignment_lock);
6716 0 : old = resource_alignment_param;
6717 0 : if (strlen(param)) {
6718 0 : resource_alignment_param = param;
6719 : } else {
6720 0 : kfree(param);
6721 0 : resource_alignment_param = NULL;
6722 : }
6723 0 : spin_unlock(&resource_alignment_lock);
6724 :
6725 0 : kfree(old);
6726 :
6727 0 : return count;
6728 : }
6729 :
6730 : static BUS_ATTR_RW(resource_alignment);
6731 :
6732 1 : static int __init pci_resource_alignment_sysfs_init(void)
6733 : {
6734 1 : return bus_create_file(&pci_bus_type,
6735 : &bus_attr_resource_alignment);
6736 : }
6737 : late_initcall(pci_resource_alignment_sysfs_init);
6738 :
6739 : static void pci_no_domains(void)
6740 : {
6741 : #ifdef CONFIG_PCI_DOMAINS
6742 : pci_domains_supported = 0;
6743 : #endif
6744 : }
6745 :
6746 : #ifdef CONFIG_PCI_DOMAINS_GENERIC
6747 : static DEFINE_IDA(pci_domain_nr_static_ida);
6748 : static DEFINE_IDA(pci_domain_nr_dynamic_ida);
6749 :
6750 : static void of_pci_reserve_static_domain_nr(void)
6751 : {
6752 : struct device_node *np;
6753 : int domain_nr;
6754 :
6755 : for_each_node_by_type(np, "pci") {
6756 : domain_nr = of_get_pci_domain_nr(np);
6757 : if (domain_nr < 0)
6758 : continue;
6759 : /*
6760 : * Permanently allocate domain_nr in dynamic_ida
6761 : * to prevent it from dynamic allocation.
6762 : */
6763 : ida_alloc_range(&pci_domain_nr_dynamic_ida,
6764 : domain_nr, domain_nr, GFP_KERNEL);
6765 : }
6766 : }
6767 :
6768 : static int of_pci_bus_find_domain_nr(struct device *parent)
6769 : {
6770 : static bool static_domains_reserved = false;
6771 : int domain_nr;
6772 :
6773 : /* On the first call scan device tree for static allocations. */
6774 : if (!static_domains_reserved) {
6775 : of_pci_reserve_static_domain_nr();
6776 : static_domains_reserved = true;
6777 : }
6778 :
6779 : if (parent) {
6780 : /*
6781 : * If domain is in DT, allocate it in static IDA. This
6782 : * prevents duplicate static allocations in case of errors
6783 : * in DT.
6784 : */
6785 : domain_nr = of_get_pci_domain_nr(parent->of_node);
6786 : if (domain_nr >= 0)
6787 : return ida_alloc_range(&pci_domain_nr_static_ida,
6788 : domain_nr, domain_nr,
6789 : GFP_KERNEL);
6790 : }
6791 :
6792 : /*
6793 : * If domain was not specified in DT, choose a free ID from dynamic
6794 : * allocations. All domain numbers from DT are permanently in
6795 : * dynamic allocations to prevent assigning them to other DT nodes
6796 : * without static domain.
6797 : */
6798 : return ida_alloc(&pci_domain_nr_dynamic_ida, GFP_KERNEL);
6799 : }
6800 :
6801 : static void of_pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
6802 : {
6803 : if (bus->domain_nr < 0)
6804 : return;
6805 :
6806 : /* Release domain from IDA where it was allocated. */
6807 : if (of_get_pci_domain_nr(parent->of_node) == bus->domain_nr)
6808 : ida_free(&pci_domain_nr_static_ida, bus->domain_nr);
6809 : else
6810 : ida_free(&pci_domain_nr_dynamic_ida, bus->domain_nr);
6811 : }
6812 :
6813 : int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6814 : {
6815 : return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6816 : acpi_pci_bus_find_domain_nr(bus);
6817 : }
6818 :
6819 : void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
6820 : {
6821 : if (!acpi_disabled)
6822 : return;
6823 : of_pci_bus_release_domain_nr(bus, parent);
6824 : }
6825 : #endif
6826 :
6827 : /**
6828 : * pci_ext_cfg_avail - can we access extended PCI config space?
6829 : *
6830 : * Returns 1 if we can access PCI extended config space (offsets
6831 : * greater than 0xff). This is the default implementation. Architecture
6832 : * implementations can override this.
6833 : */
6834 0 : int __weak pci_ext_cfg_avail(void)
6835 : {
6836 0 : return 1;
6837 : }
6838 :
6839 0 : void __weak pci_fixup_cardbus(struct pci_bus *bus)
6840 : {
6841 0 : }
6842 : EXPORT_SYMBOL(pci_fixup_cardbus);
6843 :
6844 0 : static int __init pci_setup(char *str)
6845 : {
6846 0 : while (str) {
6847 0 : char *k = strchr(str, ',');
6848 0 : if (k)
6849 0 : *k++ = 0;
6850 0 : if (*str && (str = pcibios_setup(str)) && *str) {
6851 0 : if (!strcmp(str, "nomsi")) {
6852 0 : pci_no_msi();
6853 0 : } else if (!strncmp(str, "noats", 5)) {
6854 0 : pr_info("PCIe: ATS is disabled\n");
6855 0 : pcie_ats_disabled = true;
6856 0 : } else if (!strcmp(str, "noaer")) {
6857 : pci_no_aer();
6858 0 : } else if (!strcmp(str, "earlydump")) {
6859 0 : pci_early_dump = true;
6860 0 : } else if (!strncmp(str, "realloc=", 8)) {
6861 0 : pci_realloc_get_opt(str + 8);
6862 0 : } else if (!strncmp(str, "realloc", 7)) {
6863 0 : pci_realloc_get_opt("on");
6864 0 : } else if (!strcmp(str, "nodomains")) {
6865 : pci_no_domains();
6866 0 : } else if (!strncmp(str, "noari", 5)) {
6867 0 : pcie_ari_disabled = true;
6868 0 : } else if (!strncmp(str, "cbiosize=", 9)) {
6869 0 : pci_cardbus_io_size = memparse(str + 9, &str);
6870 0 : } else if (!strncmp(str, "cbmemsize=", 10)) {
6871 0 : pci_cardbus_mem_size = memparse(str + 10, &str);
6872 0 : } else if (!strncmp(str, "resource_alignment=", 19)) {
6873 0 : resource_alignment_param = str + 19;
6874 0 : } else if (!strncmp(str, "ecrc=", 5)) {
6875 : pcie_ecrc_get_policy(str + 5);
6876 0 : } else if (!strncmp(str, "hpiosize=", 9)) {
6877 0 : pci_hotplug_io_size = memparse(str + 9, &str);
6878 0 : } else if (!strncmp(str, "hpmmiosize=", 11)) {
6879 0 : pci_hotplug_mmio_size = memparse(str + 11, &str);
6880 0 : } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6881 0 : pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6882 0 : } else if (!strncmp(str, "hpmemsize=", 10)) {
6883 0 : pci_hotplug_mmio_size = memparse(str + 10, &str);
6884 0 : pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6885 0 : } else if (!strncmp(str, "hpbussize=", 10)) {
6886 0 : pci_hotplug_bus_size =
6887 0 : simple_strtoul(str + 10, &str, 0);
6888 0 : if (pci_hotplug_bus_size > 0xff)
6889 0 : pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6890 0 : } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6891 0 : pcie_bus_config = PCIE_BUS_TUNE_OFF;
6892 0 : } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6893 0 : pcie_bus_config = PCIE_BUS_SAFE;
6894 0 : } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6895 0 : pcie_bus_config = PCIE_BUS_PERFORMANCE;
6896 0 : } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6897 0 : pcie_bus_config = PCIE_BUS_PEER2PEER;
6898 0 : } else if (!strncmp(str, "pcie_scan_all", 13)) {
6899 : pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6900 0 : } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6901 0 : disable_acs_redir_param = str + 18;
6902 : } else {
6903 0 : pr_err("PCI: Unknown option `%s'\n", str);
6904 : }
6905 : }
6906 0 : str = k;
6907 : }
6908 0 : return 0;
6909 : }
6910 : early_param("pci", pci_setup);
6911 :
6912 : /*
6913 : * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6914 : * in pci_setup(), above, to point to data in the __initdata section which
6915 : * will be freed after the init sequence is complete. We can't allocate memory
6916 : * in pci_setup() because some architectures do not have any memory allocation
6917 : * service available during an early_param() call. So we allocate memory and
6918 : * copy the variable here before the init section is freed.
6919 : *
6920 : */
6921 1 : static int __init pci_realloc_setup_params(void)
6922 : {
6923 1 : resource_alignment_param = kstrdup(resource_alignment_param,
6924 : GFP_KERNEL);
6925 1 : disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6926 :
6927 1 : return 0;
6928 : }
6929 : pure_initcall(pci_realloc_setup_params);
|
