Line data Source code
1 : /* SPDX-License-Identifier: GPL-2.0 */
2 : #ifndef DRIVERS_PCI_H
3 : #define DRIVERS_PCI_H
4 :
5 : #include <linux/pci.h>
6 :
7 : /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 : #define MAX_NR_DEVFNS 256
9 :
10 : #define PCI_FIND_CAP_TTL 48
11 :
12 : #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13 :
14 : extern const unsigned char pcie_link_speed[];
15 : extern bool pci_early_dump;
16 :
17 : bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
18 : bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
19 : bool pcie_cap_has_rtctl(const struct pci_dev *dev);
20 :
21 : /* Functions internal to the PCI core code */
22 :
23 : int pci_create_sysfs_dev_files(struct pci_dev *pdev);
24 : void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
25 : void pci_cleanup_rom(struct pci_dev *dev);
26 : #ifdef CONFIG_DMI
27 : extern const struct attribute_group pci_dev_smbios_attr_group;
28 : #endif
29 :
30 : enum pci_mmap_api {
31 : PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
32 : PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
33 : };
34 : int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
35 : enum pci_mmap_api mmap_api);
36 :
37 : bool pci_reset_supported(struct pci_dev *dev);
38 : void pci_init_reset_methods(struct pci_dev *dev);
39 : int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
40 : int pci_bus_error_reset(struct pci_dev *dev);
41 :
42 : struct pci_cap_saved_data {
43 : u16 cap_nr;
44 : bool cap_extended;
45 : unsigned int size;
46 : u32 data[];
47 : };
48 :
49 : struct pci_cap_saved_state {
50 : struct hlist_node next;
51 : struct pci_cap_saved_data cap;
52 : };
53 :
54 : void pci_allocate_cap_save_buffers(struct pci_dev *dev);
55 : void pci_free_cap_save_buffers(struct pci_dev *dev);
56 : int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
57 : int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
58 : u16 cap, unsigned int size);
59 : struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
60 : struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
61 : u16 cap);
62 :
63 : #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
64 : #define PCI_PM_D3HOT_WAIT 10 /* msec */
65 : #define PCI_PM_D3COLD_WAIT 100 /* msec */
66 :
67 : /*
68 : * Following exit from Conventional Reset, devices must be ready within 1 sec
69 : * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
70 : * Reset (PCIe r6.0 sec 5.8).
71 : */
72 : #define PCI_RESET_WAIT 1000 /* msec */
73 :
74 : void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
75 : void pci_refresh_power_state(struct pci_dev *dev);
76 : int pci_power_up(struct pci_dev *dev);
77 : void pci_disable_enabled_device(struct pci_dev *dev);
78 : int pci_finish_runtime_suspend(struct pci_dev *dev);
79 : void pcie_clear_device_status(struct pci_dev *dev);
80 : void pcie_clear_root_pme_status(struct pci_dev *dev);
81 : bool pci_check_pme_status(struct pci_dev *dev);
82 : void pci_pme_wakeup_bus(struct pci_bus *bus);
83 : int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
84 : void pci_pme_restore(struct pci_dev *dev);
85 : bool pci_dev_need_resume(struct pci_dev *dev);
86 : void pci_dev_adjust_pme(struct pci_dev *dev);
87 : void pci_dev_complete_resume(struct pci_dev *pci_dev);
88 : void pci_config_pm_runtime_get(struct pci_dev *dev);
89 : void pci_config_pm_runtime_put(struct pci_dev *dev);
90 : void pci_pm_init(struct pci_dev *dev);
91 : void pci_ea_init(struct pci_dev *dev);
92 : void pci_msi_init(struct pci_dev *dev);
93 : void pci_msix_init(struct pci_dev *dev);
94 : bool pci_bridge_d3_possible(struct pci_dev *dev);
95 : void pci_bridge_d3_update(struct pci_dev *dev);
96 : void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
97 : int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
98 :
99 : static inline void pci_wakeup_event(struct pci_dev *dev)
100 : {
101 : /* Wait 100 ms before the system can be put into a sleep state. */
102 0 : pm_wakeup_event(&dev->dev, 100);
103 : }
104 :
105 : static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
106 : {
107 : return !!(pci_dev->subordinate);
108 : }
109 :
110 : static inline bool pci_power_manageable(struct pci_dev *pci_dev)
111 : {
112 : /*
113 : * Currently we allow normal PCI devices and PCI bridges transition
114 : * into D3 if their bridge_d3 is set.
115 : */
116 0 : return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
117 : }
118 :
119 : static inline bool pcie_downstream_port(const struct pci_dev *dev)
120 : {
121 0 : int type = pci_pcie_type(dev);
122 :
123 0 : return type == PCI_EXP_TYPE_ROOT_PORT ||
124 0 : type == PCI_EXP_TYPE_DOWNSTREAM ||
125 : type == PCI_EXP_TYPE_PCIE_BRIDGE;
126 : }
127 :
128 : void pci_vpd_init(struct pci_dev *dev);
129 : void pci_vpd_release(struct pci_dev *dev);
130 : extern const struct attribute_group pci_dev_vpd_attr_group;
131 :
132 : /* PCI Virtual Channel */
133 : int pci_save_vc_state(struct pci_dev *dev);
134 : void pci_restore_vc_state(struct pci_dev *dev);
135 : void pci_allocate_vc_save_buffers(struct pci_dev *dev);
136 :
137 : /* PCI /proc functions */
138 : #ifdef CONFIG_PROC_FS
139 : int pci_proc_attach_device(struct pci_dev *dev);
140 : int pci_proc_detach_device(struct pci_dev *dev);
141 : int pci_proc_detach_bus(struct pci_bus *bus);
142 : #else
143 : static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
144 : static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
145 : static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
146 : #endif
147 :
148 : /* Functions for PCI Hotplug drivers to use */
149 : int pci_hp_add_bridge(struct pci_dev *dev);
150 :
151 : #ifdef HAVE_PCI_LEGACY
152 : void pci_create_legacy_files(struct pci_bus *bus);
153 : void pci_remove_legacy_files(struct pci_bus *bus);
154 : #else
155 : static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
156 : static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
157 : #endif
158 :
159 : /* Lock for read/write access to pci device and bus lists */
160 : extern struct rw_semaphore pci_bus_sem;
161 : extern struct mutex pci_slot_mutex;
162 :
163 : extern raw_spinlock_t pci_lock;
164 :
165 : extern unsigned int pci_pm_d3hot_delay;
166 :
167 : #ifdef CONFIG_PCI_MSI
168 : void pci_no_msi(void);
169 : #else
170 : static inline void pci_no_msi(void) { }
171 : #endif
172 :
173 : void pci_realloc_get_opt(char *);
174 :
175 : static inline int pci_no_d1d2(struct pci_dev *dev)
176 : {
177 0 : unsigned int parent_dstates = 0;
178 :
179 0 : if (dev->bus->self)
180 0 : parent_dstates = dev->bus->self->no_d1d2;
181 0 : return (dev->no_d1d2 || parent_dstates);
182 :
183 : }
184 : extern const struct attribute_group *pci_dev_groups[];
185 : extern const struct attribute_group *pcibus_groups[];
186 : extern const struct device_type pci_dev_type;
187 : extern const struct attribute_group *pci_bus_groups[];
188 :
189 : extern unsigned long pci_hotplug_io_size;
190 : extern unsigned long pci_hotplug_mmio_size;
191 : extern unsigned long pci_hotplug_mmio_pref_size;
192 : extern unsigned long pci_hotplug_bus_size;
193 :
194 : /**
195 : * pci_match_one_device - Tell if a PCI device structure has a matching
196 : * PCI device id structure
197 : * @id: single PCI device id structure to match
198 : * @dev: the PCI device structure to match against
199 : *
200 : * Returns the matching pci_device_id structure or %NULL if there is no match.
201 : */
202 : static inline const struct pci_device_id *
203 0 : pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
204 : {
205 0 : if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
206 0 : (id->device == PCI_ANY_ID || id->device == dev->device) &&
207 0 : (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
208 0 : (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
209 0 : !((id->class ^ dev->class) & id->class_mask))
210 : return id;
211 0 : return NULL;
212 : }
213 :
214 : /* PCI slot sysfs helper code */
215 : #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
216 :
217 : extern struct kset *pci_slots_kset;
218 :
219 : struct pci_slot_attribute {
220 : struct attribute attr;
221 : ssize_t (*show)(struct pci_slot *, char *);
222 : ssize_t (*store)(struct pci_slot *, const char *, size_t);
223 : };
224 : #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
225 :
226 : enum pci_bar_type {
227 : pci_bar_unknown, /* Standard PCI BAR probe */
228 : pci_bar_io, /* An I/O port BAR */
229 : pci_bar_mem32, /* A 32-bit memory BAR */
230 : pci_bar_mem64, /* A 64-bit memory BAR */
231 : };
232 :
233 : struct device *pci_get_host_bridge_device(struct pci_dev *dev);
234 : void pci_put_host_bridge_device(struct device *dev);
235 :
236 : int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
237 : bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
238 : int crs_timeout);
239 : bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
240 : int crs_timeout);
241 : int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
242 :
243 : int pci_setup_device(struct pci_dev *dev);
244 : int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
245 : struct resource *res, unsigned int reg);
246 : void pci_configure_ari(struct pci_dev *dev);
247 : void __pci_bus_size_bridges(struct pci_bus *bus,
248 : struct list_head *realloc_head);
249 : void __pci_bus_assign_resources(const struct pci_bus *bus,
250 : struct list_head *realloc_head,
251 : struct list_head *fail_head);
252 : bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
253 :
254 : void pci_reassigndev_resource_alignment(struct pci_dev *dev);
255 : void pci_disable_bridge_window(struct pci_dev *dev);
256 : struct pci_bus *pci_bus_get(struct pci_bus *bus);
257 : void pci_bus_put(struct pci_bus *bus);
258 :
259 : /* PCIe link information from Link Capabilities 2 */
260 : #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
261 : ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
262 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
263 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
264 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
265 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
266 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
267 : PCI_SPEED_UNKNOWN)
268 :
269 : /* PCIe speed to Mb/s reduced by encoding overhead */
270 : #define PCIE_SPEED2MBS_ENC(speed) \
271 : ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
272 : (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
273 : (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
274 : (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
275 : (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
276 : (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
277 : 0)
278 :
279 : const char *pci_speed_string(enum pci_bus_speed speed);
280 : enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
281 : enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
282 : u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
283 : enum pcie_link_width *width);
284 : void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
285 : void pcie_report_downtraining(struct pci_dev *dev);
286 : void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
287 :
288 : /* Single Root I/O Virtualization */
289 : struct pci_sriov {
290 : int pos; /* Capability position */
291 : int nres; /* Number of resources */
292 : u32 cap; /* SR-IOV Capabilities */
293 : u16 ctrl; /* SR-IOV Control */
294 : u16 total_VFs; /* Total VFs associated with the PF */
295 : u16 initial_VFs; /* Initial VFs associated with the PF */
296 : u16 num_VFs; /* Number of VFs available */
297 : u16 offset; /* First VF Routing ID offset */
298 : u16 stride; /* Following VF stride */
299 : u16 vf_device; /* VF device ID */
300 : u32 pgsz; /* Page size for BAR alignment */
301 : u8 link; /* Function Dependency Link */
302 : u8 max_VF_buses; /* Max buses consumed by VFs */
303 : u16 driver_max_VFs; /* Max num VFs driver supports */
304 : struct pci_dev *dev; /* Lowest numbered PF */
305 : struct pci_dev *self; /* This PF */
306 : u32 class; /* VF device */
307 : u8 hdr_type; /* VF header type */
308 : u16 subsystem_vendor; /* VF subsystem vendor */
309 : u16 subsystem_device; /* VF subsystem device */
310 : resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
311 : bool drivers_autoprobe; /* Auto probing of VFs by driver */
312 : };
313 :
314 : #ifdef CONFIG_PCI_DOE
315 : void pci_doe_init(struct pci_dev *pdev);
316 : void pci_doe_destroy(struct pci_dev *pdev);
317 : void pci_doe_disconnected(struct pci_dev *pdev);
318 : #else
319 : static inline void pci_doe_init(struct pci_dev *pdev) { }
320 : static inline void pci_doe_destroy(struct pci_dev *pdev) { }
321 : static inline void pci_doe_disconnected(struct pci_dev *pdev) { }
322 : #endif
323 :
324 : /**
325 : * pci_dev_set_io_state - Set the new error state if possible.
326 : *
327 : * @dev: PCI device to set new error_state
328 : * @new: the state we want dev to be in
329 : *
330 : * If the device is experiencing perm_failure, it has to remain in that state.
331 : * Any other transition is allowed.
332 : *
333 : * Returns true if state has been changed to the requested state.
334 : */
335 : static inline bool pci_dev_set_io_state(struct pci_dev *dev,
336 : pci_channel_state_t new)
337 : {
338 : pci_channel_state_t old;
339 :
340 : switch (new) {
341 : case pci_channel_io_perm_failure:
342 : xchg(&dev->error_state, pci_channel_io_perm_failure);
343 : return true;
344 : case pci_channel_io_frozen:
345 : old = cmpxchg(&dev->error_state, pci_channel_io_normal,
346 : pci_channel_io_frozen);
347 : return old != pci_channel_io_perm_failure;
348 : case pci_channel_io_normal:
349 : old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
350 : pci_channel_io_normal);
351 : return old != pci_channel_io_perm_failure;
352 : default:
353 : return false;
354 : }
355 : }
356 :
357 : static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
358 : {
359 : pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
360 : pci_doe_disconnected(dev);
361 :
362 : return 0;
363 : }
364 :
365 : static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
366 : {
367 : return dev->error_state == pci_channel_io_perm_failure;
368 : }
369 :
370 : /* pci_dev priv_flags */
371 : #define PCI_DEV_ADDED 0
372 : #define PCI_DPC_RECOVERED 1
373 : #define PCI_DPC_RECOVERING 2
374 :
375 : static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
376 : {
377 0 : assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
378 : }
379 :
380 : static inline bool pci_dev_is_added(const struct pci_dev *dev)
381 : {
382 0 : return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
383 : }
384 :
385 : #ifdef CONFIG_PCIEAER
386 : #include <linux/aer.h>
387 :
388 : #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
389 :
390 : struct aer_err_info {
391 : struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
392 : int error_dev_num;
393 :
394 : unsigned int id:16;
395 :
396 : unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
397 : unsigned int __pad1:5;
398 : unsigned int multi_error_valid:1;
399 :
400 : unsigned int first_error:5;
401 : unsigned int __pad2:2;
402 : unsigned int tlp_header_valid:1;
403 :
404 : unsigned int status; /* COR/UNCOR Error Status */
405 : unsigned int mask; /* COR/UNCOR Error Mask */
406 : struct aer_header_log_regs tlp; /* TLP Header */
407 : };
408 :
409 : int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
410 : void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
411 : #endif /* CONFIG_PCIEAER */
412 :
413 : #ifdef CONFIG_PCIEPORTBUS
414 : /* Cached RCEC Endpoint Association */
415 : struct rcec_ea {
416 : u8 nextbusn;
417 : u8 lastbusn;
418 : u32 bitmap;
419 : };
420 : #endif
421 :
422 : #ifdef CONFIG_PCIE_DPC
423 : void pci_save_dpc_state(struct pci_dev *dev);
424 : void pci_restore_dpc_state(struct pci_dev *dev);
425 : void pci_dpc_init(struct pci_dev *pdev);
426 : void dpc_process_error(struct pci_dev *pdev);
427 : pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
428 : bool pci_dpc_recovered(struct pci_dev *pdev);
429 : #else
430 : static inline void pci_save_dpc_state(struct pci_dev *dev) {}
431 : static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
432 : static inline void pci_dpc_init(struct pci_dev *pdev) {}
433 : static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
434 : #endif
435 :
436 : #ifdef CONFIG_PCIEPORTBUS
437 : void pci_rcec_init(struct pci_dev *dev);
438 : void pci_rcec_exit(struct pci_dev *dev);
439 : void pcie_link_rcec(struct pci_dev *rcec);
440 : void pcie_walk_rcec(struct pci_dev *rcec,
441 : int (*cb)(struct pci_dev *, void *),
442 : void *userdata);
443 : #else
444 : static inline void pci_rcec_init(struct pci_dev *dev) {}
445 : static inline void pci_rcec_exit(struct pci_dev *dev) {}
446 : static inline void pcie_link_rcec(struct pci_dev *rcec) {}
447 : static inline void pcie_walk_rcec(struct pci_dev *rcec,
448 : int (*cb)(struct pci_dev *, void *),
449 : void *userdata) {}
450 : #endif
451 :
452 : #ifdef CONFIG_PCI_ATS
453 : /* Address Translation Service */
454 : void pci_ats_init(struct pci_dev *dev);
455 : void pci_restore_ats_state(struct pci_dev *dev);
456 : #else
457 : static inline void pci_ats_init(struct pci_dev *d) { }
458 : static inline void pci_restore_ats_state(struct pci_dev *dev) { }
459 : #endif /* CONFIG_PCI_ATS */
460 :
461 : #ifdef CONFIG_PCI_PRI
462 : void pci_pri_init(struct pci_dev *dev);
463 : void pci_restore_pri_state(struct pci_dev *pdev);
464 : #else
465 : static inline void pci_pri_init(struct pci_dev *dev) { }
466 : static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
467 : #endif
468 :
469 : #ifdef CONFIG_PCI_PASID
470 : void pci_pasid_init(struct pci_dev *dev);
471 : void pci_restore_pasid_state(struct pci_dev *pdev);
472 : #else
473 : static inline void pci_pasid_init(struct pci_dev *dev) { }
474 : static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
475 : #endif
476 :
477 : #ifdef CONFIG_PCI_IOV
478 : int pci_iov_init(struct pci_dev *dev);
479 : void pci_iov_release(struct pci_dev *dev);
480 : void pci_iov_remove(struct pci_dev *dev);
481 : void pci_iov_update_resource(struct pci_dev *dev, int resno);
482 : resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
483 : void pci_restore_iov_state(struct pci_dev *dev);
484 : int pci_iov_bus_range(struct pci_bus *bus);
485 : extern const struct attribute_group sriov_pf_dev_attr_group;
486 : extern const struct attribute_group sriov_vf_dev_attr_group;
487 : #else
488 : static inline int pci_iov_init(struct pci_dev *dev)
489 : {
490 : return -ENODEV;
491 : }
492 : static inline void pci_iov_release(struct pci_dev *dev)
493 :
494 : {
495 : }
496 : static inline void pci_iov_remove(struct pci_dev *dev)
497 : {
498 : }
499 : static inline void pci_restore_iov_state(struct pci_dev *dev)
500 : {
501 : }
502 : static inline int pci_iov_bus_range(struct pci_bus *bus)
503 : {
504 : return 0;
505 : }
506 :
507 : #endif /* CONFIG_PCI_IOV */
508 :
509 : #ifdef CONFIG_PCIE_PTM
510 : void pci_ptm_init(struct pci_dev *dev);
511 : void pci_save_ptm_state(struct pci_dev *dev);
512 : void pci_restore_ptm_state(struct pci_dev *dev);
513 : void pci_suspend_ptm(struct pci_dev *dev);
514 : void pci_resume_ptm(struct pci_dev *dev);
515 : #else
516 : static inline void pci_ptm_init(struct pci_dev *dev) { }
517 : static inline void pci_save_ptm_state(struct pci_dev *dev) { }
518 : static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
519 : static inline void pci_suspend_ptm(struct pci_dev *dev) { }
520 : static inline void pci_resume_ptm(struct pci_dev *dev) { }
521 : #endif
522 :
523 : unsigned long pci_cardbus_resource_alignment(struct resource *);
524 :
525 0 : static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
526 : struct resource *res)
527 : {
528 : #ifdef CONFIG_PCI_IOV
529 : int resno = res - dev->resource;
530 :
531 : if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
532 : return pci_sriov_resource_alignment(dev, resno);
533 : #endif
534 0 : if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
535 0 : return pci_cardbus_resource_alignment(res);
536 0 : return resource_alignment(res);
537 : }
538 :
539 : void pci_acs_init(struct pci_dev *dev);
540 : #ifdef CONFIG_PCI_QUIRKS
541 : int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
542 : int pci_dev_specific_enable_acs(struct pci_dev *dev);
543 : int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
544 : #else
545 : static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
546 : u16 acs_flags)
547 : {
548 : return -ENOTTY;
549 : }
550 : static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
551 : {
552 : return -ENOTTY;
553 : }
554 : static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
555 : {
556 : return -ENOTTY;
557 : }
558 : #endif
559 :
560 : /* PCI error reporting and recovery */
561 : pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
562 : pci_channel_state_t state,
563 : pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
564 :
565 : bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
566 : #ifdef CONFIG_PCIEASPM
567 : void pcie_aspm_init_link_state(struct pci_dev *pdev);
568 : void pcie_aspm_exit_link_state(struct pci_dev *pdev);
569 : void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
570 : #else
571 : static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
572 : static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
573 : static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
574 : #endif
575 :
576 : #ifdef CONFIG_PCIE_ECRC
577 : void pcie_set_ecrc_checking(struct pci_dev *dev);
578 : void pcie_ecrc_get_policy(char *str);
579 : #else
580 : static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
581 : static inline void pcie_ecrc_get_policy(char *str) { }
582 : #endif
583 :
584 : struct pci_dev_reset_methods {
585 : u16 vendor;
586 : u16 device;
587 : int (*reset)(struct pci_dev *dev, bool probe);
588 : };
589 :
590 : struct pci_reset_fn_method {
591 : int (*reset_fn)(struct pci_dev *pdev, bool probe);
592 : char *name;
593 : };
594 :
595 : #ifdef CONFIG_PCI_QUIRKS
596 : int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
597 : #else
598 : static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
599 : {
600 : return -ENOTTY;
601 : }
602 : #endif
603 :
604 : #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
605 : int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
606 : struct resource *res);
607 : #else
608 : static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
609 : u16 segment, struct resource *res)
610 : {
611 : return -ENODEV;
612 : }
613 : #endif
614 :
615 : int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
616 : int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
617 : static inline u64 pci_rebar_size_to_bytes(int size)
618 : {
619 0 : return 1ULL << (size + 20);
620 : }
621 :
622 : struct device_node;
623 :
624 : #ifdef CONFIG_OF
625 : int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
626 : int of_get_pci_domain_nr(struct device_node *node);
627 : int of_pci_get_max_link_speed(struct device_node *node);
628 : u32 of_pci_get_slot_power_limit(struct device_node *node,
629 : u8 *slot_power_limit_value,
630 : u8 *slot_power_limit_scale);
631 : int pci_set_of_node(struct pci_dev *dev);
632 : void pci_release_of_node(struct pci_dev *dev);
633 : void pci_set_bus_of_node(struct pci_bus *bus);
634 : void pci_release_bus_of_node(struct pci_bus *bus);
635 :
636 : int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
637 :
638 : #else
639 : static inline int
640 : of_pci_parse_bus_range(struct device_node *node, struct resource *res)
641 : {
642 : return -EINVAL;
643 : }
644 :
645 : static inline int
646 : of_get_pci_domain_nr(struct device_node *node)
647 : {
648 : return -1;
649 : }
650 :
651 : static inline int
652 : of_pci_get_max_link_speed(struct device_node *node)
653 : {
654 : return -EINVAL;
655 : }
656 :
657 : static inline u32
658 : of_pci_get_slot_power_limit(struct device_node *node,
659 : u8 *slot_power_limit_value,
660 : u8 *slot_power_limit_scale)
661 : {
662 : if (slot_power_limit_value)
663 : *slot_power_limit_value = 0;
664 : if (slot_power_limit_scale)
665 : *slot_power_limit_scale = 0;
666 : return 0;
667 : }
668 :
669 : static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
670 : static inline void pci_release_of_node(struct pci_dev *dev) { }
671 : static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
672 : static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
673 :
674 : static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
675 : {
676 : return 0;
677 : }
678 :
679 : #endif /* CONFIG_OF */
680 :
681 : #ifdef CONFIG_PCIEAER
682 : void pci_no_aer(void);
683 : void pci_aer_init(struct pci_dev *dev);
684 : void pci_aer_exit(struct pci_dev *dev);
685 : extern const struct attribute_group aer_stats_attr_group;
686 : void pci_aer_clear_fatal_status(struct pci_dev *dev);
687 : int pci_aer_clear_status(struct pci_dev *dev);
688 : int pci_aer_raw_clear_status(struct pci_dev *dev);
689 : #else
690 : static inline void pci_no_aer(void) { }
691 : static inline void pci_aer_init(struct pci_dev *d) { }
692 : static inline void pci_aer_exit(struct pci_dev *d) { }
693 : static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
694 : static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
695 : static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
696 : #endif
697 :
698 : #ifdef CONFIG_ACPI
699 : int pci_acpi_program_hp_params(struct pci_dev *dev);
700 : extern const struct attribute_group pci_dev_acpi_attr_group;
701 : void pci_set_acpi_fwnode(struct pci_dev *dev);
702 : int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
703 : bool acpi_pci_power_manageable(struct pci_dev *dev);
704 : bool acpi_pci_bridge_d3(struct pci_dev *dev);
705 : int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
706 : pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
707 : void acpi_pci_refresh_power_state(struct pci_dev *dev);
708 : int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
709 : bool acpi_pci_need_resume(struct pci_dev *dev);
710 : pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
711 : #else
712 0 : static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
713 : {
714 0 : return -ENOTTY;
715 : }
716 : static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {}
717 : static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
718 : {
719 : return -ENODEV;
720 : }
721 : static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
722 : {
723 : return false;
724 : }
725 : static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
726 : {
727 : return false;
728 : }
729 : static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
730 : {
731 : return -ENODEV;
732 : }
733 : static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
734 : {
735 : return PCI_UNKNOWN;
736 : }
737 : static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) {}
738 : static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
739 : {
740 : return -ENODEV;
741 : }
742 : static inline bool acpi_pci_need_resume(struct pci_dev *dev)
743 : {
744 : return false;
745 : }
746 : static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
747 : {
748 : return PCI_POWER_ERROR;
749 : }
750 : #endif
751 :
752 : #ifdef CONFIG_PCIEASPM
753 : extern const struct attribute_group aspm_ctrl_attr_group;
754 : #endif
755 :
756 : extern const struct attribute_group pci_dev_reset_method_attr_group;
757 :
758 : #ifdef CONFIG_X86_INTEL_MID
759 : bool pci_use_mid_pm(void);
760 : int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
761 : pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
762 : #else
763 : static inline bool pci_use_mid_pm(void)
764 : {
765 : return false;
766 : }
767 : static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
768 : {
769 : return -ENODEV;
770 : }
771 : static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
772 : {
773 : return PCI_UNKNOWN;
774 : }
775 : #endif
776 :
777 : /*
778 : * Config Address for PCI Configuration Mechanism #1
779 : *
780 : * See PCI Local Bus Specification, Revision 3.0,
781 : * Section 3.2.2.3.2, Figure 3-2, p. 50.
782 : */
783 :
784 : #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
785 : #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
786 : #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
787 :
788 : #define PCI_CONF1_BUS_MASK 0xff
789 : #define PCI_CONF1_DEV_MASK 0x1f
790 : #define PCI_CONF1_FUNC_MASK 0x7
791 : #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
792 :
793 : #define PCI_CONF1_ENABLE BIT(31)
794 : #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
795 : #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
796 : #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
797 : #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
798 :
799 : #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
800 : (PCI_CONF1_ENABLE | \
801 : PCI_CONF1_BUS(bus) | \
802 : PCI_CONF1_DEV(dev) | \
803 : PCI_CONF1_FUNC(func) | \
804 : PCI_CONF1_REG(reg))
805 :
806 : /*
807 : * Extension of PCI Config Address for accessing extended PCIe registers
808 : *
809 : * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
810 : * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
811 : * are used for specifying additional 4 high bits of PCI Express register.
812 : */
813 :
814 : #define PCI_CONF1_EXT_REG_SHIFT 16
815 : #define PCI_CONF1_EXT_REG_MASK 0xf00
816 : #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
817 :
818 : #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
819 : (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
820 : PCI_CONF1_EXT_REG(reg))
821 :
822 : #endif /* DRIVERS_PCI_H */
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