Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0
2 : /*
3 : * This file contains work-arounds for many known PCI hardware bugs.
4 : * Devices present only on certain architectures (host bridges et cetera)
5 : * should be handled in arch-specific code.
6 : *
7 : * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 : *
9 : * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 : *
11 : * Init/reset quirks for USB host controllers should be in the USB quirks
12 : * file, where their drivers can use them.
13 : */
14 :
15 : #include <linux/bitfield.h>
16 : #include <linux/types.h>
17 : #include <linux/kernel.h>
18 : #include <linux/export.h>
19 : #include <linux/pci.h>
20 : #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
21 : #include <linux/init.h>
22 : #include <linux/delay.h>
23 : #include <linux/acpi.h>
24 : #include <linux/dmi.h>
25 : #include <linux/ioport.h>
26 : #include <linux/sched.h>
27 : #include <linux/ktime.h>
28 : #include <linux/mm.h>
29 : #include <linux/nvme.h>
30 : #include <linux/platform_data/x86/apple.h>
31 : #include <linux/pm_runtime.h>
32 : #include <linux/suspend.h>
33 : #include <linux/switchtec.h>
34 : #include "pci.h"
35 :
36 0 : static ktime_t fixup_debug_start(struct pci_dev *dev,
37 : void (*fn)(struct pci_dev *dev))
38 : {
39 0 : if (initcall_debug)
40 0 : pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
41 :
42 0 : return ktime_get();
43 : }
44 :
45 0 : static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
46 : void (*fn)(struct pci_dev *dev))
47 : {
48 : ktime_t delta, rettime;
49 : unsigned long long duration;
50 :
51 0 : rettime = ktime_get();
52 0 : delta = ktime_sub(rettime, calltime);
53 0 : duration = (unsigned long long) ktime_to_ns(delta) >> 10;
54 0 : if (initcall_debug || duration > 10000)
55 0 : pci_info(dev, "%pS took %lld usecs\n", fn, duration);
56 0 : }
57 :
58 0 : static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
59 : struct pci_fixup *end)
60 : {
61 : ktime_t calltime;
62 :
63 0 : for (; f < end; f++)
64 0 : if ((f->class == (u32) (dev->class >> f->class_shift) ||
65 0 : f->class == (u32) PCI_ANY_ID) &&
66 0 : (f->vendor == dev->vendor ||
67 0 : f->vendor == (u16) PCI_ANY_ID) &&
68 0 : (f->device == dev->device ||
69 : f->device == (u16) PCI_ANY_ID)) {
70 : void (*hook)(struct pci_dev *dev);
71 : #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
72 : hook = offset_to_ptr(&f->hook_offset);
73 : #else
74 0 : hook = f->hook;
75 : #endif
76 0 : calltime = fixup_debug_start(dev, hook);
77 0 : hook(dev);
78 0 : fixup_debug_report(dev, calltime, hook);
79 : }
80 0 : }
81 :
82 : extern struct pci_fixup __start_pci_fixups_early[];
83 : extern struct pci_fixup __end_pci_fixups_early[];
84 : extern struct pci_fixup __start_pci_fixups_header[];
85 : extern struct pci_fixup __end_pci_fixups_header[];
86 : extern struct pci_fixup __start_pci_fixups_final[];
87 : extern struct pci_fixup __end_pci_fixups_final[];
88 : extern struct pci_fixup __start_pci_fixups_enable[];
89 : extern struct pci_fixup __end_pci_fixups_enable[];
90 : extern struct pci_fixup __start_pci_fixups_resume[];
91 : extern struct pci_fixup __end_pci_fixups_resume[];
92 : extern struct pci_fixup __start_pci_fixups_resume_early[];
93 : extern struct pci_fixup __end_pci_fixups_resume_early[];
94 : extern struct pci_fixup __start_pci_fixups_suspend[];
95 : extern struct pci_fixup __end_pci_fixups_suspend[];
96 : extern struct pci_fixup __start_pci_fixups_suspend_late[];
97 : extern struct pci_fixup __end_pci_fixups_suspend_late[];
98 :
99 : static bool pci_apply_fixup_final_quirks;
100 :
101 0 : void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
102 : {
103 : struct pci_fixup *start, *end;
104 :
105 0 : switch (pass) {
106 : case pci_fixup_early:
107 : start = __start_pci_fixups_early;
108 : end = __end_pci_fixups_early;
109 : break;
110 :
111 : case pci_fixup_header:
112 0 : start = __start_pci_fixups_header;
113 0 : end = __end_pci_fixups_header;
114 0 : break;
115 :
116 : case pci_fixup_final:
117 0 : if (!pci_apply_fixup_final_quirks)
118 : return;
119 : start = __start_pci_fixups_final;
120 : end = __end_pci_fixups_final;
121 : break;
122 :
123 : case pci_fixup_enable:
124 0 : start = __start_pci_fixups_enable;
125 0 : end = __end_pci_fixups_enable;
126 0 : break;
127 :
128 : case pci_fixup_resume:
129 0 : start = __start_pci_fixups_resume;
130 0 : end = __end_pci_fixups_resume;
131 0 : break;
132 :
133 : case pci_fixup_resume_early:
134 0 : start = __start_pci_fixups_resume_early;
135 0 : end = __end_pci_fixups_resume_early;
136 0 : break;
137 :
138 : case pci_fixup_suspend:
139 0 : start = __start_pci_fixups_suspend;
140 0 : end = __end_pci_fixups_suspend;
141 0 : break;
142 :
143 : case pci_fixup_suspend_late:
144 0 : start = __start_pci_fixups_suspend_late;
145 0 : end = __end_pci_fixups_suspend_late;
146 0 : break;
147 :
148 : default:
149 : /* stupid compiler warning, you would think with an enum... */
150 : return;
151 : }
152 0 : pci_do_fixups(dev, start, end);
153 : }
154 : EXPORT_SYMBOL(pci_fixup_device);
155 :
156 1 : static int __init pci_apply_final_quirks(void)
157 : {
158 1 : struct pci_dev *dev = NULL;
159 1 : u8 cls = 0;
160 : u8 tmp;
161 :
162 1 : if (pci_cache_line_size)
163 0 : pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
164 :
165 1 : pci_apply_fixup_final_quirks = true;
166 2 : for_each_pci_dev(dev) {
167 0 : pci_fixup_device(pci_fixup_final, dev);
168 : /*
169 : * If arch hasn't set it explicitly yet, use the CLS
170 : * value shared by all PCI devices. If there's a
171 : * mismatch, fall back to the default value.
172 : */
173 0 : if (!pci_cache_line_size) {
174 0 : pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
175 0 : if (!cls)
176 0 : cls = tmp;
177 0 : if (!tmp || cls == tmp)
178 0 : continue;
179 :
180 0 : pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
181 : cls << 2, tmp << 2,
182 : pci_dfl_cache_line_size << 2);
183 0 : pci_cache_line_size = pci_dfl_cache_line_size;
184 : }
185 : }
186 :
187 1 : if (!pci_cache_line_size) {
188 1 : pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
189 : pci_dfl_cache_line_size << 2);
190 1 : pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
191 : }
192 :
193 1 : return 0;
194 : }
195 : fs_initcall_sync(pci_apply_final_quirks);
196 :
197 : /*
198 : * Decoding should be disabled for a PCI device during BAR sizing to avoid
199 : * conflict. But doing so may cause problems on host bridge and perhaps other
200 : * key system devices. For devices that need to have mmio decoding always-on,
201 : * we need to set the dev->mmio_always_on bit.
202 : */
203 0 : static void quirk_mmio_always_on(struct pci_dev *dev)
204 : {
205 0 : dev->mmio_always_on = 1;
206 0 : }
207 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
208 : PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
209 :
210 : /*
211 : * The Mellanox Tavor device gives false positive parity errors. Disable
212 : * parity error reporting.
213 : */
214 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity);
215 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity);
216 :
217 : /*
218 : * Deal with broken BIOSes that neglect to enable passive release,
219 : * which can cause problems in combination with the 82441FX/PPro MTRRs
220 : */
221 0 : static void quirk_passive_release(struct pci_dev *dev)
222 : {
223 0 : struct pci_dev *d = NULL;
224 : unsigned char dlc;
225 :
226 : /*
227 : * We have to make sure a particular bit is set in the PIIX3
228 : * ISA bridge, so we have to go out and find it.
229 : */
230 0 : while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
231 0 : pci_read_config_byte(d, 0x82, &dlc);
232 0 : if (!(dlc & 1<<1)) {
233 0 : pci_info(d, "PIIX3: Enabling Passive Release\n");
234 0 : dlc |= 1<<1;
235 0 : pci_write_config_byte(d, 0x82, dlc);
236 : }
237 : }
238 0 : }
239 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
240 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
241 :
242 : #ifdef CONFIG_X86_32
243 : /*
244 : * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
245 : * workaround but VIA don't answer queries. If you happen to have good
246 : * contacts at VIA ask them for me please -- Alan
247 : *
248 : * This appears to be BIOS not version dependent. So presumably there is a
249 : * chipset level fix.
250 : */
251 : static void quirk_isa_dma_hangs(struct pci_dev *dev)
252 : {
253 : if (!isa_dma_bridge_buggy) {
254 : isa_dma_bridge_buggy = 1;
255 : pci_info(dev, "Activating ISA DMA hang workarounds\n");
256 : }
257 : }
258 : /*
259 : * It's not totally clear which chipsets are the problematic ones. We know
260 : * 82C586 and 82C596 variants are affected.
261 : */
262 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
263 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
264 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
265 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
266 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
267 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
268 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
269 : #endif
270 :
271 : /*
272 : * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
273 : * for some HT machines to use C4 w/o hanging.
274 : */
275 0 : static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
276 : {
277 : u32 pmbase;
278 : u16 pm1a;
279 :
280 0 : pci_read_config_dword(dev, 0x40, &pmbase);
281 0 : pmbase = pmbase & 0xff80;
282 0 : pm1a = inw(pmbase);
283 :
284 0 : if (pm1a & 0x10) {
285 0 : pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
286 0 : outw(0x10, pmbase);
287 : }
288 0 : }
289 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
290 :
291 : /* Chipsets where PCI->PCI transfers vanish or hang */
292 0 : static void quirk_nopcipci(struct pci_dev *dev)
293 : {
294 0 : if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
295 0 : pci_info(dev, "Disabling direct PCI/PCI transfers\n");
296 0 : pci_pci_problems |= PCIPCI_FAIL;
297 : }
298 0 : }
299 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
300 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
301 :
302 0 : static void quirk_nopciamd(struct pci_dev *dev)
303 : {
304 : u8 rev;
305 0 : pci_read_config_byte(dev, 0x08, &rev);
306 0 : if (rev == 0x13) {
307 : /* Erratum 24 */
308 0 : pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
309 0 : pci_pci_problems |= PCIAGP_FAIL;
310 : }
311 0 : }
312 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
313 :
314 : /* Triton requires workarounds to be used by the drivers */
315 0 : static void quirk_triton(struct pci_dev *dev)
316 : {
317 0 : if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
318 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
319 0 : pci_pci_problems |= PCIPCI_TRITON;
320 : }
321 0 : }
322 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
323 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
324 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
325 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
326 :
327 : /*
328 : * VIA Apollo KT133 needs PCI latency patch
329 : * Made according to a Windows driver-based patch by George E. Breese;
330 : * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
331 : * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
332 : * which Mr Breese based his work.
333 : *
334 : * Updated based on further information from the site and also on
335 : * information provided by VIA
336 : */
337 0 : static void quirk_vialatency(struct pci_dev *dev)
338 : {
339 : struct pci_dev *p;
340 : u8 busarb;
341 :
342 : /*
343 : * Ok, we have a potential problem chipset here. Now see if we have
344 : * a buggy southbridge.
345 : */
346 0 : p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
347 0 : if (p != NULL) {
348 :
349 : /*
350 : * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
351 : * thanks Dan Hollis.
352 : * Check for buggy part revisions
353 : */
354 0 : if (p->revision < 0x40 || p->revision > 0x42)
355 : goto exit;
356 : } else {
357 0 : p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
358 0 : if (p == NULL) /* No problem parts */
359 : goto exit;
360 :
361 : /* Check for buggy part revisions */
362 0 : if (p->revision < 0x10 || p->revision > 0x12)
363 : goto exit;
364 : }
365 :
366 : /*
367 : * Ok we have the problem. Now set the PCI master grant to occur
368 : * every master grant. The apparent bug is that under high PCI load
369 : * (quite common in Linux of course) you can get data loss when the
370 : * CPU is held off the bus for 3 bus master requests. This happens
371 : * to include the IDE controllers....
372 : *
373 : * VIA only apply this fix when an SB Live! is present but under
374 : * both Linux and Windows this isn't enough, and we have seen
375 : * corruption without SB Live! but with things like 3 UDMA IDE
376 : * controllers. So we ignore that bit of the VIA recommendation..
377 : */
378 0 : pci_read_config_byte(dev, 0x76, &busarb);
379 :
380 : /*
381 : * Set bit 4 and bit 5 of byte 76 to 0x01
382 : * "Master priority rotation on every PCI master grant"
383 : */
384 0 : busarb &= ~(1<<5);
385 0 : busarb |= (1<<4);
386 0 : pci_write_config_byte(dev, 0x76, busarb);
387 0 : pci_info(dev, "Applying VIA southbridge workaround\n");
388 : exit:
389 0 : pci_dev_put(p);
390 0 : }
391 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
392 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
393 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
394 : /* Must restore this on a resume from RAM */
395 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
396 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
397 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
398 :
399 : /* VIA Apollo VP3 needs ETBF on BT848/878 */
400 0 : static void quirk_viaetbf(struct pci_dev *dev)
401 : {
402 0 : if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
403 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
404 0 : pci_pci_problems |= PCIPCI_VIAETBF;
405 : }
406 0 : }
407 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
408 :
409 0 : static void quirk_vsfx(struct pci_dev *dev)
410 : {
411 0 : if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
412 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
413 0 : pci_pci_problems |= PCIPCI_VSFX;
414 : }
415 0 : }
416 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
417 :
418 : /*
419 : * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
420 : * space. Latency must be set to 0xA and Triton workaround applied too.
421 : * [Info kindly provided by ALi]
422 : */
423 0 : static void quirk_alimagik(struct pci_dev *dev)
424 : {
425 0 : if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
426 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
427 0 : pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
428 : }
429 0 : }
430 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
431 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
432 :
433 : /* Natoma has some interesting boundary conditions with Zoran stuff at least */
434 0 : static void quirk_natoma(struct pci_dev *dev)
435 : {
436 0 : if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
437 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
438 0 : pci_pci_problems |= PCIPCI_NATOMA;
439 : }
440 0 : }
441 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
442 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
443 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
444 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
445 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
446 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
447 :
448 : /*
449 : * This chip can cause PCI parity errors if config register 0xA0 is read
450 : * while DMAs are occurring.
451 : */
452 0 : static void quirk_citrine(struct pci_dev *dev)
453 : {
454 0 : dev->cfg_size = 0xA0;
455 0 : }
456 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
457 :
458 : /*
459 : * This chip can cause bus lockups if config addresses above 0x600
460 : * are read or written.
461 : */
462 0 : static void quirk_nfp6000(struct pci_dev *dev)
463 : {
464 0 : dev->cfg_size = 0x600;
465 0 : }
466 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
467 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
468 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
469 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
470 :
471 : /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
472 0 : static void quirk_extend_bar_to_page(struct pci_dev *dev)
473 : {
474 : int i;
475 :
476 0 : for (i = 0; i < PCI_STD_NUM_BARS; i++) {
477 0 : struct resource *r = &dev->resource[i];
478 :
479 0 : if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
480 0 : r->end = PAGE_SIZE - 1;
481 0 : r->start = 0;
482 0 : r->flags |= IORESOURCE_UNSET;
483 0 : pci_info(dev, "expanded BAR %d to page size: %pR\n",
484 : i, r);
485 : }
486 : }
487 0 : }
488 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
489 :
490 : /*
491 : * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
492 : * If it's needed, re-allocate the region.
493 : */
494 0 : static void quirk_s3_64M(struct pci_dev *dev)
495 : {
496 0 : struct resource *r = &dev->resource[0];
497 :
498 0 : if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
499 0 : r->flags |= IORESOURCE_UNSET;
500 0 : r->start = 0;
501 0 : r->end = 0x3ffffff;
502 : }
503 0 : }
504 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
505 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
506 :
507 0 : static void quirk_io(struct pci_dev *dev, int pos, unsigned int size,
508 : const char *name)
509 : {
510 : u32 region;
511 : struct pci_bus_region bus_region;
512 0 : struct resource *res = dev->resource + pos;
513 :
514 0 : pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
515 :
516 0 : if (!region)
517 0 : return;
518 :
519 0 : res->name = pci_name(dev);
520 0 : res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
521 0 : res->flags |=
522 : (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
523 0 : region &= ~(size - 1);
524 :
525 : /* Convert from PCI bus to resource space */
526 0 : bus_region.start = region;
527 0 : bus_region.end = region + size - 1;
528 0 : pcibios_bus_to_resource(dev->bus, res, &bus_region);
529 :
530 0 : pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
531 : name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
532 : }
533 :
534 : /*
535 : * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
536 : * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
537 : * BAR0 should be 8 bytes; instead, it may be set to something like 8k
538 : * (which conflicts w/ BAR1's memory range).
539 : *
540 : * CS553x's ISA PCI BARs may also be read-only (ref:
541 : * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
542 : */
543 0 : static void quirk_cs5536_vsa(struct pci_dev *dev)
544 : {
545 : static char *name = "CS5536 ISA bridge";
546 :
547 0 : if (pci_resource_len(dev, 0) != 8) {
548 0 : quirk_io(dev, 0, 8, name); /* SMB */
549 0 : quirk_io(dev, 1, 256, name); /* GPIO */
550 0 : quirk_io(dev, 2, 64, name); /* MFGPT */
551 0 : pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
552 : name);
553 : }
554 0 : }
555 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
556 :
557 0 : static void quirk_io_region(struct pci_dev *dev, int port,
558 : unsigned int size, int nr, const char *name)
559 : {
560 : u16 region;
561 : struct pci_bus_region bus_region;
562 0 : struct resource *res = dev->resource + nr;
563 :
564 0 : pci_read_config_word(dev, port, ®ion);
565 0 : region &= ~(size - 1);
566 :
567 0 : if (!region)
568 0 : return;
569 :
570 0 : res->name = pci_name(dev);
571 0 : res->flags = IORESOURCE_IO;
572 :
573 : /* Convert from PCI bus to resource space */
574 0 : bus_region.start = region;
575 0 : bus_region.end = region + size - 1;
576 0 : pcibios_bus_to_resource(dev->bus, res, &bus_region);
577 :
578 0 : if (!pci_claim_resource(dev, nr))
579 0 : pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
580 : }
581 :
582 : /*
583 : * ATI Northbridge setups MCE the processor if you even read somewhere
584 : * between 0x3b0->0x3bb or read 0x3d3
585 : */
586 0 : static void quirk_ati_exploding_mce(struct pci_dev *dev)
587 : {
588 0 : pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
589 : /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
590 0 : request_region(0x3b0, 0x0C, "RadeonIGP");
591 0 : request_region(0x3d3, 0x01, "RadeonIGP");
592 0 : }
593 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
594 :
595 : /*
596 : * In the AMD NL platform, this device ([1022:7912]) has a class code of
597 : * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
598 : * claim it.
599 : *
600 : * But the dwc3 driver is a more specific driver for this device, and we'd
601 : * prefer to use it instead of xhci. To prevent xhci from claiming the
602 : * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
603 : * defines as "USB device (not host controller)". The dwc3 driver can then
604 : * claim it based on its Vendor and Device ID.
605 : */
606 0 : static void quirk_amd_nl_class(struct pci_dev *pdev)
607 : {
608 0 : u32 class = pdev->class;
609 :
610 : /* Use "USB Device (not host controller)" class */
611 0 : pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
612 0 : pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
613 : class, pdev->class);
614 0 : }
615 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
616 : quirk_amd_nl_class);
617 :
618 : /*
619 : * Synopsys USB 3.x host HAPS platform has a class code of
620 : * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
621 : * devices should use dwc3-haps driver. Change these devices' class code to
622 : * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
623 : * them.
624 : */
625 0 : static void quirk_synopsys_haps(struct pci_dev *pdev)
626 : {
627 0 : u32 class = pdev->class;
628 :
629 0 : switch (pdev->device) {
630 : case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
631 : case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
632 : case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
633 0 : pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
634 0 : pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
635 : class, pdev->class);
636 0 : break;
637 : }
638 0 : }
639 : DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
640 : PCI_CLASS_SERIAL_USB_XHCI, 0,
641 : quirk_synopsys_haps);
642 :
643 : /*
644 : * Let's make the southbridge information explicit instead of having to
645 : * worry about people probing the ACPI areas, for example.. (Yes, it
646 : * happens, and if you read the wrong ACPI register it will put the machine
647 : * to sleep with no way of waking it up again. Bummer).
648 : *
649 : * ALI M7101: Two IO regions pointed to by words at
650 : * 0xE0 (64 bytes of ACPI registers)
651 : * 0xE2 (32 bytes of SMB registers)
652 : */
653 0 : static void quirk_ali7101_acpi(struct pci_dev *dev)
654 : {
655 0 : quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
656 0 : quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
657 0 : }
658 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
659 :
660 0 : static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
661 : {
662 : u32 devres;
663 : u32 mask, size, base;
664 :
665 0 : pci_read_config_dword(dev, port, &devres);
666 0 : if ((devres & enable) != enable)
667 0 : return;
668 0 : mask = (devres >> 16) & 15;
669 0 : base = devres & 0xffff;
670 0 : size = 16;
671 : for (;;) {
672 0 : unsigned int bit = size >> 1;
673 0 : if ((bit & mask) == bit)
674 : break;
675 : size = bit;
676 : }
677 : /*
678 : * For now we only print it out. Eventually we'll want to
679 : * reserve it (at least if it's in the 0x1000+ range), but
680 : * let's get enough confirmation reports first.
681 : */
682 0 : base &= -size;
683 0 : pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
684 : }
685 :
686 0 : static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
687 : {
688 : u32 devres;
689 : u32 mask, size, base;
690 :
691 0 : pci_read_config_dword(dev, port, &devres);
692 0 : if ((devres & enable) != enable)
693 0 : return;
694 0 : base = devres & 0xffff0000;
695 0 : mask = (devres & 0x3f) << 16;
696 0 : size = 128 << 16;
697 : for (;;) {
698 0 : unsigned int bit = size >> 1;
699 0 : if ((bit & mask) == bit)
700 : break;
701 : size = bit;
702 : }
703 :
704 : /*
705 : * For now we only print it out. Eventually we'll want to
706 : * reserve it, but let's get enough confirmation reports first.
707 : */
708 0 : base &= -size;
709 0 : pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
710 : }
711 :
712 : /*
713 : * PIIX4 ACPI: Two IO regions pointed to by longwords at
714 : * 0x40 (64 bytes of ACPI registers)
715 : * 0x90 (16 bytes of SMB registers)
716 : * and a few strange programmable PIIX4 device resources.
717 : */
718 0 : static void quirk_piix4_acpi(struct pci_dev *dev)
719 : {
720 : u32 res_a;
721 :
722 0 : quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
723 0 : quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
724 :
725 : /* Device resource A has enables for some of the other ones */
726 0 : pci_read_config_dword(dev, 0x5c, &res_a);
727 :
728 0 : piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
729 0 : piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
730 :
731 : /* Device resource D is just bitfields for static resources */
732 :
733 : /* Device 12 enabled? */
734 0 : if (res_a & (1 << 29)) {
735 0 : piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
736 0 : piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
737 : }
738 : /* Device 13 enabled? */
739 0 : if (res_a & (1 << 30)) {
740 0 : piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
741 0 : piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
742 : }
743 0 : piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
744 0 : piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
745 0 : }
746 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
747 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
748 :
749 : #define ICH_PMBASE 0x40
750 : #define ICH_ACPI_CNTL 0x44
751 : #define ICH4_ACPI_EN 0x10
752 : #define ICH6_ACPI_EN 0x80
753 : #define ICH4_GPIOBASE 0x58
754 : #define ICH4_GPIO_CNTL 0x5c
755 : #define ICH4_GPIO_EN 0x10
756 : #define ICH6_GPIOBASE 0x48
757 : #define ICH6_GPIO_CNTL 0x4c
758 : #define ICH6_GPIO_EN 0x10
759 :
760 : /*
761 : * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
762 : * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
763 : * 0x58 (64 bytes of GPIO I/O space)
764 : */
765 0 : static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
766 : {
767 : u8 enable;
768 :
769 : /*
770 : * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
771 : * with low legacy (and fixed) ports. We don't know the decoding
772 : * priority and can't tell whether the legacy device or the one created
773 : * here is really at that address. This happens on boards with broken
774 : * BIOSes.
775 : */
776 0 : pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
777 0 : if (enable & ICH4_ACPI_EN)
778 0 : quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
779 : "ICH4 ACPI/GPIO/TCO");
780 :
781 0 : pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
782 0 : if (enable & ICH4_GPIO_EN)
783 0 : quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
784 : "ICH4 GPIO");
785 0 : }
786 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
787 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
788 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
789 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
790 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
791 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
792 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
793 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
794 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
795 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
796 :
797 0 : static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
798 : {
799 : u8 enable;
800 :
801 0 : pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
802 0 : if (enable & ICH6_ACPI_EN)
803 0 : quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
804 : "ICH6 ACPI/GPIO/TCO");
805 :
806 0 : pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
807 0 : if (enable & ICH6_GPIO_EN)
808 0 : quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
809 : "ICH6 GPIO");
810 0 : }
811 :
812 0 : static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg,
813 : const char *name, int dynsize)
814 : {
815 : u32 val;
816 : u32 size, base;
817 :
818 0 : pci_read_config_dword(dev, reg, &val);
819 :
820 : /* Enabled? */
821 0 : if (!(val & 1))
822 0 : return;
823 0 : base = val & 0xfffc;
824 0 : if (dynsize) {
825 : /*
826 : * This is not correct. It is 16, 32 or 64 bytes depending on
827 : * register D31:F0:ADh bits 5:4.
828 : *
829 : * But this gets us at least _part_ of it.
830 : */
831 : size = 16;
832 : } else {
833 0 : size = 128;
834 : }
835 0 : base &= ~(size-1);
836 :
837 : /*
838 : * Just print it out for now. We should reserve it after more
839 : * debugging.
840 : */
841 0 : pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
842 : }
843 :
844 0 : static void quirk_ich6_lpc(struct pci_dev *dev)
845 : {
846 : /* Shared ACPI/GPIO decode with all ICH6+ */
847 0 : ich6_lpc_acpi_gpio(dev);
848 :
849 : /* ICH6-specific generic IO decode */
850 0 : ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
851 0 : ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
852 0 : }
853 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
854 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
855 :
856 0 : static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg,
857 : const char *name)
858 : {
859 : u32 val;
860 : u32 mask, base;
861 :
862 0 : pci_read_config_dword(dev, reg, &val);
863 :
864 : /* Enabled? */
865 0 : if (!(val & 1))
866 0 : return;
867 :
868 : /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
869 0 : base = val & 0xfffc;
870 0 : mask = (val >> 16) & 0xfc;
871 0 : mask |= 3;
872 :
873 : /*
874 : * Just print it out for now. We should reserve it after more
875 : * debugging.
876 : */
877 0 : pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
878 : }
879 :
880 : /* ICH7-10 has the same common LPC generic IO decode registers */
881 0 : static void quirk_ich7_lpc(struct pci_dev *dev)
882 : {
883 : /* We share the common ACPI/GPIO decode with ICH6 */
884 0 : ich6_lpc_acpi_gpio(dev);
885 :
886 : /* And have 4 ICH7+ generic decodes */
887 0 : ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
888 0 : ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
889 0 : ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
890 0 : ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
891 0 : }
892 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
893 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
894 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
895 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
896 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
897 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
898 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
899 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
900 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
901 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
902 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
903 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
904 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
905 :
906 : /*
907 : * VIA ACPI: One IO region pointed to by longword at
908 : * 0x48 or 0x20 (256 bytes of ACPI registers)
909 : */
910 0 : static void quirk_vt82c586_acpi(struct pci_dev *dev)
911 : {
912 0 : if (dev->revision & 0x10)
913 0 : quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
914 : "vt82c586 ACPI");
915 0 : }
916 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
917 :
918 : /*
919 : * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
920 : * 0x48 (256 bytes of ACPI registers)
921 : * 0x70 (128 bytes of hardware monitoring register)
922 : * 0x90 (16 bytes of SMB registers)
923 : */
924 0 : static void quirk_vt82c686_acpi(struct pci_dev *dev)
925 : {
926 0 : quirk_vt82c586_acpi(dev);
927 :
928 0 : quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
929 : "vt82c686 HW-mon");
930 :
931 0 : quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
932 0 : }
933 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
934 :
935 : /*
936 : * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
937 : * 0x88 (128 bytes of power management registers)
938 : * 0xd0 (16 bytes of SMB registers)
939 : */
940 0 : static void quirk_vt8235_acpi(struct pci_dev *dev)
941 : {
942 0 : quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
943 0 : quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
944 0 : }
945 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
946 :
947 : /*
948 : * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
949 : * back-to-back: Disable fast back-to-back on the secondary bus segment
950 : */
951 0 : static void quirk_xio2000a(struct pci_dev *dev)
952 : {
953 : struct pci_dev *pdev;
954 : u16 command;
955 :
956 0 : pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
957 0 : list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
958 0 : pci_read_config_word(pdev, PCI_COMMAND, &command);
959 0 : if (command & PCI_COMMAND_FAST_BACK)
960 0 : pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
961 : }
962 0 : }
963 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
964 : quirk_xio2000a);
965 :
966 : #ifdef CONFIG_X86_IO_APIC
967 :
968 : #include <asm/io_apic.h>
969 :
970 : /*
971 : * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
972 : * devices to the external APIC.
973 : *
974 : * TODO: When we have device-specific interrupt routers, this code will go
975 : * away from quirks.
976 : */
977 : static void quirk_via_ioapic(struct pci_dev *dev)
978 : {
979 : u8 tmp;
980 :
981 : if (nr_ioapics < 1)
982 : tmp = 0; /* nothing routed to external APIC */
983 : else
984 : tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
985 :
986 : pci_info(dev, "%s VIA external APIC routing\n",
987 : tmp ? "Enabling" : "Disabling");
988 :
989 : /* Offset 0x58: External APIC IRQ output control */
990 : pci_write_config_byte(dev, 0x58, tmp);
991 : }
992 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
993 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
994 :
995 : /*
996 : * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
997 : * This leads to doubled level interrupt rates.
998 : * Set this bit to get rid of cycle wastage.
999 : * Otherwise uncritical.
1000 : */
1001 : static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1002 : {
1003 : u8 misc_control2;
1004 : #define BYPASS_APIC_DEASSERT 8
1005 :
1006 : pci_read_config_byte(dev, 0x5B, &misc_control2);
1007 : if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1008 : pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1009 : pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1010 : }
1011 : }
1012 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1013 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1014 :
1015 : /*
1016 : * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1017 : * We check all revs >= B0 (yet not in the pre production!) as the bug
1018 : * is currently marked NoFix
1019 : *
1020 : * We have multiple reports of hangs with this chipset that went away with
1021 : * noapic specified. For the moment we assume it's the erratum. We may be wrong
1022 : * of course. However the advice is demonstrably good even if so.
1023 : */
1024 : static void quirk_amd_ioapic(struct pci_dev *dev)
1025 : {
1026 : if (dev->revision >= 0x02) {
1027 : pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1028 : pci_warn(dev, " : booting with the \"noapic\" option\n");
1029 : }
1030 : }
1031 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1032 : #endif /* CONFIG_X86_IO_APIC */
1033 :
1034 : #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1035 :
1036 : static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1037 : {
1038 : /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1039 : if (dev->subsystem_device == 0xa118)
1040 : dev->sriov->link = dev->devfn;
1041 : }
1042 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1043 : #endif
1044 :
1045 : /*
1046 : * Some settings of MMRBC can lead to data corruption so block changes.
1047 : * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1048 : */
1049 0 : static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1050 : {
1051 0 : if (dev->subordinate && dev->revision <= 0x12) {
1052 0 : pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1053 : dev->revision);
1054 0 : dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1055 : }
1056 0 : }
1057 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1058 :
1059 : /*
1060 : * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1061 : * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1062 : * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1063 : * of the ACPI SCI interrupt is only done for convenience.
1064 : * -jgarzik
1065 : */
1066 0 : static void quirk_via_acpi(struct pci_dev *d)
1067 : {
1068 : u8 irq;
1069 :
1070 : /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1071 0 : pci_read_config_byte(d, 0x42, &irq);
1072 0 : irq &= 0xf;
1073 0 : if (irq && (irq != 2))
1074 0 : d->irq = irq;
1075 0 : }
1076 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1077 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1078 :
1079 : /* VIA bridges which have VLink */
1080 : static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1081 :
1082 0 : static void quirk_via_bridge(struct pci_dev *dev)
1083 : {
1084 : /* See what bridge we have and find the device ranges */
1085 0 : switch (dev->device) {
1086 : case PCI_DEVICE_ID_VIA_82C686:
1087 : /*
1088 : * The VT82C686 is special; it attaches to PCI and can have
1089 : * any device number. All its subdevices are functions of
1090 : * that single device.
1091 : */
1092 0 : via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1093 0 : via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1094 0 : break;
1095 : case PCI_DEVICE_ID_VIA_8237:
1096 : case PCI_DEVICE_ID_VIA_8237A:
1097 0 : via_vlink_dev_lo = 15;
1098 0 : break;
1099 : case PCI_DEVICE_ID_VIA_8235:
1100 0 : via_vlink_dev_lo = 16;
1101 0 : break;
1102 : case PCI_DEVICE_ID_VIA_8231:
1103 : case PCI_DEVICE_ID_VIA_8233_0:
1104 : case PCI_DEVICE_ID_VIA_8233A:
1105 : case PCI_DEVICE_ID_VIA_8233C_0:
1106 0 : via_vlink_dev_lo = 17;
1107 0 : break;
1108 : }
1109 0 : }
1110 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1111 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1112 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1113 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1114 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1115 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1116 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1117 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1118 :
1119 : /*
1120 : * quirk_via_vlink - VIA VLink IRQ number update
1121 : * @dev: PCI device
1122 : *
1123 : * If the device we are dealing with is on a PIC IRQ we need to ensure that
1124 : * the IRQ line register which usually is not relevant for PCI cards, is
1125 : * actually written so that interrupts get sent to the right place.
1126 : *
1127 : * We only do this on systems where a VIA south bridge was detected, and
1128 : * only for VIA devices on the motherboard (see quirk_via_bridge above).
1129 : */
1130 0 : static void quirk_via_vlink(struct pci_dev *dev)
1131 : {
1132 : u8 irq, new_irq;
1133 :
1134 : /* Check if we have VLink at all */
1135 0 : if (via_vlink_dev_lo == -1)
1136 0 : return;
1137 :
1138 0 : new_irq = dev->irq;
1139 :
1140 : /* Don't quirk interrupts outside the legacy IRQ range */
1141 0 : if (!new_irq || new_irq > 15)
1142 : return;
1143 :
1144 : /* Internal device ? */
1145 0 : if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1146 0 : PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1147 : return;
1148 :
1149 : /*
1150 : * This is an internal VLink device on a PIC interrupt. The BIOS
1151 : * ought to have set this but may not have, so we redo it.
1152 : */
1153 0 : pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1154 0 : if (new_irq != irq) {
1155 0 : pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1156 : irq, new_irq);
1157 0 : udelay(15); /* unknown if delay really needed */
1158 0 : pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1159 : }
1160 : }
1161 : DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1162 :
1163 : /*
1164 : * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1165 : * of VT82C597 for backward compatibility. We need to switch it off to be
1166 : * able to recognize the real type of the chip.
1167 : */
1168 0 : static void quirk_vt82c598_id(struct pci_dev *dev)
1169 : {
1170 0 : pci_write_config_byte(dev, 0xfc, 0);
1171 0 : pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1172 0 : }
1173 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1174 :
1175 : /*
1176 : * CardBus controllers have a legacy base address that enables them to
1177 : * respond as i82365 pcmcia controllers. We don't want them to do this
1178 : * even if the Linux CardBus driver is not loaded, because the Linux i82365
1179 : * driver does not (and should not) handle CardBus.
1180 : */
1181 0 : static void quirk_cardbus_legacy(struct pci_dev *dev)
1182 : {
1183 0 : pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1184 0 : }
1185 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1186 : PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1187 : DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1188 : PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1189 :
1190 : /*
1191 : * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1192 : * what the designers were smoking but let's not inhale...
1193 : *
1194 : * To be fair to AMD, it follows the spec by default, it's BIOS people who
1195 : * turn it off!
1196 : */
1197 0 : static void quirk_amd_ordering(struct pci_dev *dev)
1198 : {
1199 : u32 pcic;
1200 0 : pci_read_config_dword(dev, 0x4C, &pcic);
1201 0 : if ((pcic & 6) != 6) {
1202 0 : pcic |= 6;
1203 0 : pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1204 0 : pci_write_config_dword(dev, 0x4C, pcic);
1205 0 : pci_read_config_dword(dev, 0x84, &pcic);
1206 0 : pcic |= (1 << 23); /* Required in this mode */
1207 0 : pci_write_config_dword(dev, 0x84, pcic);
1208 : }
1209 0 : }
1210 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1211 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1212 :
1213 : /*
1214 : * DreamWorks-provided workaround for Dunord I-3000 problem
1215 : *
1216 : * This card decodes and responds to addresses not apparently assigned to
1217 : * it. We force a larger allocation to ensure that nothing gets put too
1218 : * close to it.
1219 : */
1220 0 : static void quirk_dunord(struct pci_dev *dev)
1221 : {
1222 0 : struct resource *r = &dev->resource[1];
1223 :
1224 0 : r->flags |= IORESOURCE_UNSET;
1225 0 : r->start = 0;
1226 0 : r->end = 0xffffff;
1227 0 : }
1228 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1229 :
1230 : /*
1231 : * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1232 : * decoding (transparent), and does indicate this in the ProgIf.
1233 : * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1234 : */
1235 0 : static void quirk_transparent_bridge(struct pci_dev *dev)
1236 : {
1237 0 : dev->transparent = 1;
1238 0 : }
1239 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1240 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1241 :
1242 : /*
1243 : * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1244 : * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1245 : * found at http://www.national.com/analog for info on what these bits do.
1246 : * <christer@weinigel.se>
1247 : */
1248 0 : static void quirk_mediagx_master(struct pci_dev *dev)
1249 : {
1250 : u8 reg;
1251 :
1252 0 : pci_read_config_byte(dev, 0x41, ®);
1253 0 : if (reg & 2) {
1254 0 : reg &= ~2;
1255 0 : pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1256 : reg);
1257 0 : pci_write_config_byte(dev, 0x41, reg);
1258 : }
1259 0 : }
1260 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1261 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1262 :
1263 : /*
1264 : * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1265 : * in the odd case it is not the results are corruption hence the presence
1266 : * of a Linux check.
1267 : */
1268 0 : static void quirk_disable_pxb(struct pci_dev *pdev)
1269 : {
1270 : u16 config;
1271 :
1272 0 : if (pdev->revision != 0x04) /* Only C0 requires this */
1273 0 : return;
1274 0 : pci_read_config_word(pdev, 0x40, &config);
1275 0 : if (config & (1<<6)) {
1276 0 : config &= ~(1<<6);
1277 0 : pci_write_config_word(pdev, 0x40, config);
1278 0 : pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1279 : }
1280 : }
1281 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1282 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1283 :
1284 0 : static void quirk_amd_ide_mode(struct pci_dev *pdev)
1285 : {
1286 : /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1287 : u8 tmp;
1288 :
1289 0 : pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1290 0 : if (tmp == 0x01) {
1291 0 : pci_read_config_byte(pdev, 0x40, &tmp);
1292 0 : pci_write_config_byte(pdev, 0x40, tmp|1);
1293 0 : pci_write_config_byte(pdev, 0x9, 1);
1294 0 : pci_write_config_byte(pdev, 0xa, 6);
1295 0 : pci_write_config_byte(pdev, 0x40, tmp);
1296 :
1297 0 : pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1298 0 : pci_info(pdev, "set SATA to AHCI mode\n");
1299 : }
1300 0 : }
1301 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1302 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1303 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1304 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1305 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1306 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1307 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1308 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1309 :
1310 : /* Serverworks CSB5 IDE does not fully support native mode */
1311 0 : static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1312 : {
1313 : u8 prog;
1314 0 : pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1315 0 : if (prog & 5) {
1316 0 : prog &= ~5;
1317 0 : pdev->class &= ~5;
1318 0 : pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1319 : /* PCI layer will sort out resources */
1320 : }
1321 0 : }
1322 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1323 :
1324 : /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1325 0 : static void quirk_ide_samemode(struct pci_dev *pdev)
1326 : {
1327 : u8 prog;
1328 :
1329 0 : pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1330 :
1331 0 : if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1332 0 : pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1333 0 : prog &= ~5;
1334 0 : pdev->class &= ~5;
1335 0 : pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1336 : }
1337 0 : }
1338 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1339 :
1340 : /* Some ATA devices break if put into D3 */
1341 0 : static void quirk_no_ata_d3(struct pci_dev *pdev)
1342 : {
1343 0 : pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1344 0 : }
1345 : /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1346 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1347 : PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1348 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1349 : PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1350 : /* ALi loses some register settings that we cannot then restore */
1351 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1352 : PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1353 : /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1354 : occur when mode detecting */
1355 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1356 : PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1357 :
1358 : /*
1359 : * This was originally an Alpha-specific thing, but it really fits here.
1360 : * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1361 : */
1362 0 : static void quirk_eisa_bridge(struct pci_dev *dev)
1363 : {
1364 0 : dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1365 0 : }
1366 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1367 :
1368 : /*
1369 : * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1370 : * is not activated. The myth is that Asus said that they do not want the
1371 : * users to be irritated by just another PCI Device in the Win98 device
1372 : * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1373 : * package 2.7.0 for details)
1374 : *
1375 : * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1376 : * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1377 : * becomes necessary to do this tweak in two steps -- the chosen trigger
1378 : * is either the Host bridge (preferred) or on-board VGA controller.
1379 : *
1380 : * Note that we used to unhide the SMBus that way on Toshiba laptops
1381 : * (Satellite A40 and Tecra M2) but then found that the thermal management
1382 : * was done by SMM code, which could cause unsynchronized concurrent
1383 : * accesses to the SMBus registers, with potentially bad effects. Thus you
1384 : * should be very careful when adding new entries: if SMM is accessing the
1385 : * Intel SMBus, this is a very good reason to leave it hidden.
1386 : *
1387 : * Likewise, many recent laptops use ACPI for thermal management. If the
1388 : * ACPI DSDT code accesses the SMBus, then Linux should not access it
1389 : * natively, and keeping the SMBus hidden is the right thing to do. If you
1390 : * are about to add an entry in the table below, please first disassemble
1391 : * the DSDT and double-check that there is no code accessing the SMBus.
1392 : */
1393 : static int asus_hides_smbus;
1394 :
1395 0 : static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1396 : {
1397 0 : if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1398 0 : if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1399 0 : switch (dev->subsystem_device) {
1400 : case 0x8025: /* P4B-LX */
1401 : case 0x8070: /* P4B */
1402 : case 0x8088: /* P4B533 */
1403 : case 0x1626: /* L3C notebook */
1404 0 : asus_hides_smbus = 1;
1405 : }
1406 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1407 0 : switch (dev->subsystem_device) {
1408 : case 0x80b1: /* P4GE-V */
1409 : case 0x80b2: /* P4PE */
1410 : case 0x8093: /* P4B533-V */
1411 0 : asus_hides_smbus = 1;
1412 : }
1413 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1414 0 : switch (dev->subsystem_device) {
1415 : case 0x8030: /* P4T533 */
1416 0 : asus_hides_smbus = 1;
1417 : }
1418 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1419 0 : switch (dev->subsystem_device) {
1420 : case 0x8070: /* P4G8X Deluxe */
1421 0 : asus_hides_smbus = 1;
1422 : }
1423 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1424 0 : switch (dev->subsystem_device) {
1425 : case 0x80c9: /* PU-DLS */
1426 0 : asus_hides_smbus = 1;
1427 : }
1428 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1429 0 : switch (dev->subsystem_device) {
1430 : case 0x1751: /* M2N notebook */
1431 : case 0x1821: /* M5N notebook */
1432 : case 0x1897: /* A6L notebook */
1433 0 : asus_hides_smbus = 1;
1434 : }
1435 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1436 0 : switch (dev->subsystem_device) {
1437 : case 0x184b: /* W1N notebook */
1438 : case 0x186a: /* M6Ne notebook */
1439 0 : asus_hides_smbus = 1;
1440 : }
1441 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1442 0 : switch (dev->subsystem_device) {
1443 : case 0x80f2: /* P4P800-X */
1444 0 : asus_hides_smbus = 1;
1445 : }
1446 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1447 0 : switch (dev->subsystem_device) {
1448 : case 0x1882: /* M6V notebook */
1449 : case 0x1977: /* A6VA notebook */
1450 0 : asus_hides_smbus = 1;
1451 : }
1452 0 : } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1453 0 : if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1454 0 : switch (dev->subsystem_device) {
1455 : case 0x088C: /* HP Compaq nc8000 */
1456 : case 0x0890: /* HP Compaq nc6000 */
1457 0 : asus_hides_smbus = 1;
1458 : }
1459 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1460 0 : switch (dev->subsystem_device) {
1461 : case 0x12bc: /* HP D330L */
1462 : case 0x12bd: /* HP D530 */
1463 : case 0x006a: /* HP Compaq nx9500 */
1464 0 : asus_hides_smbus = 1;
1465 : }
1466 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1467 0 : switch (dev->subsystem_device) {
1468 : case 0x12bf: /* HP xw4100 */
1469 0 : asus_hides_smbus = 1;
1470 : }
1471 0 : } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1472 0 : if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1473 0 : switch (dev->subsystem_device) {
1474 : case 0xC00C: /* Samsung P35 notebook */
1475 0 : asus_hides_smbus = 1;
1476 : }
1477 0 : } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1478 0 : if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1479 0 : switch (dev->subsystem_device) {
1480 : case 0x0058: /* Compaq Evo N620c */
1481 0 : asus_hides_smbus = 1;
1482 : }
1483 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1484 0 : switch (dev->subsystem_device) {
1485 : case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1486 : /* Motherboard doesn't have Host bridge
1487 : * subvendor/subdevice IDs, therefore checking
1488 : * its on-board VGA controller */
1489 0 : asus_hides_smbus = 1;
1490 : }
1491 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1492 0 : switch (dev->subsystem_device) {
1493 : case 0x00b8: /* Compaq Evo D510 CMT */
1494 : case 0x00b9: /* Compaq Evo D510 SFF */
1495 : case 0x00ba: /* Compaq Evo D510 USDT */
1496 : /* Motherboard doesn't have Host bridge
1497 : * subvendor/subdevice IDs and on-board VGA
1498 : * controller is disabled if an AGP card is
1499 : * inserted, therefore checking USB UHCI
1500 : * Controller #1 */
1501 0 : asus_hides_smbus = 1;
1502 : }
1503 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1504 0 : switch (dev->subsystem_device) {
1505 : case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1506 : /* Motherboard doesn't have host bridge
1507 : * subvendor/subdevice IDs, therefore checking
1508 : * its on-board VGA controller */
1509 0 : asus_hides_smbus = 1;
1510 : }
1511 : }
1512 0 : }
1513 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1514 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1515 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1516 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1517 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1518 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1519 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1520 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1521 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1522 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1523 :
1524 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1525 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1526 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1527 :
1528 0 : static void asus_hides_smbus_lpc(struct pci_dev *dev)
1529 : {
1530 : u16 val;
1531 :
1532 0 : if (likely(!asus_hides_smbus))
1533 0 : return;
1534 :
1535 0 : pci_read_config_word(dev, 0xF2, &val);
1536 0 : if (val & 0x8) {
1537 0 : pci_write_config_word(dev, 0xF2, val & (~0x8));
1538 0 : pci_read_config_word(dev, 0xF2, &val);
1539 0 : if (val & 0x8)
1540 0 : pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1541 : val);
1542 : else
1543 0 : pci_info(dev, "Enabled i801 SMBus device\n");
1544 : }
1545 : }
1546 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1547 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1548 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1549 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1550 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1551 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1552 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1553 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1554 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1555 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1556 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1557 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1558 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1559 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1560 :
1561 : /* It appears we just have one such device. If not, we have a warning */
1562 : static void __iomem *asus_rcba_base;
1563 0 : static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1564 : {
1565 : u32 rcba;
1566 :
1567 0 : if (likely(!asus_hides_smbus))
1568 0 : return;
1569 0 : WARN_ON(asus_rcba_base);
1570 :
1571 0 : pci_read_config_dword(dev, 0xF0, &rcba);
1572 : /* use bits 31:14, 16 kB aligned */
1573 0 : asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
1574 : if (asus_rcba_base == NULL)
1575 : return;
1576 : }
1577 :
1578 0 : static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1579 : {
1580 : u32 val;
1581 :
1582 0 : if (likely(!asus_hides_smbus || !asus_rcba_base))
1583 : return;
1584 :
1585 : /* read the Function Disable register, dword mode only */
1586 0 : val = readl(asus_rcba_base + 0x3418);
1587 :
1588 : /* enable the SMBus device */
1589 0 : writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1590 : }
1591 :
1592 0 : static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1593 : {
1594 0 : if (likely(!asus_hides_smbus || !asus_rcba_base))
1595 : return;
1596 :
1597 0 : iounmap(asus_rcba_base);
1598 0 : asus_rcba_base = NULL;
1599 0 : pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1600 : }
1601 :
1602 0 : static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1603 : {
1604 0 : asus_hides_smbus_lpc_ich6_suspend(dev);
1605 0 : asus_hides_smbus_lpc_ich6_resume_early(dev);
1606 0 : asus_hides_smbus_lpc_ich6_resume(dev);
1607 0 : }
1608 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1609 : DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1610 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1611 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1612 :
1613 : /* SiS 96x south bridge: BIOS typically hides SMBus device... */
1614 0 : static void quirk_sis_96x_smbus(struct pci_dev *dev)
1615 : {
1616 0 : u8 val = 0;
1617 0 : pci_read_config_byte(dev, 0x77, &val);
1618 0 : if (val & 0x10) {
1619 0 : pci_info(dev, "Enabling SiS 96x SMBus\n");
1620 0 : pci_write_config_byte(dev, 0x77, val & ~0x10);
1621 : }
1622 0 : }
1623 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1624 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1625 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1626 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1627 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1628 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1629 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1630 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1631 :
1632 : /*
1633 : * ... This is further complicated by the fact that some SiS96x south
1634 : * bridges pretend to be 85C503/5513 instead. In that case see if we
1635 : * spotted a compatible north bridge to make sure.
1636 : * (pci_find_device() doesn't work yet)
1637 : *
1638 : * We can also enable the sis96x bit in the discovery register..
1639 : */
1640 : #define SIS_DETECT_REGISTER 0x40
1641 :
1642 0 : static void quirk_sis_503(struct pci_dev *dev)
1643 : {
1644 : u8 reg;
1645 : u16 devid;
1646 :
1647 0 : pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1648 0 : pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1649 0 : pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1650 0 : if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1651 0 : pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1652 0 : return;
1653 : }
1654 :
1655 : /*
1656 : * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1657 : * it has already been processed. (Depends on link order, which is
1658 : * apparently not guaranteed)
1659 : */
1660 0 : dev->device = devid;
1661 0 : quirk_sis_96x_smbus(dev);
1662 : }
1663 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1664 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1665 :
1666 : /*
1667 : * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1668 : * and MC97 modem controller are disabled when a second PCI soundcard is
1669 : * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1670 : * -- bjd
1671 : */
1672 0 : static void asus_hides_ac97_lpc(struct pci_dev *dev)
1673 : {
1674 : u8 val;
1675 0 : int asus_hides_ac97 = 0;
1676 :
1677 0 : if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1678 0 : if (dev->device == PCI_DEVICE_ID_VIA_8237)
1679 0 : asus_hides_ac97 = 1;
1680 : }
1681 :
1682 0 : if (!asus_hides_ac97)
1683 0 : return;
1684 :
1685 0 : pci_read_config_byte(dev, 0x50, &val);
1686 0 : if (val & 0xc0) {
1687 0 : pci_write_config_byte(dev, 0x50, val & (~0xc0));
1688 0 : pci_read_config_byte(dev, 0x50, &val);
1689 0 : if (val & 0xc0)
1690 0 : pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1691 : val);
1692 : else
1693 0 : pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1694 : }
1695 : }
1696 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1697 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1698 :
1699 : #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1700 :
1701 : /*
1702 : * If we are using libata we can drive this chip properly but must do this
1703 : * early on to make the additional device appear during the PCI scanning.
1704 : */
1705 : static void quirk_jmicron_ata(struct pci_dev *pdev)
1706 : {
1707 : u32 conf1, conf5, class;
1708 : u8 hdr;
1709 :
1710 : /* Only poke fn 0 */
1711 : if (PCI_FUNC(pdev->devfn))
1712 : return;
1713 :
1714 : pci_read_config_dword(pdev, 0x40, &conf1);
1715 : pci_read_config_dword(pdev, 0x80, &conf5);
1716 :
1717 : conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1718 : conf5 &= ~(1 << 24); /* Clear bit 24 */
1719 :
1720 : switch (pdev->device) {
1721 : case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1722 : case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1723 : case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1724 : /* The controller should be in single function ahci mode */
1725 : conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1726 : break;
1727 :
1728 : case PCI_DEVICE_ID_JMICRON_JMB365:
1729 : case PCI_DEVICE_ID_JMICRON_JMB366:
1730 : /* Redirect IDE second PATA port to the right spot */
1731 : conf5 |= (1 << 24);
1732 : fallthrough;
1733 : case PCI_DEVICE_ID_JMICRON_JMB361:
1734 : case PCI_DEVICE_ID_JMICRON_JMB363:
1735 : case PCI_DEVICE_ID_JMICRON_JMB369:
1736 : /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1737 : /* Set the class codes correctly and then direct IDE 0 */
1738 : conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1739 : break;
1740 :
1741 : case PCI_DEVICE_ID_JMICRON_JMB368:
1742 : /* The controller should be in single function IDE mode */
1743 : conf1 |= 0x00C00000; /* Set 22, 23 */
1744 : break;
1745 : }
1746 :
1747 : pci_write_config_dword(pdev, 0x40, conf1);
1748 : pci_write_config_dword(pdev, 0x80, conf5);
1749 :
1750 : /* Update pdev accordingly */
1751 : pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1752 : pdev->hdr_type = hdr & 0x7f;
1753 : pdev->multifunction = !!(hdr & 0x80);
1754 :
1755 : pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1756 : pdev->class = class >> 8;
1757 : }
1758 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1759 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1760 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1761 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1762 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1763 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1764 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1765 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1766 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1767 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1768 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1769 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1770 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1771 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1772 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1773 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1774 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1775 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1776 :
1777 : #endif
1778 :
1779 0 : static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1780 : {
1781 0 : if (dev->multifunction) {
1782 0 : device_disable_async_suspend(&dev->dev);
1783 0 : pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1784 : }
1785 0 : }
1786 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1787 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1788 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1789 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1790 :
1791 : #ifdef CONFIG_X86_IO_APIC
1792 : static void quirk_alder_ioapic(struct pci_dev *pdev)
1793 : {
1794 : int i;
1795 :
1796 : if ((pdev->class >> 8) != 0xff00)
1797 : return;
1798 :
1799 : /*
1800 : * The first BAR is the location of the IO-APIC... we must
1801 : * not touch this (and it's already covered by the fixmap), so
1802 : * forcibly insert it into the resource tree.
1803 : */
1804 : if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1805 : insert_resource(&iomem_resource, &pdev->resource[0]);
1806 :
1807 : /*
1808 : * The next five BARs all seem to be rubbish, so just clean
1809 : * them out.
1810 : */
1811 : for (i = 1; i < PCI_STD_NUM_BARS; i++)
1812 : memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1813 : }
1814 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1815 : #endif
1816 :
1817 0 : static void quirk_no_msi(struct pci_dev *dev)
1818 : {
1819 0 : pci_info(dev, "avoiding MSI to work around a hardware defect\n");
1820 0 : dev->no_msi = 1;
1821 0 : }
1822 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
1823 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
1824 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
1825 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
1826 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
1827 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
1828 :
1829 0 : static void quirk_pcie_mch(struct pci_dev *pdev)
1830 : {
1831 0 : pdev->no_msi = 1;
1832 0 : }
1833 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1834 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1835 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1836 :
1837 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1838 :
1839 : /*
1840 : * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are
1841 : * actually on the AMBA bus. These fake PCI devices can support SVA via
1842 : * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
1843 : *
1844 : * Normally stalling must not be enabled for PCI devices, since it would
1845 : * break the PCI requirement for free-flowing writes and may lead to
1846 : * deadlock. We expect PCI devices to support ATS and PRI if they want to
1847 : * be fault-tolerant, so there's no ACPI binding to describe anything else,
1848 : * even when a "PCI" device turns out to be a regular old SoC device
1849 : * dressed up as a RCiEP and normal rules don't apply.
1850 : */
1851 0 : static void quirk_huawei_pcie_sva(struct pci_dev *pdev)
1852 : {
1853 0 : struct property_entry properties[] = {
1854 : PROPERTY_ENTRY_BOOL("dma-can-stall"),
1855 : {},
1856 : };
1857 :
1858 0 : if (pdev->revision != 0x21 && pdev->revision != 0x30)
1859 0 : return;
1860 :
1861 0 : pdev->pasid_no_tlp = 1;
1862 :
1863 : /*
1864 : * Set the dma-can-stall property on ACPI platforms. Device tree
1865 : * can set it directly.
1866 : */
1867 0 : if (!pdev->dev.of_node &&
1868 0 : device_create_managed_software_node(&pdev->dev, properties, NULL))
1869 0 : pci_warn(pdev, "could not add stall property");
1870 : }
1871 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva);
1872 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva);
1873 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva);
1874 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva);
1875 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva);
1876 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva);
1877 :
1878 : /*
1879 : * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1880 : * together on certain PXH-based systems.
1881 : */
1882 0 : static void quirk_pcie_pxh(struct pci_dev *dev)
1883 : {
1884 0 : dev->no_msi = 1;
1885 0 : pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1886 0 : }
1887 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1888 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1889 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1890 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1891 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1892 :
1893 : /*
1894 : * Some Intel PCI Express chipsets have trouble with downstream device
1895 : * power management.
1896 : */
1897 0 : static void quirk_intel_pcie_pm(struct pci_dev *dev)
1898 : {
1899 0 : pci_pm_d3hot_delay = 120;
1900 0 : dev->no_d1d2 = 1;
1901 0 : }
1902 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1903 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1904 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1905 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1906 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1907 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1908 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1909 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1910 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1911 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1912 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1913 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1914 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1915 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1916 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1917 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1918 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1919 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1920 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1921 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1922 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1923 :
1924 : static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
1925 : {
1926 0 : if (dev->d3hot_delay >= delay)
1927 : return;
1928 :
1929 0 : dev->d3hot_delay = delay;
1930 0 : pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
1931 : dev->d3hot_delay);
1932 : }
1933 :
1934 0 : static void quirk_radeon_pm(struct pci_dev *dev)
1935 : {
1936 0 : if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1937 : dev->subsystem_device == 0x00e2)
1938 : quirk_d3hot_delay(dev, 20);
1939 0 : }
1940 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1941 :
1942 : /*
1943 : * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus
1944 : * reset is performed too soon after transition to D0, extend d3hot_delay
1945 : * to previous effective default for all NVIDIA HDA controllers.
1946 : */
1947 0 : static void quirk_nvidia_hda_pm(struct pci_dev *dev)
1948 : {
1949 0 : quirk_d3hot_delay(dev, 20);
1950 0 : }
1951 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
1952 : PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8,
1953 : quirk_nvidia_hda_pm);
1954 :
1955 : /*
1956 : * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1957 : * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1958 : *
1959 : * The kernel attempts to transition these devices to D3cold, but that seems
1960 : * to be ineffective on the platforms in question; the PCI device appears to
1961 : * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1962 : * extended delay in order to succeed.
1963 : */
1964 0 : static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
1965 : {
1966 0 : quirk_d3hot_delay(dev, 20);
1967 0 : }
1968 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
1969 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
1970 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
1971 :
1972 : #ifdef CONFIG_X86_IO_APIC
1973 : static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1974 : {
1975 : noioapicreroute = 1;
1976 : pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1977 :
1978 : return 0;
1979 : }
1980 :
1981 : static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1982 : /*
1983 : * Systems to exclude from boot interrupt reroute quirks
1984 : */
1985 : {
1986 : .callback = dmi_disable_ioapicreroute,
1987 : .ident = "ASUSTek Computer INC. M2N-LR",
1988 : .matches = {
1989 : DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1990 : DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1991 : },
1992 : },
1993 : {}
1994 : };
1995 :
1996 : /*
1997 : * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1998 : * remap the original interrupt in the Linux kernel to the boot interrupt, so
1999 : * that a PCI device's interrupt handler is installed on the boot interrupt
2000 : * line instead.
2001 : */
2002 : static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
2003 : {
2004 : dmi_check_system(boot_interrupt_dmi_table);
2005 : if (noioapicquirk || noioapicreroute)
2006 : return;
2007 :
2008 : dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
2009 : pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
2010 : dev->vendor, dev->device);
2011 : }
2012 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
2013 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
2014 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
2015 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
2016 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
2017 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
2018 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
2019 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
2020 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
2021 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
2022 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
2023 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
2024 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
2025 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
2026 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
2027 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
2028 :
2029 : /*
2030 : * On some chipsets we can disable the generation of legacy INTx boot
2031 : * interrupts.
2032 : */
2033 :
2034 : /*
2035 : * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2036 : * 300641-004US, section 5.7.3.
2037 : *
2038 : * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2039 : * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2040 : * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2041 : * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2042 : * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2043 : * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2044 : * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2045 : * Core IO on Xeon D-1500, see Intel order no 332051-001.
2046 : * Core IO on Xeon Scalable, see Intel order no 610950.
2047 : */
2048 : #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
2049 : #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
2050 :
2051 : #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
2052 : #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
2053 :
2054 : static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
2055 : {
2056 : u16 pci_config_word;
2057 : u32 pci_config_dword;
2058 :
2059 : if (noioapicquirk)
2060 : return;
2061 :
2062 : switch (dev->device) {
2063 : case PCI_DEVICE_ID_INTEL_ESB_10:
2064 : pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2065 : &pci_config_word);
2066 : pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
2067 : pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2068 : pci_config_word);
2069 : break;
2070 : case 0x3c28: /* Xeon E5 1600/2600/4600 */
2071 : case 0x0e28: /* Xeon E5/E7 V2 */
2072 : case 0x2f28: /* Xeon E5/E7 V3,V4 */
2073 : case 0x6f28: /* Xeon D-1500 */
2074 : case 0x2034: /* Xeon Scalable Family */
2075 : pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2076 : &pci_config_dword);
2077 : pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
2078 : pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2079 : pci_config_dword);
2080 : break;
2081 : default:
2082 : return;
2083 : }
2084 : pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2085 : dev->vendor, dev->device);
2086 : }
2087 : /*
2088 : * Device 29 Func 5 Device IDs of IO-APIC
2089 : * containing ABAR—APIC1 Alternate Base Address Register
2090 : */
2091 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2092 : quirk_disable_intel_boot_interrupt);
2093 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2094 : quirk_disable_intel_boot_interrupt);
2095 :
2096 : /*
2097 : * Device 5 Func 0 Device IDs of Core IO modules/hubs
2098 : * containing Coherent Interface Protocol Interrupt Control
2099 : *
2100 : * Device IDs obtained from volume 2 datasheets of commented
2101 : * families above.
2102 : */
2103 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2104 : quirk_disable_intel_boot_interrupt);
2105 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2106 : quirk_disable_intel_boot_interrupt);
2107 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2108 : quirk_disable_intel_boot_interrupt);
2109 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2110 : quirk_disable_intel_boot_interrupt);
2111 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2112 : quirk_disable_intel_boot_interrupt);
2113 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2114 : quirk_disable_intel_boot_interrupt);
2115 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2116 : quirk_disable_intel_boot_interrupt);
2117 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2118 : quirk_disable_intel_boot_interrupt);
2119 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2120 : quirk_disable_intel_boot_interrupt);
2121 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2122 : quirk_disable_intel_boot_interrupt);
2123 :
2124 : /* Disable boot interrupts on HT-1000 */
2125 : #define BC_HT1000_FEATURE_REG 0x64
2126 : #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2127 : #define BC_HT1000_MAP_IDX 0xC00
2128 : #define BC_HT1000_MAP_DATA 0xC01
2129 :
2130 : static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2131 : {
2132 : u32 pci_config_dword;
2133 : u8 irq;
2134 :
2135 : if (noioapicquirk)
2136 : return;
2137 :
2138 : pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2139 : pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2140 : BC_HT1000_PIC_REGS_ENABLE);
2141 :
2142 : for (irq = 0x10; irq < 0x10 + 32; irq++) {
2143 : outb(irq, BC_HT1000_MAP_IDX);
2144 : outb(0x00, BC_HT1000_MAP_DATA);
2145 : }
2146 :
2147 : pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2148 :
2149 : pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2150 : dev->vendor, dev->device);
2151 : }
2152 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2153 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2154 :
2155 : /* Disable boot interrupts on AMD and ATI chipsets */
2156 :
2157 : /*
2158 : * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2159 : * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2160 : * (due to an erratum).
2161 : */
2162 : #define AMD_813X_MISC 0x40
2163 : #define AMD_813X_NOIOAMODE (1<<0)
2164 : #define AMD_813X_REV_B1 0x12
2165 : #define AMD_813X_REV_B2 0x13
2166 :
2167 : static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2168 : {
2169 : u32 pci_config_dword;
2170 :
2171 : if (noioapicquirk)
2172 : return;
2173 : if ((dev->revision == AMD_813X_REV_B1) ||
2174 : (dev->revision == AMD_813X_REV_B2))
2175 : return;
2176 :
2177 : pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2178 : pci_config_dword &= ~AMD_813X_NOIOAMODE;
2179 : pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2180 :
2181 : pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2182 : dev->vendor, dev->device);
2183 : }
2184 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2185 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2186 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2187 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2188 :
2189 : #define AMD_8111_PCI_IRQ_ROUTING 0x56
2190 :
2191 : static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2192 : {
2193 : u16 pci_config_word;
2194 :
2195 : if (noioapicquirk)
2196 : return;
2197 :
2198 : pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2199 : if (!pci_config_word) {
2200 : pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2201 : dev->vendor, dev->device);
2202 : return;
2203 : }
2204 : pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2205 : pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2206 : dev->vendor, dev->device);
2207 : }
2208 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2209 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2210 : #endif /* CONFIG_X86_IO_APIC */
2211 :
2212 : /*
2213 : * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2214 : * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2215 : * Re-allocate the region if needed...
2216 : */
2217 0 : static void quirk_tc86c001_ide(struct pci_dev *dev)
2218 : {
2219 0 : struct resource *r = &dev->resource[0];
2220 :
2221 0 : if (r->start & 0x8) {
2222 0 : r->flags |= IORESOURCE_UNSET;
2223 0 : r->start = 0;
2224 0 : r->end = 0xf;
2225 : }
2226 0 : }
2227 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2228 : PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2229 : quirk_tc86c001_ide);
2230 :
2231 : /*
2232 : * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2233 : * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2234 : * being read correctly if bit 7 of the base address is set.
2235 : * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2236 : * Re-allocate the regions to a 256-byte boundary if necessary.
2237 : */
2238 0 : static void quirk_plx_pci9050(struct pci_dev *dev)
2239 : {
2240 : unsigned int bar;
2241 :
2242 : /* Fixed in revision 2 (PCI 9052). */
2243 0 : if (dev->revision >= 2)
2244 : return;
2245 0 : for (bar = 0; bar <= 1; bar++)
2246 0 : if (pci_resource_len(dev, bar) == 0x80 &&
2247 0 : (pci_resource_start(dev, bar) & 0x80)) {
2248 0 : struct resource *r = &dev->resource[bar];
2249 0 : pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2250 : bar);
2251 0 : r->flags |= IORESOURCE_UNSET;
2252 0 : r->start = 0;
2253 0 : r->end = 0xff;
2254 : }
2255 : }
2256 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2257 : quirk_plx_pci9050);
2258 : /*
2259 : * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2260 : * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2261 : * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2262 : * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2263 : *
2264 : * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2265 : * driver.
2266 : */
2267 : DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2268 : DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2269 :
2270 0 : static void quirk_netmos(struct pci_dev *dev)
2271 : {
2272 0 : unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2273 0 : unsigned int num_serial = dev->subsystem_device & 0xf;
2274 :
2275 : /*
2276 : * These Netmos parts are multiport serial devices with optional
2277 : * parallel ports. Even when parallel ports are present, they
2278 : * are identified as class SERIAL, which means the serial driver
2279 : * will claim them. To prevent this, mark them as class OTHER.
2280 : * These combo devices should be claimed by parport_serial.
2281 : *
2282 : * The subdevice ID is of the form 0x00PS, where <P> is the number
2283 : * of parallel ports and <S> is the number of serial ports.
2284 : */
2285 0 : switch (dev->device) {
2286 : case PCI_DEVICE_ID_NETMOS_9835:
2287 : /* Well, this rule doesn't hold for the following 9835 device */
2288 0 : if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2289 : dev->subsystem_device == 0x0299)
2290 : return;
2291 : fallthrough;
2292 : case PCI_DEVICE_ID_NETMOS_9735:
2293 : case PCI_DEVICE_ID_NETMOS_9745:
2294 : case PCI_DEVICE_ID_NETMOS_9845:
2295 : case PCI_DEVICE_ID_NETMOS_9855:
2296 0 : if (num_parallel) {
2297 0 : pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2298 : dev->device, num_parallel, num_serial);
2299 0 : dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2300 0 : (dev->class & 0xff);
2301 : }
2302 : }
2303 : }
2304 : DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2305 : PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2306 :
2307 0 : static void quirk_e100_interrupt(struct pci_dev *dev)
2308 : {
2309 : u16 command, pmcsr;
2310 : u8 __iomem *csr;
2311 : u8 cmd_hi;
2312 :
2313 0 : switch (dev->device) {
2314 : /* PCI IDs taken from drivers/net/e100.c */
2315 : case 0x1029:
2316 : case 0x1030 ... 0x1034:
2317 : case 0x1038 ... 0x103E:
2318 : case 0x1050 ... 0x1057:
2319 : case 0x1059:
2320 : case 0x1064 ... 0x106B:
2321 : case 0x1091 ... 0x1095:
2322 : case 0x1209:
2323 : case 0x1229:
2324 : case 0x2449:
2325 : case 0x2459:
2326 : case 0x245D:
2327 : case 0x27DC:
2328 : break;
2329 : default:
2330 0 : return;
2331 : }
2332 :
2333 : /*
2334 : * Some firmware hands off the e100 with interrupts enabled,
2335 : * which can cause a flood of interrupts if packets are
2336 : * received before the driver attaches to the device. So
2337 : * disable all e100 interrupts here. The driver will
2338 : * re-enable them when it's ready.
2339 : */
2340 0 : pci_read_config_word(dev, PCI_COMMAND, &command);
2341 :
2342 0 : if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2343 : return;
2344 :
2345 : /*
2346 : * Check that the device is in the D0 power state. If it's not,
2347 : * there is no point to look any further.
2348 : */
2349 0 : if (dev->pm_cap) {
2350 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2351 0 : if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2352 : return;
2353 : }
2354 :
2355 : /* Convert from PCI bus to resource space. */
2356 0 : csr = ioremap(pci_resource_start(dev, 0), 8);
2357 0 : if (!csr) {
2358 0 : pci_warn(dev, "Can't map e100 registers\n");
2359 0 : return;
2360 : }
2361 :
2362 0 : cmd_hi = readb(csr + 3);
2363 0 : if (cmd_hi == 0) {
2364 0 : pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2365 0 : writeb(1, csr + 3);
2366 : }
2367 :
2368 0 : iounmap(csr);
2369 : }
2370 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2371 : PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2372 :
2373 : /*
2374 : * The 82575 and 82598 may experience data corruption issues when transitioning
2375 : * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2376 : */
2377 0 : static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2378 : {
2379 0 : pci_info(dev, "Disabling L0s\n");
2380 0 : pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2381 0 : }
2382 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2383 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2384 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2385 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2386 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2387 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2388 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2389 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2390 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2391 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2392 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2393 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2394 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2395 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2396 :
2397 0 : static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2398 : {
2399 0 : pci_info(dev, "Disabling ASPM L0s/L1\n");
2400 0 : pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2401 0 : }
2402 :
2403 : /*
2404 : * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2405 : * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2406 : * disable both L0s and L1 for now to be safe.
2407 : */
2408 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2409 :
2410 : /*
2411 : * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2412 : * Link bit cleared after starting the link retrain process to allow this
2413 : * process to finish.
2414 : *
2415 : * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2416 : * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2417 : */
2418 0 : static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2419 : {
2420 0 : dev->clear_retrain_link = 1;
2421 0 : pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2422 0 : }
2423 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link);
2424 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link);
2425 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link);
2426 :
2427 0 : static void fixup_rev1_53c810(struct pci_dev *dev)
2428 : {
2429 0 : u32 class = dev->class;
2430 :
2431 : /*
2432 : * rev 1 ncr53c810 chips don't set the class at all which means
2433 : * they don't get their resources remapped. Fix that here.
2434 : */
2435 0 : if (class)
2436 : return;
2437 :
2438 0 : dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2439 0 : pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2440 : class, dev->class);
2441 : }
2442 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2443 :
2444 : /* Enable 1k I/O space granularity on the Intel P64H2 */
2445 0 : static void quirk_p64h2_1k_io(struct pci_dev *dev)
2446 : {
2447 : u16 en1k;
2448 :
2449 0 : pci_read_config_word(dev, 0x40, &en1k);
2450 :
2451 0 : if (en1k & 0x200) {
2452 0 : pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2453 0 : dev->io_window_1k = 1;
2454 : }
2455 0 : }
2456 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2457 :
2458 : /*
2459 : * Under some circumstances, AER is not linked with extended capabilities.
2460 : * Force it to be linked by setting the corresponding control bit in the
2461 : * config space.
2462 : */
2463 0 : static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2464 : {
2465 : uint8_t b;
2466 :
2467 0 : if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2468 0 : if (!(b & 0x20)) {
2469 0 : pci_write_config_byte(dev, 0xf41, b | 0x20);
2470 0 : pci_info(dev, "Linking AER extended capability\n");
2471 : }
2472 : }
2473 0 : }
2474 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2475 : quirk_nvidia_ck804_pcie_aer_ext_cap);
2476 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2477 : quirk_nvidia_ck804_pcie_aer_ext_cap);
2478 :
2479 0 : static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2480 : {
2481 : /*
2482 : * Disable PCI Bus Parking and PCI Master read caching on CX700
2483 : * which causes unspecified timing errors with a VT6212L on the PCI
2484 : * bus leading to USB2.0 packet loss.
2485 : *
2486 : * This quirk is only enabled if a second (on the external PCI bus)
2487 : * VT6212L is found -- the CX700 core itself also contains a USB
2488 : * host controller with the same PCI ID as the VT6212L.
2489 : */
2490 :
2491 : /* Count VT6212L instances */
2492 0 : struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2493 : PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2494 : uint8_t b;
2495 :
2496 : /*
2497 : * p should contain the first (internal) VT6212L -- see if we have
2498 : * an external one by searching again.
2499 : */
2500 0 : p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2501 0 : if (!p)
2502 0 : return;
2503 0 : pci_dev_put(p);
2504 :
2505 0 : if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2506 0 : if (b & 0x40) {
2507 : /* Turn off PCI Bus Parking */
2508 0 : pci_write_config_byte(dev, 0x76, b ^ 0x40);
2509 :
2510 0 : pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2511 : }
2512 : }
2513 :
2514 0 : if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2515 0 : if (b != 0) {
2516 : /* Turn off PCI Master read caching */
2517 0 : pci_write_config_byte(dev, 0x72, 0x0);
2518 :
2519 : /* Set PCI Master Bus time-out to "1x16 PCLK" */
2520 0 : pci_write_config_byte(dev, 0x75, 0x1);
2521 :
2522 : /* Disable "Read FIFO Timer" */
2523 0 : pci_write_config_byte(dev, 0x77, 0x0);
2524 :
2525 0 : pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2526 : }
2527 : }
2528 : }
2529 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2530 :
2531 0 : static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2532 : {
2533 : u32 rev;
2534 :
2535 0 : pci_read_config_dword(dev, 0xf4, &rev);
2536 :
2537 : /* Only CAP the MRRS if the device is a 5719 A0 */
2538 0 : if (rev == 0x05719000) {
2539 0 : int readrq = pcie_get_readrq(dev);
2540 0 : if (readrq > 2048)
2541 0 : pcie_set_readrq(dev, 2048);
2542 : }
2543 0 : }
2544 : DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2545 : PCI_DEVICE_ID_TIGON3_5719,
2546 : quirk_brcm_5719_limit_mrrs);
2547 :
2548 : /*
2549 : * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2550 : * hide device 6 which configures the overflow device access containing the
2551 : * DRBs - this is where we expose device 6.
2552 : * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2553 : */
2554 0 : static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2555 : {
2556 : u8 reg;
2557 :
2558 0 : if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2559 0 : pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2560 0 : pci_write_config_byte(dev, 0xF4, reg | 0x02);
2561 : }
2562 0 : }
2563 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2564 : quirk_unhide_mch_dev6);
2565 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2566 : quirk_unhide_mch_dev6);
2567 :
2568 : #ifdef CONFIG_PCI_MSI
2569 : /*
2570 : * Some chipsets do not support MSI. We cannot easily rely on setting
2571 : * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2572 : * other buses controlled by the chipset even if Linux is not aware of it.
2573 : * Instead of setting the flag on all buses in the machine, simply disable
2574 : * MSI globally.
2575 : */
2576 0 : static void quirk_disable_all_msi(struct pci_dev *dev)
2577 : {
2578 0 : pci_no_msi();
2579 0 : pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2580 0 : }
2581 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2582 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2583 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2584 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2585 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2586 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2587 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2588 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2589 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi);
2590 :
2591 : /* Disable MSI on chipsets that are known to not support it */
2592 0 : static void quirk_disable_msi(struct pci_dev *dev)
2593 : {
2594 0 : if (dev->subordinate) {
2595 0 : pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2596 0 : dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2597 : }
2598 0 : }
2599 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2600 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2601 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2602 :
2603 : /*
2604 : * The APC bridge device in AMD 780 family northbridges has some random
2605 : * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2606 : * we use the possible vendor/device IDs of the host bridge for the
2607 : * declared quirk, and search for the APC bridge by slot number.
2608 : */
2609 0 : static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2610 : {
2611 : struct pci_dev *apc_bridge;
2612 :
2613 0 : apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2614 0 : if (apc_bridge) {
2615 0 : if (apc_bridge->device == 0x9602)
2616 : quirk_disable_msi(apc_bridge);
2617 0 : pci_dev_put(apc_bridge);
2618 : }
2619 0 : }
2620 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2621 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2622 :
2623 : /*
2624 : * Go through the list of HyperTransport capabilities and return 1 if a HT
2625 : * MSI capability is found and enabled.
2626 : */
2627 0 : static int msi_ht_cap_enabled(struct pci_dev *dev)
2628 : {
2629 0 : int pos, ttl = PCI_FIND_CAP_TTL;
2630 :
2631 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2632 0 : while (pos && ttl--) {
2633 : u8 flags;
2634 :
2635 0 : if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2636 : &flags) == 0) {
2637 0 : pci_info(dev, "Found %s HT MSI Mapping\n",
2638 : flags & HT_MSI_FLAGS_ENABLE ?
2639 : "enabled" : "disabled");
2640 0 : return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2641 : }
2642 :
2643 0 : pos = pci_find_next_ht_capability(dev, pos,
2644 : HT_CAPTYPE_MSI_MAPPING);
2645 : }
2646 : return 0;
2647 : }
2648 :
2649 : /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2650 0 : static void quirk_msi_ht_cap(struct pci_dev *dev)
2651 : {
2652 0 : if (!msi_ht_cap_enabled(dev))
2653 : quirk_disable_msi(dev);
2654 0 : }
2655 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2656 : quirk_msi_ht_cap);
2657 :
2658 : /*
2659 : * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2660 : * if the MSI capability is set in any of these mappings.
2661 : */
2662 0 : static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2663 : {
2664 : struct pci_dev *pdev;
2665 :
2666 : /*
2667 : * Check HT MSI cap on this chipset and the root one. A single one
2668 : * having MSI is enough to be sure that MSI is supported.
2669 : */
2670 0 : pdev = pci_get_slot(dev->bus, 0);
2671 0 : if (!pdev)
2672 : return;
2673 0 : if (!msi_ht_cap_enabled(pdev))
2674 0 : quirk_msi_ht_cap(dev);
2675 0 : pci_dev_put(pdev);
2676 : }
2677 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2678 : quirk_nvidia_ck804_msi_ht_cap);
2679 :
2680 : /* Force enable MSI mapping capability on HT bridges */
2681 0 : static void ht_enable_msi_mapping(struct pci_dev *dev)
2682 : {
2683 0 : int pos, ttl = PCI_FIND_CAP_TTL;
2684 :
2685 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2686 0 : while (pos && ttl--) {
2687 : u8 flags;
2688 :
2689 0 : if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2690 : &flags) == 0) {
2691 0 : pci_info(dev, "Enabling HT MSI Mapping\n");
2692 :
2693 0 : pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2694 : flags | HT_MSI_FLAGS_ENABLE);
2695 : }
2696 0 : pos = pci_find_next_ht_capability(dev, pos,
2697 : HT_CAPTYPE_MSI_MAPPING);
2698 : }
2699 0 : }
2700 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2701 : PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2702 : ht_enable_msi_mapping);
2703 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2704 : ht_enable_msi_mapping);
2705 :
2706 : /*
2707 : * The P5N32-SLI motherboards from Asus have a problem with MSI
2708 : * for the MCP55 NIC. It is not yet determined whether the MSI problem
2709 : * also affects other devices. As for now, turn off MSI for this device.
2710 : */
2711 0 : static void nvenet_msi_disable(struct pci_dev *dev)
2712 : {
2713 0 : const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2714 :
2715 : if (board_name &&
2716 : (strstr(board_name, "P5N32-SLI PREMIUM") ||
2717 : strstr(board_name, "P5N32-E SLI"))) {
2718 : pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2719 : dev->no_msi = 1;
2720 : }
2721 0 : }
2722 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2723 : PCI_DEVICE_ID_NVIDIA_NVENET_15,
2724 : nvenet_msi_disable);
2725 :
2726 : /*
2727 : * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2728 : * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI
2729 : * interrupts for PME and AER events; instead only INTx interrupts are
2730 : * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts
2731 : * for other events, since PCIe specification doesn't support using a mix of
2732 : * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2733 : * service drivers registering their respective ISRs for MSIs.
2734 : */
2735 0 : static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2736 : {
2737 0 : dev->no_msi = 1;
2738 0 : }
2739 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2740 : PCI_CLASS_BRIDGE_PCI, 8,
2741 : pci_quirk_nvidia_tegra_disable_rp_msi);
2742 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2743 : PCI_CLASS_BRIDGE_PCI, 8,
2744 : pci_quirk_nvidia_tegra_disable_rp_msi);
2745 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2746 : PCI_CLASS_BRIDGE_PCI, 8,
2747 : pci_quirk_nvidia_tegra_disable_rp_msi);
2748 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2749 : PCI_CLASS_BRIDGE_PCI, 8,
2750 : pci_quirk_nvidia_tegra_disable_rp_msi);
2751 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2752 : PCI_CLASS_BRIDGE_PCI, 8,
2753 : pci_quirk_nvidia_tegra_disable_rp_msi);
2754 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2755 : PCI_CLASS_BRIDGE_PCI, 8,
2756 : pci_quirk_nvidia_tegra_disable_rp_msi);
2757 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2758 : PCI_CLASS_BRIDGE_PCI, 8,
2759 : pci_quirk_nvidia_tegra_disable_rp_msi);
2760 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2761 : PCI_CLASS_BRIDGE_PCI, 8,
2762 : pci_quirk_nvidia_tegra_disable_rp_msi);
2763 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2764 : PCI_CLASS_BRIDGE_PCI, 8,
2765 : pci_quirk_nvidia_tegra_disable_rp_msi);
2766 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2767 : PCI_CLASS_BRIDGE_PCI, 8,
2768 : pci_quirk_nvidia_tegra_disable_rp_msi);
2769 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2770 : PCI_CLASS_BRIDGE_PCI, 8,
2771 : pci_quirk_nvidia_tegra_disable_rp_msi);
2772 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2773 : PCI_CLASS_BRIDGE_PCI, 8,
2774 : pci_quirk_nvidia_tegra_disable_rp_msi);
2775 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2776 : PCI_CLASS_BRIDGE_PCI, 8,
2777 : pci_quirk_nvidia_tegra_disable_rp_msi);
2778 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a,
2779 : PCI_CLASS_BRIDGE_PCI, 8,
2780 : pci_quirk_nvidia_tegra_disable_rp_msi);
2781 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c,
2782 : PCI_CLASS_BRIDGE_PCI, 8,
2783 : pci_quirk_nvidia_tegra_disable_rp_msi);
2784 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e,
2785 : PCI_CLASS_BRIDGE_PCI, 8,
2786 : pci_quirk_nvidia_tegra_disable_rp_msi);
2787 :
2788 : /*
2789 : * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2790 : * config register. This register controls the routing of legacy
2791 : * interrupts from devices that route through the MCP55. If this register
2792 : * is misprogrammed, interrupts are only sent to the BSP, unlike
2793 : * conventional systems where the IRQ is broadcast to all online CPUs. Not
2794 : * having this register set properly prevents kdump from booting up
2795 : * properly, so let's make sure that we have it set correctly.
2796 : * Note that this is an undocumented register.
2797 : */
2798 0 : static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2799 : {
2800 : u32 cfg;
2801 :
2802 0 : if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2803 0 : return;
2804 :
2805 0 : pci_read_config_dword(dev, 0x74, &cfg);
2806 :
2807 0 : if (cfg & ((1 << 2) | (1 << 15))) {
2808 0 : pr_info("Rewriting IRQ routing register on MCP55\n");
2809 0 : cfg &= ~((1 << 2) | (1 << 15));
2810 0 : pci_write_config_dword(dev, 0x74, cfg);
2811 : }
2812 : }
2813 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2814 : PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2815 : nvbridge_check_legacy_irq_routing);
2816 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2817 : PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2818 : nvbridge_check_legacy_irq_routing);
2819 :
2820 0 : static int ht_check_msi_mapping(struct pci_dev *dev)
2821 : {
2822 0 : int pos, ttl = PCI_FIND_CAP_TTL;
2823 0 : int found = 0;
2824 :
2825 : /* Check if there is HT MSI cap or enabled on this device */
2826 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2827 0 : while (pos && ttl--) {
2828 : u8 flags;
2829 :
2830 0 : if (found < 1)
2831 0 : found = 1;
2832 0 : if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2833 : &flags) == 0) {
2834 0 : if (flags & HT_MSI_FLAGS_ENABLE) {
2835 0 : if (found < 2) {
2836 0 : found = 2;
2837 0 : break;
2838 : }
2839 : }
2840 : }
2841 0 : pos = pci_find_next_ht_capability(dev, pos,
2842 : HT_CAPTYPE_MSI_MAPPING);
2843 : }
2844 :
2845 0 : return found;
2846 : }
2847 :
2848 0 : static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2849 : {
2850 : struct pci_dev *dev;
2851 : int pos;
2852 : int i, dev_no;
2853 0 : int found = 0;
2854 :
2855 0 : dev_no = host_bridge->devfn >> 3;
2856 0 : for (i = dev_no + 1; i < 0x20; i++) {
2857 0 : dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2858 0 : if (!dev)
2859 0 : continue;
2860 :
2861 : /* found next host bridge? */
2862 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2863 0 : if (pos != 0) {
2864 0 : pci_dev_put(dev);
2865 : break;
2866 : }
2867 :
2868 0 : if (ht_check_msi_mapping(dev)) {
2869 0 : found = 1;
2870 0 : pci_dev_put(dev);
2871 : break;
2872 : }
2873 0 : pci_dev_put(dev);
2874 : }
2875 :
2876 0 : return found;
2877 : }
2878 :
2879 : #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2880 : #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2881 :
2882 0 : static int is_end_of_ht_chain(struct pci_dev *dev)
2883 : {
2884 : int pos, ctrl_off;
2885 0 : int end = 0;
2886 : u16 flags, ctrl;
2887 :
2888 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2889 :
2890 0 : if (!pos)
2891 : goto out;
2892 :
2893 0 : pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2894 :
2895 0 : ctrl_off = ((flags >> 10) & 1) ?
2896 0 : PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2897 0 : pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2898 :
2899 0 : if (ctrl & (1 << 6))
2900 0 : end = 1;
2901 :
2902 : out:
2903 0 : return end;
2904 : }
2905 :
2906 0 : static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2907 : {
2908 : struct pci_dev *host_bridge;
2909 : int pos;
2910 : int i, dev_no;
2911 0 : int found = 0;
2912 :
2913 0 : dev_no = dev->devfn >> 3;
2914 0 : for (i = dev_no; i >= 0; i--) {
2915 0 : host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2916 0 : if (!host_bridge)
2917 0 : continue;
2918 :
2919 0 : pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2920 0 : if (pos != 0) {
2921 : found = 1;
2922 : break;
2923 : }
2924 0 : pci_dev_put(host_bridge);
2925 : }
2926 :
2927 0 : if (!found)
2928 : return;
2929 :
2930 : /* don't enable end_device/host_bridge with leaf directly here */
2931 0 : if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2932 0 : host_bridge_with_leaf(host_bridge))
2933 : goto out;
2934 :
2935 : /* root did that ! */
2936 0 : if (msi_ht_cap_enabled(host_bridge))
2937 : goto out;
2938 :
2939 0 : ht_enable_msi_mapping(dev);
2940 :
2941 : out:
2942 0 : pci_dev_put(host_bridge);
2943 : }
2944 :
2945 0 : static void ht_disable_msi_mapping(struct pci_dev *dev)
2946 : {
2947 0 : int pos, ttl = PCI_FIND_CAP_TTL;
2948 :
2949 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2950 0 : while (pos && ttl--) {
2951 : u8 flags;
2952 :
2953 0 : if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2954 : &flags) == 0) {
2955 0 : pci_info(dev, "Disabling HT MSI Mapping\n");
2956 :
2957 0 : pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2958 0 : flags & ~HT_MSI_FLAGS_ENABLE);
2959 : }
2960 0 : pos = pci_find_next_ht_capability(dev, pos,
2961 : HT_CAPTYPE_MSI_MAPPING);
2962 : }
2963 0 : }
2964 :
2965 0 : static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2966 : {
2967 : struct pci_dev *host_bridge;
2968 : int pos;
2969 : int found;
2970 :
2971 0 : if (!pci_msi_enabled())
2972 : return;
2973 :
2974 : /* check if there is HT MSI cap or enabled on this device */
2975 0 : found = ht_check_msi_mapping(dev);
2976 :
2977 : /* no HT MSI CAP */
2978 0 : if (found == 0)
2979 : return;
2980 :
2981 : /*
2982 : * HT MSI mapping should be disabled on devices that are below
2983 : * a non-Hypertransport host bridge. Locate the host bridge...
2984 : */
2985 0 : host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2986 : PCI_DEVFN(0, 0));
2987 0 : if (host_bridge == NULL) {
2988 0 : pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2989 0 : return;
2990 : }
2991 :
2992 0 : pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2993 0 : if (pos != 0) {
2994 : /* Host bridge is to HT */
2995 0 : if (found == 1) {
2996 : /* it is not enabled, try to enable it */
2997 0 : if (all)
2998 0 : ht_enable_msi_mapping(dev);
2999 : else
3000 0 : nv_ht_enable_msi_mapping(dev);
3001 : }
3002 : goto out;
3003 : }
3004 :
3005 : /* HT MSI is not enabled */
3006 0 : if (found == 1)
3007 : goto out;
3008 :
3009 : /* Host bridge is not to HT, disable HT MSI mapping on this device */
3010 0 : ht_disable_msi_mapping(dev);
3011 :
3012 : out:
3013 0 : pci_dev_put(host_bridge);
3014 : }
3015 :
3016 0 : static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
3017 : {
3018 0 : return __nv_msi_ht_cap_quirk(dev, 1);
3019 : }
3020 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
3021 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
3022 :
3023 0 : static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
3024 : {
3025 0 : return __nv_msi_ht_cap_quirk(dev, 0);
3026 : }
3027 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
3028 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
3029 :
3030 0 : static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
3031 : {
3032 0 : dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3033 0 : }
3034 :
3035 0 : static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
3036 : {
3037 : struct pci_dev *p;
3038 :
3039 : /*
3040 : * SB700 MSI issue will be fixed at HW level from revision A21;
3041 : * we need check PCI REVISION ID of SMBus controller to get SB700
3042 : * revision.
3043 : */
3044 0 : p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3045 : NULL);
3046 0 : if (!p)
3047 : return;
3048 :
3049 0 : if ((p->revision < 0x3B) && (p->revision >= 0x30))
3050 0 : dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3051 0 : pci_dev_put(p);
3052 : }
3053 :
3054 0 : static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
3055 : {
3056 : /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
3057 0 : if (dev->revision < 0x18) {
3058 0 : pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
3059 0 : dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3060 : }
3061 0 : }
3062 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3063 : PCI_DEVICE_ID_TIGON3_5780,
3064 : quirk_msi_intx_disable_bug);
3065 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3066 : PCI_DEVICE_ID_TIGON3_5780S,
3067 : quirk_msi_intx_disable_bug);
3068 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3069 : PCI_DEVICE_ID_TIGON3_5714,
3070 : quirk_msi_intx_disable_bug);
3071 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3072 : PCI_DEVICE_ID_TIGON3_5714S,
3073 : quirk_msi_intx_disable_bug);
3074 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3075 : PCI_DEVICE_ID_TIGON3_5715,
3076 : quirk_msi_intx_disable_bug);
3077 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3078 : PCI_DEVICE_ID_TIGON3_5715S,
3079 : quirk_msi_intx_disable_bug);
3080 :
3081 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3082 : quirk_msi_intx_disable_ati_bug);
3083 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3084 : quirk_msi_intx_disable_ati_bug);
3085 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3086 : quirk_msi_intx_disable_ati_bug);
3087 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3088 : quirk_msi_intx_disable_ati_bug);
3089 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3090 : quirk_msi_intx_disable_ati_bug);
3091 :
3092 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3093 : quirk_msi_intx_disable_bug);
3094 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3095 : quirk_msi_intx_disable_bug);
3096 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3097 : quirk_msi_intx_disable_bug);
3098 :
3099 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3100 : quirk_msi_intx_disable_bug);
3101 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3102 : quirk_msi_intx_disable_bug);
3103 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3104 : quirk_msi_intx_disable_bug);
3105 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3106 : quirk_msi_intx_disable_bug);
3107 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3108 : quirk_msi_intx_disable_bug);
3109 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3110 : quirk_msi_intx_disable_bug);
3111 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3112 : quirk_msi_intx_disable_qca_bug);
3113 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3114 : quirk_msi_intx_disable_qca_bug);
3115 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3116 : quirk_msi_intx_disable_qca_bug);
3117 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3118 : quirk_msi_intx_disable_qca_bug);
3119 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3120 : quirk_msi_intx_disable_qca_bug);
3121 :
3122 : /*
3123 : * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3124 : * should be disabled on platforms where the device (mistakenly) advertises it.
3125 : *
3126 : * Notice that this quirk also disables MSI (which may work, but hasn't been
3127 : * tested), since currently there is no standard way to disable only MSI-X.
3128 : *
3129 : * The 0031 device id is reused for other non Root Port device types,
3130 : * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3131 : */
3132 0 : static void quirk_al_msi_disable(struct pci_dev *dev)
3133 : {
3134 0 : dev->no_msi = 1;
3135 0 : pci_warn(dev, "Disabling MSI/MSI-X\n");
3136 0 : }
3137 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3138 : PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
3139 : #endif /* CONFIG_PCI_MSI */
3140 :
3141 : /*
3142 : * Allow manual resource allocation for PCI hotplug bridges via
3143 : * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3144 : * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3145 : * allocate resources when hotplug device is inserted and PCI bus is
3146 : * rescanned.
3147 : */
3148 0 : static void quirk_hotplug_bridge(struct pci_dev *dev)
3149 : {
3150 0 : dev->is_hotplug_bridge = 1;
3151 0 : }
3152 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3153 :
3154 : /*
3155 : * This is a quirk for the Ricoh MMC controller found as a part of some
3156 : * multifunction chips.
3157 : *
3158 : * This is very similar and based on the ricoh_mmc driver written by
3159 : * Philip Langdale. Thank you for these magic sequences.
3160 : *
3161 : * These chips implement the four main memory card controllers (SD, MMC,
3162 : * MS, xD) and one or both of CardBus or FireWire.
3163 : *
3164 : * It happens that they implement SD and MMC support as separate
3165 : * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3166 : * cards but the chip detects MMC cards in hardware and directs them to the
3167 : * MMC controller - so the SDHCI driver never sees them.
3168 : *
3169 : * To get around this, we must disable the useless MMC controller. At that
3170 : * point, the SDHCI controller will start seeing them. It seems to be the
3171 : * case that the relevant PCI registers to deactivate the MMC controller
3172 : * live on PCI function 0, which might be the CardBus controller or the
3173 : * FireWire controller, depending on the particular chip in question
3174 : *
3175 : * This has to be done early, because as soon as we disable the MMC controller
3176 : * other PCI functions shift up one level, e.g. function #2 becomes function
3177 : * #1, and this will confuse the PCI core.
3178 : */
3179 : #ifdef CONFIG_MMC_RICOH_MMC
3180 : static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3181 : {
3182 : u8 write_enable;
3183 : u8 write_target;
3184 : u8 disable;
3185 :
3186 : /*
3187 : * Disable via CardBus interface
3188 : *
3189 : * This must be done via function #0
3190 : */
3191 : if (PCI_FUNC(dev->devfn))
3192 : return;
3193 :
3194 : pci_read_config_byte(dev, 0xB7, &disable);
3195 : if (disable & 0x02)
3196 : return;
3197 :
3198 : pci_read_config_byte(dev, 0x8E, &write_enable);
3199 : pci_write_config_byte(dev, 0x8E, 0xAA);
3200 : pci_read_config_byte(dev, 0x8D, &write_target);
3201 : pci_write_config_byte(dev, 0x8D, 0xB7);
3202 : pci_write_config_byte(dev, 0xB7, disable | 0x02);
3203 : pci_write_config_byte(dev, 0x8E, write_enable);
3204 : pci_write_config_byte(dev, 0x8D, write_target);
3205 :
3206 : pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3207 : pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3208 : }
3209 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3210 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3211 :
3212 : static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3213 : {
3214 : u8 write_enable;
3215 : u8 disable;
3216 :
3217 : /*
3218 : * Disable via FireWire interface
3219 : *
3220 : * This must be done via function #0
3221 : */
3222 : if (PCI_FUNC(dev->devfn))
3223 : return;
3224 : /*
3225 : * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3226 : * certain types of SD/MMC cards. Lowering the SD base clock
3227 : * frequency from 200Mhz to 50Mhz fixes this issue.
3228 : *
3229 : * 0x150 - SD2.0 mode enable for changing base clock
3230 : * frequency to 50Mhz
3231 : * 0xe1 - Base clock frequency
3232 : * 0x32 - 50Mhz new clock frequency
3233 : * 0xf9 - Key register for 0x150
3234 : * 0xfc - key register for 0xe1
3235 : */
3236 : if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3237 : dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3238 : pci_write_config_byte(dev, 0xf9, 0xfc);
3239 : pci_write_config_byte(dev, 0x150, 0x10);
3240 : pci_write_config_byte(dev, 0xf9, 0x00);
3241 : pci_write_config_byte(dev, 0xfc, 0x01);
3242 : pci_write_config_byte(dev, 0xe1, 0x32);
3243 : pci_write_config_byte(dev, 0xfc, 0x00);
3244 :
3245 : pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3246 : }
3247 :
3248 : pci_read_config_byte(dev, 0xCB, &disable);
3249 :
3250 : if (disable & 0x02)
3251 : return;
3252 :
3253 : pci_read_config_byte(dev, 0xCA, &write_enable);
3254 : pci_write_config_byte(dev, 0xCA, 0x57);
3255 : pci_write_config_byte(dev, 0xCB, disable | 0x02);
3256 : pci_write_config_byte(dev, 0xCA, write_enable);
3257 :
3258 : pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3259 : pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3260 :
3261 : }
3262 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3263 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3264 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3265 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3266 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3267 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3268 : #endif /*CONFIG_MMC_RICOH_MMC*/
3269 :
3270 : #ifdef CONFIG_DMAR_TABLE
3271 : #define VTUNCERRMSK_REG 0x1ac
3272 : #define VTD_MSK_SPEC_ERRORS (1 << 31)
3273 : /*
3274 : * This is a quirk for masking VT-d spec-defined errors to platform error
3275 : * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3276 : * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3277 : * on the RAS config settings of the platform) when a VT-d fault happens.
3278 : * The resulting SMI caused the system to hang.
3279 : *
3280 : * VT-d spec-related errors are already handled by the VT-d OS code, so no
3281 : * need to report the same error through other channels.
3282 : */
3283 : static void vtd_mask_spec_errors(struct pci_dev *dev)
3284 : {
3285 : u32 word;
3286 :
3287 : pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3288 : pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3289 : }
3290 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3291 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3292 : #endif
3293 :
3294 0 : static void fixup_ti816x_class(struct pci_dev *dev)
3295 : {
3296 0 : u32 class = dev->class;
3297 :
3298 : /* TI 816x devices do not have class code set when in PCIe boot mode */
3299 0 : dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3300 0 : pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3301 : class, dev->class);
3302 0 : }
3303 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3304 : PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3305 :
3306 : /*
3307 : * Some PCIe devices do not work reliably with the claimed maximum
3308 : * payload size supported.
3309 : */
3310 0 : static void fixup_mpss_256(struct pci_dev *dev)
3311 : {
3312 0 : dev->pcie_mpss = 1; /* 256 bytes */
3313 0 : }
3314 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3315 : PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3316 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3317 : PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3318 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3319 : PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3320 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3321 :
3322 : /*
3323 : * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3324 : * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3325 : * Since there is no way of knowing what the PCIe MPS on each fabric will be
3326 : * until all of the devices are discovered and buses walked, read completion
3327 : * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3328 : * it is possible to hotplug a device with MPS of 256B.
3329 : */
3330 0 : static void quirk_intel_mc_errata(struct pci_dev *dev)
3331 : {
3332 : int err;
3333 : u16 rcc;
3334 :
3335 0 : if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3336 : pcie_bus_config == PCIE_BUS_DEFAULT)
3337 0 : return;
3338 :
3339 : /*
3340 : * Intel erratum specifies bits to change but does not say what
3341 : * they are. Keeping them magical until such time as the registers
3342 : * and values can be explained.
3343 : */
3344 0 : err = pci_read_config_word(dev, 0x48, &rcc);
3345 0 : if (err) {
3346 0 : pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3347 0 : return;
3348 : }
3349 :
3350 0 : if (!(rcc & (1 << 10)))
3351 : return;
3352 :
3353 0 : rcc &= ~(1 << 10);
3354 :
3355 0 : err = pci_write_config_word(dev, 0x48, rcc);
3356 0 : if (err) {
3357 0 : pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3358 0 : return;
3359 : }
3360 :
3361 0 : pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3362 : }
3363 : /* Intel 5000 series memory controllers and ports 2-7 */
3364 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3365 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3366 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3367 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3368 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3369 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3370 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3371 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3372 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3373 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3374 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3375 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3376 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3377 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3378 : /* Intel 5100 series memory controllers and ports 2-7 */
3379 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3380 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3381 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3382 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3383 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3384 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3385 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3386 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3387 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3388 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3389 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3390 :
3391 : /*
3392 : * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3393 : * To work around this, query the size it should be configured to by the
3394 : * device and modify the resource end to correspond to this new size.
3395 : */
3396 0 : static void quirk_intel_ntb(struct pci_dev *dev)
3397 : {
3398 : int rc;
3399 : u8 val;
3400 :
3401 0 : rc = pci_read_config_byte(dev, 0x00D0, &val);
3402 0 : if (rc)
3403 0 : return;
3404 :
3405 0 : dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3406 :
3407 0 : rc = pci_read_config_byte(dev, 0x00D1, &val);
3408 0 : if (rc)
3409 : return;
3410 :
3411 0 : dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3412 : }
3413 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3414 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3415 :
3416 : /*
3417 : * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3418 : * though no one is handling them (e.g., if the i915 driver is never
3419 : * loaded). Additionally the interrupt destination is not set up properly
3420 : * and the interrupt ends up -somewhere-.
3421 : *
3422 : * These spurious interrupts are "sticky" and the kernel disables the
3423 : * (shared) interrupt line after 100,000+ generated interrupts.
3424 : *
3425 : * Fix it by disabling the still enabled interrupts. This resolves crashes
3426 : * often seen on monitor unplug.
3427 : */
3428 : #define I915_DEIER_REG 0x4400c
3429 0 : static void disable_igfx_irq(struct pci_dev *dev)
3430 : {
3431 0 : void __iomem *regs = pci_iomap(dev, 0, 0);
3432 0 : if (regs == NULL) {
3433 0 : pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3434 0 : return;
3435 : }
3436 :
3437 : /* Check if any interrupt line is still enabled */
3438 0 : if (readl(regs + I915_DEIER_REG) != 0) {
3439 0 : pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3440 :
3441 0 : writel(0, regs + I915_DEIER_REG);
3442 : }
3443 :
3444 0 : pci_iounmap(dev, regs);
3445 : }
3446 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3447 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3448 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3449 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3450 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3451 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3452 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3453 :
3454 : /*
3455 : * PCI devices which are on Intel chips can skip the 10ms delay
3456 : * before entering D3 mode.
3457 : */
3458 0 : static void quirk_remove_d3hot_delay(struct pci_dev *dev)
3459 : {
3460 0 : dev->d3hot_delay = 0;
3461 0 : }
3462 : /* C600 Series devices do not need 10ms d3hot_delay */
3463 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3464 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3465 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3466 : /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3467 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3468 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3469 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3470 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3471 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3472 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3473 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3474 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3475 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3476 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3477 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3478 : /* Intel Cherrytrail devices do not need 10ms d3hot_delay */
3479 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3480 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3481 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3482 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3483 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3484 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3485 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3486 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3487 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3488 :
3489 : /*
3490 : * Some devices may pass our check in pci_intx_mask_supported() if
3491 : * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3492 : * support this feature.
3493 : */
3494 0 : static void quirk_broken_intx_masking(struct pci_dev *dev)
3495 : {
3496 0 : dev->broken_intx_masking = 1;
3497 0 : }
3498 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3499 : quirk_broken_intx_masking);
3500 : DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3501 : quirk_broken_intx_masking);
3502 : DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3503 : quirk_broken_intx_masking);
3504 :
3505 : /*
3506 : * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3507 : * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3508 : *
3509 : * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3510 : */
3511 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3512 : quirk_broken_intx_masking);
3513 :
3514 : /*
3515 : * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3516 : * DisINTx can be set but the interrupt status bit is non-functional.
3517 : */
3518 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3519 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3520 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3521 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3522 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3523 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3524 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3525 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3526 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3527 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3528 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3529 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3530 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3531 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3532 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3533 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3534 :
3535 : static u16 mellanox_broken_intx_devs[] = {
3536 : PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3537 : PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3538 : PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3539 : PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3540 : PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3541 : PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3542 : PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3543 : PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3544 : PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3545 : PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3546 : PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3547 : PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3548 : PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3549 : PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3550 : };
3551 :
3552 : #define CONNECTX_4_CURR_MAX_MINOR 99
3553 : #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3554 :
3555 : /*
3556 : * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3557 : * If so, don't mark it as broken.
3558 : * FW minor > 99 means older FW version format and no INTx masking support.
3559 : * FW minor < 14 means new FW version format and no INTx masking support.
3560 : */
3561 0 : static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3562 : {
3563 : __be32 __iomem *fw_ver;
3564 : u16 fw_major;
3565 : u16 fw_minor;
3566 : u16 fw_subminor;
3567 : u32 fw_maj_min;
3568 : u32 fw_sub_min;
3569 : int i;
3570 :
3571 0 : for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3572 0 : if (pdev->device == mellanox_broken_intx_devs[i]) {
3573 0 : pdev->broken_intx_masking = 1;
3574 0 : return;
3575 : }
3576 : }
3577 :
3578 : /*
3579 : * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3580 : * support so shouldn't be checked further
3581 : */
3582 0 : if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3583 : return;
3584 :
3585 0 : if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3586 : pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3587 : return;
3588 :
3589 : /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3590 0 : if (pci_enable_device_mem(pdev)) {
3591 0 : pci_warn(pdev, "Can't enable device memory\n");
3592 0 : return;
3593 : }
3594 :
3595 0 : fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3596 0 : if (!fw_ver) {
3597 0 : pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3598 0 : goto out;
3599 : }
3600 :
3601 : /* Reading from resource space should be 32b aligned */
3602 0 : fw_maj_min = ioread32be(fw_ver);
3603 0 : fw_sub_min = ioread32be(fw_ver + 1);
3604 0 : fw_major = fw_maj_min & 0xffff;
3605 0 : fw_minor = fw_maj_min >> 16;
3606 0 : fw_subminor = fw_sub_min & 0xffff;
3607 0 : if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3608 : fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3609 0 : pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3610 : fw_major, fw_minor, fw_subminor, pdev->device ==
3611 : PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3612 0 : pdev->broken_intx_masking = 1;
3613 : }
3614 :
3615 0 : iounmap(fw_ver);
3616 :
3617 : out:
3618 0 : pci_disable_device(pdev);
3619 : }
3620 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3621 : mellanox_check_broken_intx_masking);
3622 :
3623 0 : static void quirk_no_bus_reset(struct pci_dev *dev)
3624 : {
3625 0 : dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3626 0 : }
3627 :
3628 : /*
3629 : * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3630 : * prevented for those affected devices.
3631 : */
3632 0 : static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3633 : {
3634 0 : if ((dev->device & 0xffc0) == 0x2340)
3635 : quirk_no_bus_reset(dev);
3636 0 : }
3637 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3638 : quirk_nvidia_no_bus_reset);
3639 :
3640 : /*
3641 : * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3642 : * The device will throw a Link Down error on AER-capable systems and
3643 : * regardless of AER, config space of the device is never accessible again
3644 : * and typically causes the system to hang or reset when access is attempted.
3645 : * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
3646 : */
3647 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3648 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3649 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3650 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3651 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3652 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3653 :
3654 : /*
3655 : * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3656 : * reset when used with certain child devices. After the reset, config
3657 : * accesses to the child may fail.
3658 : */
3659 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3660 :
3661 : /*
3662 : * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3663 : * automatically disables LTSSM when Secondary Bus Reset is received and
3664 : * the device stops working. Prevent bus reset for these devices. With
3665 : * this change, the device can be assigned to VMs with VFIO, but it will
3666 : * leak state between VMs. Reference
3667 : * https://e2e.ti.com/support/processors/f/791/t/954382
3668 : */
3669 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3670 :
3671 0 : static void quirk_no_pm_reset(struct pci_dev *dev)
3672 : {
3673 : /*
3674 : * We can't do a bus reset on root bus devices, but an ineffective
3675 : * PM reset may be better than nothing.
3676 : */
3677 0 : if (!pci_is_root_bus(dev->bus))
3678 0 : dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3679 0 : }
3680 :
3681 : /*
3682 : * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3683 : * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3684 : * to have no effect on the device: it retains the framebuffer contents and
3685 : * monitor sync. Advertising this support makes other layers, like VFIO,
3686 : * assume pci_reset_function() is viable for this device. Mark it as
3687 : * unavailable to skip it when testing reset methods.
3688 : */
3689 : DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3690 : PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3691 :
3692 : /*
3693 : * Thunderbolt controllers with broken MSI hotplug signaling:
3694 : * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3695 : * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3696 : */
3697 0 : static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3698 : {
3699 0 : if (pdev->is_hotplug_bridge &&
3700 0 : (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3701 0 : pdev->revision <= 1))
3702 0 : pdev->no_msi = 1;
3703 0 : }
3704 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3705 : quirk_thunderbolt_hotplug_msi);
3706 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3707 : quirk_thunderbolt_hotplug_msi);
3708 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3709 : quirk_thunderbolt_hotplug_msi);
3710 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3711 : quirk_thunderbolt_hotplug_msi);
3712 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3713 : quirk_thunderbolt_hotplug_msi);
3714 :
3715 : #ifdef CONFIG_ACPI
3716 : /*
3717 : * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3718 : *
3719 : * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3720 : * shutdown before suspend. Otherwise the native host interface (NHI) will not
3721 : * be present after resume if a device was plugged in before suspend.
3722 : *
3723 : * The Thunderbolt controller consists of a PCIe switch with downstream
3724 : * bridges leading to the NHI and to the tunnel PCI bridges.
3725 : *
3726 : * This quirk cuts power to the whole chip. Therefore we have to apply it
3727 : * during suspend_noirq of the upstream bridge.
3728 : *
3729 : * Power is automagically restored before resume. No action is needed.
3730 : */
3731 : static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3732 : {
3733 : acpi_handle bridge, SXIO, SXFP, SXLV;
3734 :
3735 : if (!x86_apple_machine)
3736 : return;
3737 : if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3738 : return;
3739 :
3740 : /*
3741 : * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
3742 : * We don't know how to turn it back on again, but firmware does,
3743 : * so we can only use SXIO/SXFP/SXLF if we're suspending via
3744 : * firmware.
3745 : */
3746 : if (!pm_suspend_via_firmware())
3747 : return;
3748 :
3749 : bridge = ACPI_HANDLE(&dev->dev);
3750 : if (!bridge)
3751 : return;
3752 :
3753 : /*
3754 : * SXIO and SXLV are present only on machines requiring this quirk.
3755 : * Thunderbolt bridges in external devices might have the same
3756 : * device ID as those on the host, but they will not have the
3757 : * associated ACPI methods. This implicitly checks that we are at
3758 : * the right bridge.
3759 : */
3760 : if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3761 : || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3762 : || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3763 : return;
3764 : pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3765 :
3766 : /* magic sequence */
3767 : acpi_execute_simple_method(SXIO, NULL, 1);
3768 : acpi_execute_simple_method(SXFP, NULL, 0);
3769 : msleep(300);
3770 : acpi_execute_simple_method(SXLV, NULL, 0);
3771 : acpi_execute_simple_method(SXIO, NULL, 0);
3772 : acpi_execute_simple_method(SXLV, NULL, 0);
3773 : }
3774 : DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3775 : PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3776 : quirk_apple_poweroff_thunderbolt);
3777 : #endif
3778 :
3779 : /*
3780 : * Following are device-specific reset methods which can be used to
3781 : * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3782 : * not available.
3783 : */
3784 0 : static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe)
3785 : {
3786 : /*
3787 : * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3788 : *
3789 : * The 82599 supports FLR on VFs, but FLR support is reported only
3790 : * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3791 : * Thus we must call pcie_flr() directly without first checking if it is
3792 : * supported.
3793 : */
3794 0 : if (!probe)
3795 0 : pcie_flr(dev);
3796 0 : return 0;
3797 : }
3798 :
3799 : #define SOUTH_CHICKEN2 0xc2004
3800 : #define PCH_PP_STATUS 0xc7200
3801 : #define PCH_PP_CONTROL 0xc7204
3802 : #define MSG_CTL 0x45010
3803 : #define NSDE_PWR_STATE 0xd0100
3804 : #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3805 :
3806 0 : static int reset_ivb_igd(struct pci_dev *dev, bool probe)
3807 : {
3808 : void __iomem *mmio_base;
3809 : unsigned long timeout;
3810 : u32 val;
3811 :
3812 0 : if (probe)
3813 : return 0;
3814 :
3815 0 : mmio_base = pci_iomap(dev, 0, 0);
3816 0 : if (!mmio_base)
3817 : return -ENOMEM;
3818 :
3819 0 : iowrite32(0x00000002, mmio_base + MSG_CTL);
3820 :
3821 : /*
3822 : * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3823 : * driver loaded sets the right bits. However, this's a reset and
3824 : * the bits have been set by i915 previously, so we clobber
3825 : * SOUTH_CHICKEN2 register directly here.
3826 : */
3827 0 : iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3828 :
3829 0 : val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3830 0 : iowrite32(val, mmio_base + PCH_PP_CONTROL);
3831 :
3832 0 : timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3833 : do {
3834 0 : val = ioread32(mmio_base + PCH_PP_STATUS);
3835 0 : if ((val & 0xb0000000) == 0)
3836 : goto reset_complete;
3837 0 : msleep(10);
3838 0 : } while (time_before(jiffies, timeout));
3839 0 : pci_warn(dev, "timeout during reset\n");
3840 :
3841 : reset_complete:
3842 0 : iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3843 :
3844 0 : pci_iounmap(dev, mmio_base);
3845 0 : return 0;
3846 : }
3847 :
3848 : /* Device-specific reset method for Chelsio T4-based adapters */
3849 0 : static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)
3850 : {
3851 : u16 old_command;
3852 : u16 msix_flags;
3853 :
3854 : /*
3855 : * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3856 : * that we have no device-specific reset method.
3857 : */
3858 0 : if ((dev->device & 0xf000) != 0x4000)
3859 : return -ENOTTY;
3860 :
3861 : /*
3862 : * If this is the "probe" phase, return 0 indicating that we can
3863 : * reset this device.
3864 : */
3865 0 : if (probe)
3866 : return 0;
3867 :
3868 : /*
3869 : * T4 can wedge if there are DMAs in flight within the chip and Bus
3870 : * Master has been disabled. We need to have it on till the Function
3871 : * Level Reset completes. (BUS_MASTER is disabled in
3872 : * pci_reset_function()).
3873 : */
3874 0 : pci_read_config_word(dev, PCI_COMMAND, &old_command);
3875 0 : pci_write_config_word(dev, PCI_COMMAND,
3876 : old_command | PCI_COMMAND_MASTER);
3877 :
3878 : /*
3879 : * Perform the actual device function reset, saving and restoring
3880 : * configuration information around the reset.
3881 : */
3882 0 : pci_save_state(dev);
3883 :
3884 : /*
3885 : * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3886 : * are disabled when an MSI-X interrupt message needs to be delivered.
3887 : * So we briefly re-enable MSI-X interrupts for the duration of the
3888 : * FLR. The pci_restore_state() below will restore the original
3889 : * MSI-X state.
3890 : */
3891 0 : pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3892 0 : if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3893 0 : pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3894 : msix_flags |
3895 : PCI_MSIX_FLAGS_ENABLE |
3896 : PCI_MSIX_FLAGS_MASKALL);
3897 :
3898 0 : pcie_flr(dev);
3899 :
3900 : /*
3901 : * Restore the configuration information (BAR values, etc.) including
3902 : * the original PCI Configuration Space Command word, and return
3903 : * success.
3904 : */
3905 0 : pci_restore_state(dev);
3906 0 : pci_write_config_word(dev, PCI_COMMAND, old_command);
3907 0 : return 0;
3908 : }
3909 :
3910 : #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3911 : #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3912 : #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3913 :
3914 : /*
3915 : * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3916 : * FLR where config space reads from the device return -1. We seem to be
3917 : * able to avoid this condition if we disable the NVMe controller prior to
3918 : * FLR. This quirk is generic for any NVMe class device requiring similar
3919 : * assistance to quiesce the device prior to FLR.
3920 : *
3921 : * NVMe specification: https://nvmexpress.org/resources/specifications/
3922 : * Revision 1.0e:
3923 : * Chapter 2: Required and optional PCI config registers
3924 : * Chapter 3: NVMe control registers
3925 : * Chapter 7.3: Reset behavior
3926 : */
3927 0 : static int nvme_disable_and_flr(struct pci_dev *dev, bool probe)
3928 : {
3929 : void __iomem *bar;
3930 : u16 cmd;
3931 : u32 cfg;
3932 :
3933 0 : if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3934 0 : pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0))
3935 : return -ENOTTY;
3936 :
3937 0 : if (probe)
3938 : return 0;
3939 :
3940 0 : bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3941 0 : if (!bar)
3942 : return -ENOTTY;
3943 :
3944 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
3945 0 : pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3946 :
3947 0 : cfg = readl(bar + NVME_REG_CC);
3948 :
3949 : /* Disable controller if enabled */
3950 0 : if (cfg & NVME_CC_ENABLE) {
3951 0 : u32 cap = readl(bar + NVME_REG_CAP);
3952 : unsigned long timeout;
3953 :
3954 : /*
3955 : * Per nvme_disable_ctrl() skip shutdown notification as it
3956 : * could complete commands to the admin queue. We only intend
3957 : * to quiesce the device before reset.
3958 : */
3959 0 : cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3960 :
3961 0 : writel(cfg, bar + NVME_REG_CC);
3962 :
3963 : /*
3964 : * Some controllers require an additional delay here, see
3965 : * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3966 : * supported by this quirk.
3967 : */
3968 :
3969 : /* Cap register provides max timeout in 500ms increments */
3970 0 : timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3971 :
3972 : for (;;) {
3973 0 : u32 status = readl(bar + NVME_REG_CSTS);
3974 :
3975 : /* Ready status becomes zero on disable complete */
3976 0 : if (!(status & NVME_CSTS_RDY))
3977 : break;
3978 :
3979 0 : msleep(100);
3980 :
3981 0 : if (time_after(jiffies, timeout)) {
3982 0 : pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3983 0 : break;
3984 : }
3985 : }
3986 : }
3987 :
3988 0 : pci_iounmap(dev, bar);
3989 :
3990 0 : pcie_flr(dev);
3991 :
3992 0 : return 0;
3993 : }
3994 :
3995 : /*
3996 : * Intel DC P3700 NVMe controller will timeout waiting for ready status
3997 : * to change after NVMe enable if the driver starts interacting with the
3998 : * device too soon after FLR. A 250ms delay after FLR has heuristically
3999 : * proven to produce reliably working results for device assignment cases.
4000 : */
4001 0 : static int delay_250ms_after_flr(struct pci_dev *dev, bool probe)
4002 : {
4003 0 : if (probe)
4004 0 : return pcie_reset_flr(dev, PCI_RESET_PROBE);
4005 :
4006 0 : pcie_reset_flr(dev, PCI_RESET_DO_RESET);
4007 :
4008 0 : msleep(250);
4009 :
4010 0 : return 0;
4011 : }
4012 :
4013 : #define PCI_DEVICE_ID_HINIC_VF 0x375E
4014 : #define HINIC_VF_FLR_TYPE 0x1000
4015 : #define HINIC_VF_FLR_CAP_BIT (1UL << 30)
4016 : #define HINIC_VF_OP 0xE80
4017 : #define HINIC_VF_FLR_PROC_BIT (1UL << 18)
4018 : #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
4019 :
4020 : /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
4021 0 : static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe)
4022 : {
4023 : unsigned long timeout;
4024 : void __iomem *bar;
4025 : u32 val;
4026 :
4027 0 : if (probe)
4028 : return 0;
4029 :
4030 0 : bar = pci_iomap(pdev, 0, 0);
4031 0 : if (!bar)
4032 : return -ENOTTY;
4033 :
4034 : /* Get and check firmware capabilities */
4035 0 : val = ioread32be(bar + HINIC_VF_FLR_TYPE);
4036 0 : if (!(val & HINIC_VF_FLR_CAP_BIT)) {
4037 0 : pci_iounmap(pdev, bar);
4038 0 : return -ENOTTY;
4039 : }
4040 :
4041 : /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
4042 0 : val = ioread32be(bar + HINIC_VF_OP);
4043 0 : val = val | HINIC_VF_FLR_PROC_BIT;
4044 0 : iowrite32be(val, bar + HINIC_VF_OP);
4045 :
4046 0 : pcie_flr(pdev);
4047 :
4048 : /*
4049 : * The device must recapture its Bus and Device Numbers after FLR
4050 : * in order generate Completions. Issue a config write to let the
4051 : * device capture this information.
4052 : */
4053 0 : pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
4054 :
4055 : /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
4056 0 : timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
4057 : do {
4058 0 : val = ioread32be(bar + HINIC_VF_OP);
4059 0 : if (!(val & HINIC_VF_FLR_PROC_BIT))
4060 : goto reset_complete;
4061 0 : msleep(20);
4062 0 : } while (time_before(jiffies, timeout));
4063 :
4064 0 : val = ioread32be(bar + HINIC_VF_OP);
4065 0 : if (!(val & HINIC_VF_FLR_PROC_BIT))
4066 : goto reset_complete;
4067 :
4068 0 : pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
4069 :
4070 : reset_complete:
4071 0 : pci_iounmap(pdev, bar);
4072 :
4073 0 : return 0;
4074 : }
4075 :
4076 : static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
4077 : { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
4078 : reset_intel_82599_sfp_virtfn },
4079 : { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
4080 : reset_ivb_igd },
4081 : { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
4082 : reset_ivb_igd },
4083 : { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4084 : { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4085 : { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr },
4086 : { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4087 : reset_chelsio_generic_dev },
4088 : { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
4089 : reset_hinic_vf_dev },
4090 : { 0 }
4091 : };
4092 :
4093 : /*
4094 : * These device-specific reset methods are here rather than in a driver
4095 : * because when a host assigns a device to a guest VM, the host may need
4096 : * to reset the device but probably doesn't have a driver for it.
4097 : */
4098 0 : int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
4099 : {
4100 : const struct pci_dev_reset_methods *i;
4101 :
4102 0 : for (i = pci_dev_reset_methods; i->reset; i++) {
4103 0 : if ((i->vendor == dev->vendor ||
4104 0 : i->vendor == (u16)PCI_ANY_ID) &&
4105 0 : (i->device == dev->device ||
4106 : i->device == (u16)PCI_ANY_ID))
4107 0 : return i->reset(dev, probe);
4108 : }
4109 :
4110 : return -ENOTTY;
4111 : }
4112 :
4113 0 : static void quirk_dma_func0_alias(struct pci_dev *dev)
4114 : {
4115 0 : if (PCI_FUNC(dev->devfn) != 0)
4116 0 : pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
4117 0 : }
4118 :
4119 : /*
4120 : * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4121 : *
4122 : * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4123 : */
4124 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4125 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4126 :
4127 0 : static void quirk_dma_func1_alias(struct pci_dev *dev)
4128 : {
4129 0 : if (PCI_FUNC(dev->devfn) != 1)
4130 0 : pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
4131 0 : }
4132 :
4133 : /*
4134 : * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4135 : * SKUs function 1 is present and is a legacy IDE controller, in other
4136 : * SKUs this function is not present, making this a ghost requester.
4137 : * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4138 : */
4139 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4140 : quirk_dma_func1_alias);
4141 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4142 : quirk_dma_func1_alias);
4143 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */
4144 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4145 : quirk_dma_func1_alias);
4146 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4147 : quirk_dma_func1_alias);
4148 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4149 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4150 : quirk_dma_func1_alias);
4151 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4152 : quirk_dma_func1_alias);
4153 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4154 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4155 : quirk_dma_func1_alias);
4156 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4157 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4158 : quirk_dma_func1_alias);
4159 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4160 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4161 : quirk_dma_func1_alias);
4162 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4163 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4164 : quirk_dma_func1_alias);
4165 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4166 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4167 : quirk_dma_func1_alias);
4168 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4169 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4170 : quirk_dma_func1_alias);
4171 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4172 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4173 : quirk_dma_func1_alias);
4174 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4175 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4176 : quirk_dma_func1_alias);
4177 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4178 : quirk_dma_func1_alias);
4179 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4180 : quirk_dma_func1_alias);
4181 : /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4182 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4183 : PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4184 : quirk_dma_func1_alias);
4185 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4186 : DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4187 : 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4188 : quirk_dma_func1_alias);
4189 :
4190 : /*
4191 : * Some devices DMA with the wrong devfn, not just the wrong function.
4192 : * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4193 : * the alias is "fixed" and independent of the device devfn.
4194 : *
4195 : * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4196 : * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4197 : * single device on the secondary bus. In reality, the single exposed
4198 : * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4199 : * that provides a bridge to the internal bus of the I/O processor. The
4200 : * controller supports private devices, which can be hidden from PCI config
4201 : * space. In the case of the Adaptec 3405, a private device at 01.0
4202 : * appears to be the DMA engine, which therefore needs to become a DMA
4203 : * alias for the device.
4204 : */
4205 : static const struct pci_device_id fixed_dma_alias_tbl[] = {
4206 : { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4207 : PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4208 : .driver_data = PCI_DEVFN(1, 0) },
4209 : { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4210 : PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4211 : .driver_data = PCI_DEVFN(1, 0) },
4212 : { 0 }
4213 : };
4214 :
4215 0 : static void quirk_fixed_dma_alias(struct pci_dev *dev)
4216 : {
4217 : const struct pci_device_id *id;
4218 :
4219 0 : id = pci_match_id(fixed_dma_alias_tbl, dev);
4220 0 : if (id)
4221 0 : pci_add_dma_alias(dev, id->driver_data, 1);
4222 0 : }
4223 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4224 :
4225 : /*
4226 : * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4227 : * using the wrong DMA alias for the device. Some of these devices can be
4228 : * used as either forward or reverse bridges, so we need to test whether the
4229 : * device is operating in the correct mode. We could probably apply this
4230 : * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4231 : * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4232 : * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4233 : */
4234 0 : static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4235 : {
4236 0 : if (!pci_is_root_bus(pdev->bus) &&
4237 0 : pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4238 0 : !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4239 0 : pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4240 0 : pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4241 0 : }
4242 : /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4243 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4244 : quirk_use_pcie_bridge_dma_alias);
4245 : /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4246 : DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4247 : /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4248 : DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4249 : /* ITE 8893 has the same problem as the 8892 */
4250 : DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4251 : /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4252 : DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4253 :
4254 : /*
4255 : * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4256 : * be added as aliases to the DMA device in order to allow buffer access
4257 : * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4258 : * programmed in the EEPROM.
4259 : */
4260 0 : static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4261 : {
4262 0 : pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4263 0 : pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4264 0 : pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
4265 0 : }
4266 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4267 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4268 :
4269 : /*
4270 : * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4271 : * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4272 : *
4273 : * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4274 : * when IOMMU is enabled. These aliases allow computational unit access to
4275 : * host memory. These aliases mark the whole VCA device as one IOMMU
4276 : * group.
4277 : *
4278 : * All possible slot numbers (0x20) are used, since we are unable to tell
4279 : * what slot is used on other side. This quirk is intended for both host
4280 : * and computational unit sides. The VCA devices have up to five functions
4281 : * (four for DMA channels and one additional).
4282 : */
4283 0 : static void quirk_pex_vca_alias(struct pci_dev *pdev)
4284 : {
4285 0 : const unsigned int num_pci_slots = 0x20;
4286 : unsigned int slot;
4287 :
4288 0 : for (slot = 0; slot < num_pci_slots; slot++)
4289 0 : pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
4290 0 : }
4291 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4292 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4293 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4294 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4295 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4296 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4297 :
4298 : /*
4299 : * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4300 : * associated not at the root bus, but at a bridge below. This quirk avoids
4301 : * generating invalid DMA aliases.
4302 : */
4303 0 : static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4304 : {
4305 0 : pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4306 0 : }
4307 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4308 : quirk_bridge_cavm_thrx2_pcie_root);
4309 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4310 : quirk_bridge_cavm_thrx2_pcie_root);
4311 :
4312 : /*
4313 : * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4314 : * class code. Fix it.
4315 : */
4316 0 : static void quirk_tw686x_class(struct pci_dev *pdev)
4317 : {
4318 0 : u32 class = pdev->class;
4319 :
4320 : /* Use "Multimedia controller" class */
4321 0 : pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4322 0 : pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4323 : class, pdev->class);
4324 0 : }
4325 : DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4326 : quirk_tw686x_class);
4327 : DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4328 : quirk_tw686x_class);
4329 : DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4330 : quirk_tw686x_class);
4331 : DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4332 : quirk_tw686x_class);
4333 :
4334 : /*
4335 : * Some devices have problems with Transaction Layer Packets with the Relaxed
4336 : * Ordering Attribute set. Such devices should mark themselves and other
4337 : * device drivers should check before sending TLPs with RO set.
4338 : */
4339 0 : static void quirk_relaxedordering_disable(struct pci_dev *dev)
4340 : {
4341 0 : dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4342 0 : pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4343 0 : }
4344 :
4345 : /*
4346 : * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4347 : * Complex have a Flow Control Credit issue which can cause performance
4348 : * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4349 : */
4350 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4351 : quirk_relaxedordering_disable);
4352 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4353 : quirk_relaxedordering_disable);
4354 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4355 : quirk_relaxedordering_disable);
4356 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4357 : quirk_relaxedordering_disable);
4358 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4359 : quirk_relaxedordering_disable);
4360 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4361 : quirk_relaxedordering_disable);
4362 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4363 : quirk_relaxedordering_disable);
4364 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4365 : quirk_relaxedordering_disable);
4366 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4367 : quirk_relaxedordering_disable);
4368 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4369 : quirk_relaxedordering_disable);
4370 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4371 : quirk_relaxedordering_disable);
4372 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4373 : quirk_relaxedordering_disable);
4374 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4375 : quirk_relaxedordering_disable);
4376 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4377 : quirk_relaxedordering_disable);
4378 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4379 : quirk_relaxedordering_disable);
4380 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4381 : quirk_relaxedordering_disable);
4382 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4383 : quirk_relaxedordering_disable);
4384 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4385 : quirk_relaxedordering_disable);
4386 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4387 : quirk_relaxedordering_disable);
4388 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4389 : quirk_relaxedordering_disable);
4390 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4391 : quirk_relaxedordering_disable);
4392 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4393 : quirk_relaxedordering_disable);
4394 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4395 : quirk_relaxedordering_disable);
4396 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4397 : quirk_relaxedordering_disable);
4398 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4399 : quirk_relaxedordering_disable);
4400 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4401 : quirk_relaxedordering_disable);
4402 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4403 : quirk_relaxedordering_disable);
4404 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4405 : quirk_relaxedordering_disable);
4406 :
4407 : /*
4408 : * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4409 : * where Upstream Transaction Layer Packets with the Relaxed Ordering
4410 : * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4411 : * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4412 : * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4413 : * November 10, 2010). As a result, on this platform we can't use Relaxed
4414 : * Ordering for Upstream TLPs.
4415 : */
4416 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4417 : quirk_relaxedordering_disable);
4418 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4419 : quirk_relaxedordering_disable);
4420 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4421 : quirk_relaxedordering_disable);
4422 :
4423 : /*
4424 : * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4425 : * values for the Attribute as were supplied in the header of the
4426 : * corresponding Request, except as explicitly allowed when IDO is used."
4427 : *
4428 : * If a non-compliant device generates a completion with a different
4429 : * attribute than the request, the receiver may accept it (which itself
4430 : * seems non-compliant based on sec 2.3.2), or it may handle it as a
4431 : * Malformed TLP or an Unexpected Completion, which will probably lead to a
4432 : * device access timeout.
4433 : *
4434 : * If the non-compliant device generates completions with zero attributes
4435 : * (instead of copying the attributes from the request), we can work around
4436 : * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4437 : * upstream devices so they always generate requests with zero attributes.
4438 : *
4439 : * This affects other devices under the same Root Port, but since these
4440 : * attributes are performance hints, there should be no functional problem.
4441 : *
4442 : * Note that Configuration Space accesses are never supposed to have TLP
4443 : * Attributes, so we're safe waiting till after any Configuration Space
4444 : * accesses to do the Root Port fixup.
4445 : */
4446 0 : static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4447 : {
4448 0 : struct pci_dev *root_port = pcie_find_root_port(pdev);
4449 :
4450 0 : if (!root_port) {
4451 0 : pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4452 0 : return;
4453 : }
4454 :
4455 0 : pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4456 : dev_name(&pdev->dev));
4457 0 : pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4458 : PCI_EXP_DEVCTL_RELAX_EN |
4459 : PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4460 : }
4461 :
4462 : /*
4463 : * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4464 : * Completion it generates.
4465 : */
4466 0 : static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4467 : {
4468 : /*
4469 : * This mask/compare operation selects for Physical Function 4 on a
4470 : * T5. We only need to fix up the Root Port once for any of the
4471 : * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4472 : * 0x54xx so we use that one.
4473 : */
4474 0 : if ((pdev->device & 0xff00) == 0x5400)
4475 0 : quirk_disable_root_port_attributes(pdev);
4476 0 : }
4477 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4478 : quirk_chelsio_T5_disable_root_port_attributes);
4479 :
4480 : /*
4481 : * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4482 : * by a device
4483 : * @acs_ctrl_req: Bitmask of desired ACS controls
4484 : * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4485 : * the hardware design
4486 : *
4487 : * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4488 : * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4489 : * caller desires. Return 0 otherwise.
4490 : */
4491 : static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4492 : {
4493 0 : if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4494 : return 1;
4495 : return 0;
4496 : }
4497 :
4498 : /*
4499 : * AMD has indicated that the devices below do not support peer-to-peer
4500 : * in any system where they are found in the southbridge with an AMD
4501 : * IOMMU in the system. Multifunction devices that do not support
4502 : * peer-to-peer between functions can claim to support a subset of ACS.
4503 : * Such devices effectively enable request redirect (RR) and completion
4504 : * redirect (CR) since all transactions are redirected to the upstream
4505 : * root complex.
4506 : *
4507 : * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4508 : * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4509 : * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
4510 : *
4511 : * 1002:4385 SBx00 SMBus Controller
4512 : * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4513 : * 1002:4383 SBx00 Azalia (Intel HDA)
4514 : * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4515 : * 1002:4384 SBx00 PCI to PCI Bridge
4516 : * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4517 : *
4518 : * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4519 : *
4520 : * 1022:780f [AMD] FCH PCI Bridge
4521 : * 1022:7809 [AMD] FCH USB OHCI Controller
4522 : */
4523 0 : static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4524 : {
4525 : #ifdef CONFIG_ACPI
4526 : struct acpi_table_header *header = NULL;
4527 : acpi_status status;
4528 :
4529 : /* Targeting multifunction devices on the SB (appears on root bus) */
4530 : if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4531 : return -ENODEV;
4532 :
4533 : /* The IVRS table describes the AMD IOMMU */
4534 : status = acpi_get_table("IVRS", 0, &header);
4535 : if (ACPI_FAILURE(status))
4536 : return -ENODEV;
4537 :
4538 : acpi_put_table(header);
4539 :
4540 : /* Filter out flags not applicable to multifunction */
4541 : acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4542 :
4543 : return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4544 : #else
4545 0 : return -ENODEV;
4546 : #endif
4547 : }
4548 :
4549 : static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4550 : {
4551 0 : if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4552 : return false;
4553 :
4554 0 : switch (dev->device) {
4555 : /*
4556 : * Effectively selects all downstream ports for whole ThunderX1
4557 : * (which represents 8 SoCs).
4558 : */
4559 : case 0xa000 ... 0xa7ff: /* ThunderX1 */
4560 : case 0xaf84: /* ThunderX2 */
4561 : case 0xb884: /* ThunderX3 */
4562 : return true;
4563 : default:
4564 : return false;
4565 : }
4566 : }
4567 :
4568 0 : static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4569 : {
4570 0 : if (!pci_quirk_cavium_acs_match(dev))
4571 : return -ENOTTY;
4572 :
4573 : /*
4574 : * Cavium Root Ports don't advertise an ACS capability. However,
4575 : * the RTL internally implements similar protection as if ACS had
4576 : * Source Validation, Request Redirection, Completion Redirection,
4577 : * and Upstream Forwarding features enabled. Assert that the
4578 : * hardware implements and enables equivalent ACS functionality for
4579 : * these flags.
4580 : */
4581 : return pci_acs_ctrl_enabled(acs_flags,
4582 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4583 : }
4584 :
4585 0 : static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4586 : {
4587 : /*
4588 : * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4589 : * transactions with others, allowing masking out these bits as if they
4590 : * were unimplemented in the ACS capability.
4591 : */
4592 0 : return pci_acs_ctrl_enabled(acs_flags,
4593 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4594 : }
4595 :
4596 : /*
4597 : * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4598 : * But the implementation could block peer-to-peer transactions between them
4599 : * and provide ACS-like functionality.
4600 : */
4601 0 : static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4602 : {
4603 0 : if (!pci_is_pcie(dev) ||
4604 0 : ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4605 0 : (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4606 : return -ENOTTY;
4607 :
4608 0 : switch (dev->device) {
4609 : case 0x0710 ... 0x071e:
4610 : case 0x0721:
4611 : case 0x0723 ... 0x0732:
4612 : return pci_acs_ctrl_enabled(acs_flags,
4613 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4614 : }
4615 :
4616 : return false;
4617 : }
4618 :
4619 : /*
4620 : * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4621 : * transactions and validate bus numbers in requests, but do not provide an
4622 : * actual PCIe ACS capability. This is the list of device IDs known to fall
4623 : * into that category as provided by Intel in Red Hat bugzilla 1037684.
4624 : */
4625 : static const u16 pci_quirk_intel_pch_acs_ids[] = {
4626 : /* Ibexpeak PCH */
4627 : 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4628 : 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4629 : /* Cougarpoint PCH */
4630 : 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4631 : 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4632 : /* Pantherpoint PCH */
4633 : 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4634 : 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4635 : /* Lynxpoint-H PCH */
4636 : 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4637 : 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4638 : /* Lynxpoint-LP PCH */
4639 : 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4640 : 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4641 : /* Wildcat PCH */
4642 : 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4643 : 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4644 : /* Patsburg (X79) PCH */
4645 : 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4646 : /* Wellsburg (X99) PCH */
4647 : 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4648 : 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4649 : /* Lynx Point (9 series) PCH */
4650 : 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4651 : };
4652 :
4653 : static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4654 : {
4655 : int i;
4656 :
4657 : /* Filter out a few obvious non-matches first */
4658 0 : if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4659 : return false;
4660 :
4661 0 : for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4662 0 : if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4663 : return true;
4664 :
4665 : return false;
4666 : }
4667 :
4668 0 : static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4669 : {
4670 0 : if (!pci_quirk_intel_pch_acs_match(dev))
4671 : return -ENOTTY;
4672 :
4673 0 : if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4674 : return pci_acs_ctrl_enabled(acs_flags,
4675 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4676 :
4677 : return pci_acs_ctrl_enabled(acs_flags, 0);
4678 : }
4679 :
4680 : /*
4681 : * These QCOM Root Ports do provide ACS-like features to disable peer
4682 : * transactions and validate bus numbers in requests, but do not provide an
4683 : * actual PCIe ACS capability. Hardware supports source validation but it
4684 : * will report the issue as Completer Abort instead of ACS Violation.
4685 : * Hardware doesn't support peer-to-peer and each Root Port is a Root
4686 : * Complex with unique segment numbers. It is not possible for one Root
4687 : * Port to pass traffic to another Root Port. All PCIe transactions are
4688 : * terminated inside the Root Port.
4689 : */
4690 0 : static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4691 : {
4692 0 : return pci_acs_ctrl_enabled(acs_flags,
4693 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4694 : }
4695 :
4696 : /*
4697 : * Each of these NXP Root Ports is in a Root Complex with a unique segment
4698 : * number and does provide isolation features to disable peer transactions
4699 : * and validate bus numbers in requests, but does not provide an ACS
4700 : * capability.
4701 : */
4702 0 : static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags)
4703 : {
4704 0 : return pci_acs_ctrl_enabled(acs_flags,
4705 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4706 : }
4707 :
4708 0 : static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4709 : {
4710 0 : if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4711 : return -ENOTTY;
4712 :
4713 : /*
4714 : * Amazon's Annapurna Labs root ports don't include an ACS capability,
4715 : * but do include ACS-like functionality. The hardware doesn't support
4716 : * peer-to-peer transactions via the root port and each has a unique
4717 : * segment number.
4718 : *
4719 : * Additionally, the root ports cannot send traffic to each other.
4720 : */
4721 0 : acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4722 :
4723 0 : return acs_flags ? 0 : 1;
4724 : }
4725 :
4726 : /*
4727 : * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4728 : * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4729 : * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4730 : * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4731 : * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4732 : * control register is at offset 8 instead of 6 and we should probably use
4733 : * dword accesses to them. This applies to the following PCI Device IDs, as
4734 : * found in volume 1 of the datasheet[2]:
4735 : *
4736 : * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4737 : * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4738 : *
4739 : * N.B. This doesn't fix what lspci shows.
4740 : *
4741 : * The 100 series chipset specification update includes this as errata #23[3].
4742 : *
4743 : * The 200 series chipset (Union Point) has the same bug according to the
4744 : * specification update (Intel 200 Series Chipset Family Platform Controller
4745 : * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4746 : * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4747 : * chipset include:
4748 : *
4749 : * 0xa290-0xa29f PCI Express Root port #{0-16}
4750 : * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4751 : *
4752 : * Mobile chipsets are also affected, 7th & 8th Generation
4753 : * Specification update confirms ACS errata 22, status no fix: (7th Generation
4754 : * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4755 : * Processor Family I/O for U Quad Core Platforms Specification Update,
4756 : * August 2017, Revision 002, Document#: 334660-002)[6]
4757 : * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4758 : * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4759 : * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4760 : *
4761 : * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4762 : *
4763 : * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4764 : * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4765 : * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4766 : * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4767 : * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4768 : * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4769 : * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4770 : */
4771 0 : static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4772 : {
4773 0 : if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4774 : return false;
4775 :
4776 0 : switch (dev->device) {
4777 : case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4778 : case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4779 : case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4780 : return true;
4781 : }
4782 :
4783 0 : return false;
4784 : }
4785 :
4786 : #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4787 :
4788 0 : static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4789 : {
4790 : int pos;
4791 : u32 cap, ctrl;
4792 :
4793 0 : if (!pci_quirk_intel_spt_pch_acs_match(dev))
4794 : return -ENOTTY;
4795 :
4796 0 : pos = dev->acs_cap;
4797 0 : if (!pos)
4798 : return -ENOTTY;
4799 :
4800 : /* see pci_acs_flags_enabled() */
4801 0 : pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4802 0 : acs_flags &= (cap | PCI_ACS_EC);
4803 :
4804 0 : pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4805 :
4806 0 : return pci_acs_ctrl_enabled(acs_flags, ctrl);
4807 : }
4808 :
4809 0 : static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4810 : {
4811 : /*
4812 : * SV, TB, and UF are not relevant to multifunction endpoints.
4813 : *
4814 : * Multifunction devices are only required to implement RR, CR, and DT
4815 : * in their ACS capability if they support peer-to-peer transactions.
4816 : * Devices matching this quirk have been verified by the vendor to not
4817 : * perform peer-to-peer with other functions, allowing us to mask out
4818 : * these bits as if they were unimplemented in the ACS capability.
4819 : */
4820 0 : return pci_acs_ctrl_enabled(acs_flags,
4821 : PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4822 : PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4823 : }
4824 :
4825 0 : static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4826 : {
4827 : /*
4828 : * Intel RCiEP's are required to allow p2p only on translated
4829 : * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4830 : * "Root-Complex Peer to Peer Considerations".
4831 : */
4832 0 : if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4833 : return -ENOTTY;
4834 :
4835 : return pci_acs_ctrl_enabled(acs_flags,
4836 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4837 : }
4838 :
4839 0 : static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4840 : {
4841 : /*
4842 : * iProc PAXB Root Ports don't advertise an ACS capability, but
4843 : * they do not allow peer-to-peer transactions between Root Ports.
4844 : * Allow each Root Port to be in a separate IOMMU group by masking
4845 : * SV/RR/CR/UF bits.
4846 : */
4847 0 : return pci_acs_ctrl_enabled(acs_flags,
4848 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4849 : }
4850 :
4851 : /*
4852 : * Wangxun 10G/1G NICs have no ACS capability, and on multi-function
4853 : * devices, peer-to-peer transactions are not be used between the functions.
4854 : * So add an ACS quirk for below devices to isolate functions.
4855 : * SFxxx 1G NICs(em).
4856 : * RP1000/RP2000 10G NICs(sp).
4857 : */
4858 0 : static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags)
4859 : {
4860 0 : switch (dev->device) {
4861 : case 0x0100 ... 0x010F:
4862 : case 0x1001:
4863 : case 0x2001:
4864 : return pci_acs_ctrl_enabled(acs_flags,
4865 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4866 : }
4867 :
4868 : return false;
4869 : }
4870 :
4871 : static const struct pci_dev_acs_enabled {
4872 : u16 vendor;
4873 : u16 device;
4874 : int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4875 : } pci_dev_acs_enabled[] = {
4876 : { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4877 : { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4878 : { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4879 : { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4880 : { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4881 : { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4882 : { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4883 : { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4884 : { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4885 : { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4886 : { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4887 : { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4888 : { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4889 : { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4890 : { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4891 : { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4892 : { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4893 : { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4894 : { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4895 : { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4896 : { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4897 : { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4898 : { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4899 : { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4900 : { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4901 : { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4902 : { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4903 : { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4904 : { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4905 : { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4906 : { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4907 : /* 82580 */
4908 : { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4909 : { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4910 : { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4911 : { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4912 : { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4913 : { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4914 : { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4915 : /* 82576 */
4916 : { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4917 : { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4918 : { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4919 : { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4920 : { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4921 : { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4922 : { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4923 : { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4924 : /* 82575 */
4925 : { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4926 : { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4927 : { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4928 : /* I350 */
4929 : { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4930 : { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4931 : { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4932 : { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4933 : /* 82571 (Quads omitted due to non-ACS switch) */
4934 : { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4935 : { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4936 : { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4937 : { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4938 : /* I219 */
4939 : { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4940 : { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4941 : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
4942 : /* QCOM QDF2xxx root ports */
4943 : { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4944 : { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4945 : /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4946 : { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4947 : /* Intel PCH root ports */
4948 : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4949 : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4950 : { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4951 : { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4952 : /* Cavium ThunderX */
4953 : { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4954 : /* Cavium multi-function devices */
4955 : { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
4956 : { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
4957 : { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
4958 : /* APM X-Gene */
4959 : { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4960 : /* Ampere Computing */
4961 : { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4962 : { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4963 : { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4964 : { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4965 : { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4966 : { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4967 : { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4968 : { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4969 : /* Broadcom multi-function device */
4970 : { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
4971 : { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
4972 : { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
4973 : { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
4974 : { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4975 : /* Amazon Annapurna Labs */
4976 : { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4977 : /* Zhaoxin multi-function devices */
4978 : { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
4979 : { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
4980 : { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
4981 : /* NXP root ports, xx=16, 12, or 08 cores */
4982 : /* LX2xx0A : without security features + CAN-FD */
4983 : { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
4984 : { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
4985 : { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
4986 : /* LX2xx0C : security features + CAN-FD */
4987 : { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
4988 : { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
4989 : { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
4990 : /* LX2xx0E : security features + CAN */
4991 : { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
4992 : { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
4993 : { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
4994 : /* LX2xx0N : without security features + CAN */
4995 : { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
4996 : { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
4997 : { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
4998 : /* LX2xx2A : without security features + CAN-FD */
4999 : { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
5000 : { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
5001 : { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
5002 : /* LX2xx2C : security features + CAN-FD */
5003 : { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
5004 : { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
5005 : { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
5006 : /* LX2xx2E : security features + CAN */
5007 : { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
5008 : { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
5009 : { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
5010 : /* LX2xx2N : without security features + CAN */
5011 : { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
5012 : { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
5013 : { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
5014 : /* Zhaoxin Root/Downstream Ports */
5015 : { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
5016 : /* Wangxun nics */
5017 : { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
5018 : { 0 }
5019 : };
5020 :
5021 : /*
5022 : * pci_dev_specific_acs_enabled - check whether device provides ACS controls
5023 : * @dev: PCI device
5024 : * @acs_flags: Bitmask of desired ACS controls
5025 : *
5026 : * Returns:
5027 : * -ENOTTY: No quirk applies to this device; we can't tell whether the
5028 : * device provides the desired controls
5029 : * 0: Device does not provide all the desired controls
5030 : * >0: Device provides all the controls in @acs_flags
5031 : */
5032 0 : int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
5033 : {
5034 : const struct pci_dev_acs_enabled *i;
5035 : int ret;
5036 :
5037 : /*
5038 : * Allow devices that do not expose standard PCIe ACS capabilities
5039 : * or control to indicate their support here. Multi-function express
5040 : * devices which do not allow internal peer-to-peer between functions,
5041 : * but do not implement PCIe ACS may wish to return true here.
5042 : */
5043 0 : for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
5044 0 : if ((i->vendor == dev->vendor ||
5045 0 : i->vendor == (u16)PCI_ANY_ID) &&
5046 0 : (i->device == dev->device ||
5047 : i->device == (u16)PCI_ANY_ID)) {
5048 0 : ret = i->acs_enabled(dev, acs_flags);
5049 0 : if (ret >= 0)
5050 : return ret;
5051 : }
5052 : }
5053 :
5054 : return -ENOTTY;
5055 : }
5056 :
5057 : /* Config space offset of Root Complex Base Address register */
5058 : #define INTEL_LPC_RCBA_REG 0xf0
5059 : /* 31:14 RCBA address */
5060 : #define INTEL_LPC_RCBA_MASK 0xffffc000
5061 : /* RCBA Enable */
5062 : #define INTEL_LPC_RCBA_ENABLE (1 << 0)
5063 :
5064 : /* Backbone Scratch Pad Register */
5065 : #define INTEL_BSPR_REG 0x1104
5066 : /* Backbone Peer Non-Posted Disable */
5067 : #define INTEL_BSPR_REG_BPNPD (1 << 8)
5068 : /* Backbone Peer Posted Disable */
5069 : #define INTEL_BSPR_REG_BPPD (1 << 9)
5070 :
5071 : /* Upstream Peer Decode Configuration Register */
5072 : #define INTEL_UPDCR_REG 0x1014
5073 : /* 5:0 Peer Decode Enable bits */
5074 : #define INTEL_UPDCR_REG_MASK 0x3f
5075 :
5076 0 : static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
5077 : {
5078 : u32 rcba, bspr, updcr;
5079 : void __iomem *rcba_mem;
5080 :
5081 : /*
5082 : * Read the RCBA register from the LPC (D31:F0). PCH root ports
5083 : * are D28:F* and therefore get probed before LPC, thus we can't
5084 : * use pci_get_slot()/pci_read_config_dword() here.
5085 : */
5086 0 : pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
5087 : INTEL_LPC_RCBA_REG, &rcba);
5088 0 : if (!(rcba & INTEL_LPC_RCBA_ENABLE))
5089 : return -EINVAL;
5090 :
5091 0 : rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
5092 : PAGE_ALIGN(INTEL_UPDCR_REG));
5093 0 : if (!rcba_mem)
5094 : return -ENOMEM;
5095 :
5096 : /*
5097 : * The BSPR can disallow peer cycles, but it's set by soft strap and
5098 : * therefore read-only. If both posted and non-posted peer cycles are
5099 : * disallowed, we're ok. If either are allowed, then we need to use
5100 : * the UPDCR to disable peer decodes for each port. This provides the
5101 : * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5102 : */
5103 0 : bspr = readl(rcba_mem + INTEL_BSPR_REG);
5104 0 : bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
5105 0 : if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
5106 0 : updcr = readl(rcba_mem + INTEL_UPDCR_REG);
5107 0 : if (updcr & INTEL_UPDCR_REG_MASK) {
5108 0 : pci_info(dev, "Disabling UPDCR peer decodes\n");
5109 0 : updcr &= ~INTEL_UPDCR_REG_MASK;
5110 0 : writel(updcr, rcba_mem + INTEL_UPDCR_REG);
5111 : }
5112 : }
5113 :
5114 0 : iounmap(rcba_mem);
5115 0 : return 0;
5116 : }
5117 :
5118 : /* Miscellaneous Port Configuration register */
5119 : #define INTEL_MPC_REG 0xd8
5120 : /* MPC: Invalid Receive Bus Number Check Enable */
5121 : #define INTEL_MPC_REG_IRBNCE (1 << 26)
5122 :
5123 0 : static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
5124 : {
5125 : u32 mpc;
5126 :
5127 : /*
5128 : * When enabled, the IRBNCE bit of the MPC register enables the
5129 : * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
5130 : * ensures that requester IDs fall within the bus number range
5131 : * of the bridge. Enable if not already.
5132 : */
5133 0 : pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
5134 0 : if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
5135 0 : pci_info(dev, "Enabling MPC IRBNCE\n");
5136 0 : mpc |= INTEL_MPC_REG_IRBNCE;
5137 0 : pci_write_config_word(dev, INTEL_MPC_REG, mpc);
5138 : }
5139 0 : }
5140 :
5141 : /*
5142 : * Currently this quirk does the equivalent of
5143 : * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5144 : *
5145 : * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
5146 : * if dev->external_facing || dev->untrusted
5147 : */
5148 0 : static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
5149 : {
5150 0 : if (!pci_quirk_intel_pch_acs_match(dev))
5151 : return -ENOTTY;
5152 :
5153 0 : if (pci_quirk_enable_intel_lpc_acs(dev)) {
5154 0 : pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
5155 0 : return 0;
5156 : }
5157 :
5158 0 : pci_quirk_enable_intel_rp_mpc_acs(dev);
5159 :
5160 0 : dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
5161 :
5162 0 : pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
5163 :
5164 0 : return 0;
5165 : }
5166 :
5167 0 : static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
5168 : {
5169 : int pos;
5170 : u32 cap, ctrl;
5171 :
5172 0 : if (!pci_quirk_intel_spt_pch_acs_match(dev))
5173 : return -ENOTTY;
5174 :
5175 0 : pos = dev->acs_cap;
5176 0 : if (!pos)
5177 : return -ENOTTY;
5178 :
5179 0 : pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5180 0 : pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5181 :
5182 0 : ctrl |= (cap & PCI_ACS_SV);
5183 0 : ctrl |= (cap & PCI_ACS_RR);
5184 0 : ctrl |= (cap & PCI_ACS_CR);
5185 0 : ctrl |= (cap & PCI_ACS_UF);
5186 :
5187 0 : if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
5188 0 : ctrl |= (cap & PCI_ACS_TB);
5189 :
5190 0 : pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5191 :
5192 0 : pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
5193 :
5194 0 : return 0;
5195 : }
5196 :
5197 0 : static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
5198 : {
5199 : int pos;
5200 : u32 cap, ctrl;
5201 :
5202 0 : if (!pci_quirk_intel_spt_pch_acs_match(dev))
5203 : return -ENOTTY;
5204 :
5205 0 : pos = dev->acs_cap;
5206 0 : if (!pos)
5207 : return -ENOTTY;
5208 :
5209 0 : pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5210 0 : pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5211 :
5212 0 : ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
5213 :
5214 0 : pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5215 :
5216 0 : pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5217 :
5218 0 : return 0;
5219 : }
5220 :
5221 : static const struct pci_dev_acs_ops {
5222 : u16 vendor;
5223 : u16 device;
5224 : int (*enable_acs)(struct pci_dev *dev);
5225 : int (*disable_acs_redir)(struct pci_dev *dev);
5226 : } pci_dev_acs_ops[] = {
5227 : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5228 : .enable_acs = pci_quirk_enable_intel_pch_acs,
5229 : },
5230 : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5231 : .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5232 : .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5233 : },
5234 : };
5235 :
5236 0 : int pci_dev_specific_enable_acs(struct pci_dev *dev)
5237 : {
5238 : const struct pci_dev_acs_ops *p;
5239 : int i, ret;
5240 :
5241 0 : for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5242 0 : p = &pci_dev_acs_ops[i];
5243 0 : if ((p->vendor == dev->vendor ||
5244 0 : p->vendor == (u16)PCI_ANY_ID) &&
5245 0 : (p->device == dev->device ||
5246 0 : p->device == (u16)PCI_ANY_ID) &&
5247 0 : p->enable_acs) {
5248 0 : ret = p->enable_acs(dev);
5249 0 : if (ret >= 0)
5250 : return ret;
5251 : }
5252 : }
5253 :
5254 : return -ENOTTY;
5255 : }
5256 :
5257 0 : int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5258 : {
5259 : const struct pci_dev_acs_ops *p;
5260 : int i, ret;
5261 :
5262 0 : for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5263 0 : p = &pci_dev_acs_ops[i];
5264 0 : if ((p->vendor == dev->vendor ||
5265 0 : p->vendor == (u16)PCI_ANY_ID) &&
5266 0 : (p->device == dev->device ||
5267 0 : p->device == (u16)PCI_ANY_ID) &&
5268 0 : p->disable_acs_redir) {
5269 0 : ret = p->disable_acs_redir(dev);
5270 0 : if (ret >= 0)
5271 : return ret;
5272 : }
5273 : }
5274 :
5275 : return -ENOTTY;
5276 : }
5277 :
5278 : /*
5279 : * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5280 : * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5281 : * Next Capability pointer in the MSI Capability Structure should point to
5282 : * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5283 : * the list.
5284 : */
5285 0 : static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5286 : {
5287 0 : int pos, i = 0;
5288 : u8 next_cap;
5289 : u16 reg16, *cap;
5290 : struct pci_cap_saved_state *state;
5291 :
5292 : /* Bail if the hardware bug is fixed */
5293 0 : if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5294 0 : return;
5295 :
5296 : /* Bail if MSI Capability Structure is not found for some reason */
5297 0 : pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
5298 0 : if (!pos)
5299 : return;
5300 :
5301 : /*
5302 : * Bail if Next Capability pointer in the MSI Capability Structure
5303 : * is not the expected incorrect 0x00.
5304 : */
5305 0 : pci_read_config_byte(pdev, pos + 1, &next_cap);
5306 0 : if (next_cap)
5307 : return;
5308 :
5309 : /*
5310 : * PCIe Capability Structure is expected to be at 0x50 and should
5311 : * terminate the list (Next Capability pointer is 0x00). Verify
5312 : * Capability Id and Next Capability pointer is as expected.
5313 : * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5314 : * to correctly set kernel data structures which have already been
5315 : * set incorrectly due to the hardware bug.
5316 : */
5317 0 : pos = 0x50;
5318 0 : pci_read_config_word(pdev, pos, ®16);
5319 0 : if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5320 : u32 status;
5321 : #ifndef PCI_EXP_SAVE_REGS
5322 : #define PCI_EXP_SAVE_REGS 7
5323 : #endif
5324 0 : int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5325 :
5326 0 : pdev->pcie_cap = pos;
5327 0 : pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
5328 0 : pdev->pcie_flags_reg = reg16;
5329 0 : pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
5330 0 : pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5331 :
5332 0 : pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5333 0 : if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
5334 0 : PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
5335 0 : pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5336 :
5337 0 : if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5338 0 : return;
5339 :
5340 : /* Save PCIe cap */
5341 0 : state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5342 0 : if (!state)
5343 : return;
5344 :
5345 0 : state->cap.cap_nr = PCI_CAP_ID_EXP;
5346 0 : state->cap.cap_extended = 0;
5347 0 : state->cap.size = size;
5348 0 : cap = (u16 *)&state->cap.data[0];
5349 0 : pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5350 0 : pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5351 0 : pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5352 0 : pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
5353 0 : pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5354 0 : pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5355 0 : pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5356 0 : hlist_add_head(&state->next, &pdev->saved_cap_space);
5357 : }
5358 : }
5359 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5360 :
5361 : /*
5362 : * FLR may cause the following to devices to hang:
5363 : *
5364 : * AMD Starship/Matisse HD Audio Controller 0x1487
5365 : * AMD Starship USB 3.0 Host Controller 0x148c
5366 : * AMD Matisse USB 3.0 Host Controller 0x149c
5367 : * Intel 82579LM Gigabit Ethernet Controller 0x1502
5368 : * Intel 82579V Gigabit Ethernet Controller 0x1503
5369 : *
5370 : */
5371 0 : static void quirk_no_flr(struct pci_dev *dev)
5372 : {
5373 0 : dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5374 0 : }
5375 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5376 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5377 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5378 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr);
5379 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5380 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5381 :
5382 : /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */
5383 0 : static void quirk_no_flr_snet(struct pci_dev *dev)
5384 : {
5385 0 : if (dev->revision == 0x1)
5386 : quirk_no_flr(dev);
5387 0 : }
5388 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet);
5389 :
5390 0 : static void quirk_no_ext_tags(struct pci_dev *pdev)
5391 : {
5392 0 : struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5393 :
5394 0 : if (!bridge)
5395 : return;
5396 :
5397 0 : bridge->no_ext_tags = 1;
5398 0 : pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5399 :
5400 0 : pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5401 : }
5402 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5403 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5404 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5405 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5406 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5407 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5408 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5409 :
5410 : #ifdef CONFIG_PCI_ATS
5411 : /*
5412 : * Some devices require additional driver setup to enable ATS. Don't use
5413 : * ATS for those devices as ATS will be enabled before the driver has had a
5414 : * chance to load and configure the device.
5415 : */
5416 : static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5417 : {
5418 : if (pdev->device == 0x15d8) {
5419 : if (pdev->revision == 0xcf &&
5420 : pdev->subsystem_vendor == 0xea50 &&
5421 : (pdev->subsystem_device == 0xce19 ||
5422 : pdev->subsystem_device == 0xcc10 ||
5423 : pdev->subsystem_device == 0xcc08))
5424 : goto no_ats;
5425 : else
5426 : return;
5427 : }
5428 :
5429 : no_ats:
5430 : pci_info(pdev, "disabling ATS\n");
5431 : pdev->ats_cap = 0;
5432 : }
5433 :
5434 : /* AMD Stoney platform GPU */
5435 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5436 : /* AMD Iceland dGPU */
5437 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5438 : /* AMD Navi10 dGPU */
5439 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
5440 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5441 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
5442 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
5443 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
5444 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
5445 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
5446 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
5447 : /* AMD Navi14 dGPU */
5448 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5449 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5450 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
5451 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
5452 : /* AMD Raven platform iGPU */
5453 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
5454 : #endif /* CONFIG_PCI_ATS */
5455 :
5456 : /* Freescale PCIe doesn't support MSI in RC mode */
5457 0 : static void quirk_fsl_no_msi(struct pci_dev *pdev)
5458 : {
5459 0 : if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5460 0 : pdev->no_msi = 1;
5461 0 : }
5462 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5463 :
5464 : /*
5465 : * Although not allowed by the spec, some multi-function devices have
5466 : * dependencies of one function (consumer) on another (supplier). For the
5467 : * consumer to work in D0, the supplier must also be in D0. Create a
5468 : * device link from the consumer to the supplier to enforce this
5469 : * dependency. Runtime PM is allowed by default on the consumer to prevent
5470 : * it from permanently keeping the supplier awake.
5471 : */
5472 0 : static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5473 : unsigned int supplier, unsigned int class,
5474 : unsigned int class_shift)
5475 : {
5476 : struct pci_dev *supplier_pdev;
5477 :
5478 0 : if (PCI_FUNC(pdev->devfn) != consumer)
5479 : return;
5480 :
5481 0 : supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5482 0 : pdev->bus->number,
5483 0 : PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5484 0 : if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5485 0 : pci_dev_put(supplier_pdev);
5486 0 : return;
5487 : }
5488 :
5489 0 : if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5490 : DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5491 0 : pci_info(pdev, "D0 power state depends on %s\n",
5492 : pci_name(supplier_pdev));
5493 : else
5494 0 : pci_err(pdev, "Cannot enforce power dependency on %s\n",
5495 : pci_name(supplier_pdev));
5496 :
5497 0 : pm_runtime_allow(&pdev->dev);
5498 0 : pci_dev_put(supplier_pdev);
5499 : }
5500 :
5501 : /*
5502 : * Create device link for GPUs with integrated HDA controller for streaming
5503 : * audio to attached displays.
5504 : */
5505 0 : static void quirk_gpu_hda(struct pci_dev *hda)
5506 : {
5507 0 : pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5508 0 : }
5509 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5510 : PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5511 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5512 : PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5513 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5514 : PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5515 :
5516 : /*
5517 : * Create device link for GPUs with integrated USB xHCI Host
5518 : * controller to VGA.
5519 : */
5520 0 : static void quirk_gpu_usb(struct pci_dev *usb)
5521 : {
5522 0 : pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5523 0 : }
5524 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5525 : PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5526 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5527 : PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5528 :
5529 : /*
5530 : * Create device link for GPUs with integrated Type-C UCSI controller
5531 : * to VGA. Currently there is no class code defined for UCSI device over PCI
5532 : * so using UNKNOWN class for now and it will be updated when UCSI
5533 : * over PCI gets a class code.
5534 : */
5535 : #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5536 0 : static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5537 : {
5538 0 : pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5539 0 : }
5540 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5541 : PCI_CLASS_SERIAL_UNKNOWN, 8,
5542 : quirk_gpu_usb_typec_ucsi);
5543 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5544 : PCI_CLASS_SERIAL_UNKNOWN, 8,
5545 : quirk_gpu_usb_typec_ucsi);
5546 :
5547 : /*
5548 : * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5549 : * disabled. https://devtalk.nvidia.com/default/topic/1024022
5550 : */
5551 0 : static void quirk_nvidia_hda(struct pci_dev *gpu)
5552 : {
5553 : u8 hdr_type;
5554 : u32 val;
5555 :
5556 : /* There was no integrated HDA controller before MCP89 */
5557 0 : if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5558 0 : return;
5559 :
5560 : /* Bit 25 at offset 0x488 enables the HDA controller */
5561 0 : pci_read_config_dword(gpu, 0x488, &val);
5562 0 : if (val & BIT(25))
5563 : return;
5564 :
5565 0 : pci_info(gpu, "Enabling HDA controller\n");
5566 0 : pci_write_config_dword(gpu, 0x488, val | BIT(25));
5567 :
5568 : /* The GPU becomes a multi-function device when the HDA is enabled */
5569 0 : pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5570 0 : gpu->multifunction = !!(hdr_type & 0x80);
5571 : }
5572 : DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5573 : PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5574 : DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5575 : PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5576 :
5577 : /*
5578 : * Some IDT switches incorrectly flag an ACS Source Validation error on
5579 : * completions for config read requests even though PCIe r4.0, sec
5580 : * 6.12.1.1, says that completions are never affected by ACS Source
5581 : * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5582 : *
5583 : * Item #36 - Downstream port applies ACS Source Validation to Completions
5584 : * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5585 : * completions are never affected by ACS Source Validation. However,
5586 : * completions received by a downstream port of the PCIe switch from a
5587 : * device that has not yet captured a PCIe bus number are incorrectly
5588 : * dropped by ACS Source Validation by the switch downstream port.
5589 : *
5590 : * The workaround suggested by IDT is to issue a config write to the
5591 : * downstream device before issuing the first config read. This allows the
5592 : * downstream device to capture its bus and device numbers (see PCIe r4.0,
5593 : * sec 2.2.9), thus avoiding the ACS error on the completion.
5594 : *
5595 : * However, we don't know when the device is ready to accept the config
5596 : * write, so we do config reads until we receive a non-Config Request Retry
5597 : * Status, then do the config write.
5598 : *
5599 : * To avoid hitting the erratum when doing the config reads, we disable ACS
5600 : * SV around this process.
5601 : */
5602 0 : int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5603 : {
5604 : int pos;
5605 0 : u16 ctrl = 0;
5606 : bool found;
5607 0 : struct pci_dev *bridge = bus->self;
5608 :
5609 0 : pos = bridge->acs_cap;
5610 :
5611 : /* Disable ACS SV before initial config reads */
5612 0 : if (pos) {
5613 0 : pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5614 0 : if (ctrl & PCI_ACS_SV)
5615 0 : pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5616 : ctrl & ~PCI_ACS_SV);
5617 : }
5618 :
5619 0 : found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5620 :
5621 : /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5622 0 : if (found)
5623 0 : pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5624 :
5625 : /* Re-enable ACS_SV if it was previously enabled */
5626 0 : if (ctrl & PCI_ACS_SV)
5627 0 : pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5628 :
5629 0 : return found;
5630 : }
5631 :
5632 : /*
5633 : * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5634 : * NT endpoints via the internal switch fabric. These IDs replace the
5635 : * originating requestor ID TLPs which access host memory on peer NTB
5636 : * ports. Therefore, all proxy IDs must be aliased to the NTB device
5637 : * to permit access when the IOMMU is turned on.
5638 : */
5639 0 : static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5640 : {
5641 : void __iomem *mmio;
5642 : struct ntb_info_regs __iomem *mmio_ntb;
5643 : struct ntb_ctrl_regs __iomem *mmio_ctrl;
5644 : u64 partition_map;
5645 : u8 partition;
5646 : int pp;
5647 :
5648 0 : if (pci_enable_device(pdev)) {
5649 0 : pci_err(pdev, "Cannot enable Switchtec device\n");
5650 0 : return;
5651 : }
5652 :
5653 0 : mmio = pci_iomap(pdev, 0, 0);
5654 0 : if (mmio == NULL) {
5655 0 : pci_disable_device(pdev);
5656 0 : pci_err(pdev, "Cannot iomap Switchtec device\n");
5657 0 : return;
5658 : }
5659 :
5660 0 : pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5661 :
5662 0 : mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5663 0 : mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5664 :
5665 0 : partition = ioread8(&mmio_ntb->partition_id);
5666 :
5667 0 : partition_map = ioread32(&mmio_ntb->ep_map);
5668 0 : partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5669 0 : partition_map &= ~(1ULL << partition);
5670 :
5671 0 : for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5672 : struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5673 0 : u32 table_sz = 0;
5674 : int te;
5675 :
5676 0 : if (!(partition_map & (1ULL << pp)))
5677 0 : continue;
5678 :
5679 : pci_dbg(pdev, "Processing partition %d\n", pp);
5680 :
5681 0 : mmio_peer_ctrl = &mmio_ctrl[pp];
5682 :
5683 0 : table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5684 0 : if (!table_sz) {
5685 0 : pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5686 0 : continue;
5687 : }
5688 :
5689 0 : if (table_sz > 512) {
5690 0 : pci_warn(pdev,
5691 : "Invalid Switchtec partition %d table_sz %d\n",
5692 : pp, table_sz);
5693 0 : continue;
5694 : }
5695 :
5696 0 : for (te = 0; te < table_sz; te++) {
5697 : u32 rid_entry;
5698 : u8 devfn;
5699 :
5700 0 : rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5701 0 : devfn = (rid_entry >> 1) & 0xFF;
5702 : pci_dbg(pdev,
5703 : "Aliasing Partition %d Proxy ID %02x.%d\n",
5704 : pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5705 0 : pci_add_dma_alias(pdev, devfn, 1);
5706 : }
5707 : }
5708 :
5709 0 : pci_iounmap(pdev, mmio);
5710 0 : pci_disable_device(pdev);
5711 : }
5712 : #define SWITCHTEC_QUIRK(vid) \
5713 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5714 : PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5715 :
5716 : SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5717 : SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5718 : SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5719 : SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5720 : SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5721 : SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5722 : SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5723 : SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5724 : SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5725 : SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5726 : SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5727 : SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5728 : SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5729 : SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5730 : SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5731 : SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5732 : SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5733 : SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5734 : SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5735 : SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5736 : SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5737 : SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5738 : SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5739 : SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5740 : SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5741 : SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5742 : SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5743 : SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5744 : SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5745 : SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5746 : SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5747 : SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5748 : SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5749 : SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5750 : SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5751 : SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5752 : SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5753 : SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5754 : SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5755 : SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5756 : SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5757 : SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5758 : SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5759 : SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5760 : SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5761 : SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5762 : SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5763 : SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5764 : SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */
5765 : SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */
5766 : SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */
5767 : SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */
5768 : SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */
5769 : SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */
5770 : SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */
5771 : SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */
5772 : SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */
5773 :
5774 : /*
5775 : * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5776 : * These IDs are used to forward responses to the originator on the other
5777 : * side of the NTB. Alias all possible IDs to the NTB to permit access when
5778 : * the IOMMU is turned on.
5779 : */
5780 0 : static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5781 : {
5782 0 : pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5783 : /* PLX NTB may use all 256 devfns */
5784 0 : pci_add_dma_alias(pdev, 0, 256);
5785 0 : }
5786 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5787 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5788 :
5789 : /*
5790 : * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5791 : * not always reset the secondary Nvidia GPU between reboots if the system
5792 : * is configured to use Hybrid Graphics mode. This results in the GPU
5793 : * being left in whatever state it was in during the *previous* boot, which
5794 : * causes spurious interrupts from the GPU, which in turn causes us to
5795 : * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5796 : * this also completely breaks nouveau.
5797 : *
5798 : * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5799 : * clean state and fixes all these issues.
5800 : *
5801 : * When the machine is configured in Dedicated display mode, the issue
5802 : * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5803 : * mode, so we can detect that and avoid resetting it.
5804 : */
5805 0 : static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5806 : {
5807 : void __iomem *map;
5808 : int ret;
5809 :
5810 0 : if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5811 0 : pdev->subsystem_device != 0x222e ||
5812 0 : !pci_reset_supported(pdev))
5813 : return;
5814 :
5815 0 : if (pci_enable_device_mem(pdev))
5816 : return;
5817 :
5818 : /*
5819 : * Based on nvkm_device_ctor() in
5820 : * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5821 : */
5822 0 : map = pci_iomap(pdev, 0, 0x23000);
5823 0 : if (!map) {
5824 0 : pci_err(pdev, "Can't map MMIO space\n");
5825 0 : goto out_disable;
5826 : }
5827 :
5828 : /*
5829 : * Make sure the GPU looks like it's been POSTed before resetting
5830 : * it.
5831 : */
5832 0 : if (ioread32(map + 0x2240c) & 0x2) {
5833 0 : pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5834 0 : ret = pci_reset_bus(pdev);
5835 0 : if (ret < 0)
5836 0 : pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5837 : }
5838 :
5839 0 : iounmap(map);
5840 : out_disable:
5841 0 : pci_disable_device(pdev);
5842 : }
5843 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5844 : PCI_CLASS_DISPLAY_VGA, 8,
5845 : quirk_reset_lenovo_thinkpad_p50_nvgpu);
5846 :
5847 : /*
5848 : * Device [1b21:2142]
5849 : * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5850 : */
5851 0 : static void pci_fixup_no_d0_pme(struct pci_dev *dev)
5852 : {
5853 0 : pci_info(dev, "PME# does not work under D0, disabling it\n");
5854 0 : dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
5855 0 : }
5856 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
5857 :
5858 : /*
5859 : * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
5860 : *
5861 : * These devices advertise PME# support in all power states but don't
5862 : * reliably assert it.
5863 : *
5864 : * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
5865 : * says "The MSI Function is not implemented on this device" in chapters
5866 : * 7.3.27, 7.3.29-7.3.31.
5867 : */
5868 0 : static void pci_fixup_no_msi_no_pme(struct pci_dev *dev)
5869 : {
5870 : #ifdef CONFIG_PCI_MSI
5871 0 : pci_info(dev, "MSI is not implemented on this device, disabling it\n");
5872 0 : dev->no_msi = 1;
5873 : #endif
5874 0 : pci_info(dev, "PME# is unreliable, disabling it\n");
5875 0 : dev->pme_support = 0;
5876 0 : }
5877 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
5878 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
5879 :
5880 0 : static void apex_pci_fixup_class(struct pci_dev *pdev)
5881 : {
5882 0 : pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
5883 0 : }
5884 : DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5885 : PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
5886 :
5887 : /*
5888 : * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 -
5889 : * ACS P2P Request Redirect is not functional
5890 : *
5891 : * When ACS P2P Request Redirect is enabled and bandwidth is not balanced
5892 : * between upstream and downstream ports, packets are queued in an internal
5893 : * buffer until CPLD packet. The workaround is to use the switch in store and
5894 : * forward mode.
5895 : */
5896 : #define PI7C9X2Gxxx_MODE_REG 0x74
5897 : #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0)
5898 0 : static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev)
5899 : {
5900 : struct pci_dev *upstream;
5901 : u16 val;
5902 :
5903 : /* Downstream ports only */
5904 0 : if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)
5905 0 : return;
5906 :
5907 : /* Check for ACS P2P Request Redirect use */
5908 0 : if (!pdev->acs_cap)
5909 : return;
5910 0 : pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val);
5911 0 : if (!(val & PCI_ACS_RR))
5912 : return;
5913 :
5914 0 : upstream = pci_upstream_bridge(pdev);
5915 0 : if (!upstream)
5916 : return;
5917 :
5918 0 : pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val);
5919 0 : if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) {
5920 0 : pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n");
5921 0 : pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val |
5922 : PI7C9X2Gxxx_STORE_FORWARD_MODE);
5923 : }
5924 : }
5925 : /*
5926 : * Apply fixup on enable and on resume, in order to apply the fix up whenever
5927 : * ACS configuration changes or switch mode is reset
5928 : */
5929 : DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404,
5930 : pci_fixup_pericom_acs_store_forward);
5931 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404,
5932 : pci_fixup_pericom_acs_store_forward);
5933 : DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304,
5934 : pci_fixup_pericom_acs_store_forward);
5935 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304,
5936 : pci_fixup_pericom_acs_store_forward);
5937 : DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303,
5938 : pci_fixup_pericom_acs_store_forward);
5939 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303,
5940 : pci_fixup_pericom_acs_store_forward);
5941 :
5942 0 : static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
5943 : {
5944 0 : pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
5945 0 : }
5946 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
5947 :
5948 0 : static void rom_bar_overlap_defect(struct pci_dev *dev)
5949 : {
5950 0 : pci_info(dev, "working around ROM BAR overlap defect\n");
5951 0 : dev->rom_bar_overlap = 1;
5952 0 : }
5953 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect);
5954 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect);
5955 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect);
5956 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect);
5957 :
5958 : #ifdef CONFIG_PCIEASPM
5959 : /*
5960 : * Several Intel DG2 graphics devices advertise that they can only tolerate
5961 : * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1
5962 : * from being enabled. But in fact these devices can tolerate unlimited
5963 : * latency. Override their Device Capabilities value to allow ASPM L1 to
5964 : * be enabled.
5965 : */
5966 0 : static void aspm_l1_acceptable_latency(struct pci_dev *dev)
5967 : {
5968 0 : u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap);
5969 :
5970 0 : if (l1_lat < 7) {
5971 0 : dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7);
5972 0 : pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n",
5973 : l1_lat);
5974 : }
5975 0 : }
5976 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency);
5977 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency);
5978 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency);
5979 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency);
5980 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency);
5981 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency);
5982 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency);
5983 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency);
5984 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency);
5985 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency);
5986 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency);
5987 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency);
5988 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency);
5989 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency);
5990 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency);
5991 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency);
5992 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency);
5993 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency);
5994 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency);
5995 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency);
5996 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency);
5997 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency);
5998 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency);
5999 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
6000 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
6001 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
6002 : #endif
6003 :
6004 : #ifdef CONFIG_PCIE_DPC
6005 : /*
6006 : * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears
6007 : * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root
6008 : * Ports.
6009 : */
6010 : static void dpc_log_size(struct pci_dev *dev)
6011 : {
6012 : u16 dpc, val;
6013 :
6014 : dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
6015 : if (!dpc)
6016 : return;
6017 :
6018 : pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val);
6019 : if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
6020 : return;
6021 :
6022 : if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) {
6023 : pci_info(dev, "Overriding RP PIO Log Size to 4\n");
6024 : dev->dpc_rp_log_size = 4;
6025 : }
6026 : }
6027 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
6028 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
6029 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
6030 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
6031 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size);
6032 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size);
6033 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size);
6034 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size);
6035 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
6036 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
6037 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
6038 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
6039 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
6040 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
6041 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
6042 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
6043 : #endif
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