Line data Source code
1 : /* SPDX-License-Identifier: GPL-2.0 */
2 : #ifndef _LINUX_IRQ_H
3 : #define _LINUX_IRQ_H
4 :
5 : /*
6 : * Please do not include this file in generic code. There is currently
7 : * no requirement for any architecture to implement anything held
8 : * within this file.
9 : *
10 : * Thanks. --rmk
11 : */
12 :
13 : #include <linux/cache.h>
14 : #include <linux/spinlock.h>
15 : #include <linux/cpumask.h>
16 : #include <linux/irqhandler.h>
17 : #include <linux/irqreturn.h>
18 : #include <linux/irqnr.h>
19 : #include <linux/topology.h>
20 : #include <linux/io.h>
21 : #include <linux/slab.h>
22 :
23 : #include <asm/irq.h>
24 : #include <asm/ptrace.h>
25 : #include <asm/irq_regs.h>
26 :
27 : struct seq_file;
28 : struct module;
29 : struct msi_msg;
30 : struct irq_affinity_desc;
31 : enum irqchip_irq_state;
32 :
33 : /*
34 : * IRQ line status.
35 : *
36 : * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
37 : *
38 : * IRQ_TYPE_NONE - default, unspecified type
39 : * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 : * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 : * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 : * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 : * IRQ_TYPE_LEVEL_LOW - low level triggered
44 : * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
45 : * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
46 : * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
47 : * to setup the HW to a sane default (used
48 : * by irqdomain map() callbacks to synchronize
49 : * the HW state and SW flags for a newly
50 : * allocated descriptor).
51 : *
52 : * IRQ_TYPE_PROBE - Special flag for probing in progress
53 : *
54 : * Bits which can be modified via irq_set/clear/modify_status_flags()
55 : * IRQ_LEVEL - Interrupt is level type. Will be also
56 : * updated in the code when the above trigger
57 : * bits are modified via irq_set_irq_type()
58 : * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
59 : * it from affinity setting
60 : * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
61 : * IRQ_NOREQUEST - Interrupt cannot be requested via
62 : * request_irq()
63 : * IRQ_NOTHREAD - Interrupt cannot be threaded
64 : * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
65 : * request/setup_irq()
66 : * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
67 : * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
68 : * IRQ_NESTED_THREAD - Interrupt nests into another thread
69 : * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
70 : * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
71 : * it from the spurious interrupt detection
72 : * mechanism and from core side polling.
73 : * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
74 : * IRQ_HIDDEN - Don't show up in /proc/interrupts
75 : * IRQ_NO_DEBUG - Exclude from note_interrupt() debugging
76 : */
77 : enum {
78 : IRQ_TYPE_NONE = 0x00000000,
79 : IRQ_TYPE_EDGE_RISING = 0x00000001,
80 : IRQ_TYPE_EDGE_FALLING = 0x00000002,
81 : IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
82 : IRQ_TYPE_LEVEL_HIGH = 0x00000004,
83 : IRQ_TYPE_LEVEL_LOW = 0x00000008,
84 : IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
85 : IRQ_TYPE_SENSE_MASK = 0x0000000f,
86 : IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
87 :
88 : IRQ_TYPE_PROBE = 0x00000010,
89 :
90 : IRQ_LEVEL = (1 << 8),
91 : IRQ_PER_CPU = (1 << 9),
92 : IRQ_NOPROBE = (1 << 10),
93 : IRQ_NOREQUEST = (1 << 11),
94 : IRQ_NOAUTOEN = (1 << 12),
95 : IRQ_NO_BALANCING = (1 << 13),
96 : IRQ_MOVE_PCNTXT = (1 << 14),
97 : IRQ_NESTED_THREAD = (1 << 15),
98 : IRQ_NOTHREAD = (1 << 16),
99 : IRQ_PER_CPU_DEVID = (1 << 17),
100 : IRQ_IS_POLLED = (1 << 18),
101 : IRQ_DISABLE_UNLAZY = (1 << 19),
102 : IRQ_HIDDEN = (1 << 20),
103 : IRQ_NO_DEBUG = (1 << 21),
104 : };
105 :
106 : #define IRQF_MODIFY_MASK \
107 : (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
108 : IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
109 : IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
110 : IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN)
111 :
112 : #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
113 :
114 : /*
115 : * Return value for chip->irq_set_affinity()
116 : *
117 : * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
118 : * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
119 : * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
120 : * support stacked irqchips, which indicates skipping
121 : * all descendant irqchips.
122 : */
123 : enum {
124 : IRQ_SET_MASK_OK = 0,
125 : IRQ_SET_MASK_OK_NOCOPY,
126 : IRQ_SET_MASK_OK_DONE,
127 : };
128 :
129 : struct msi_desc;
130 : struct irq_domain;
131 :
132 : /**
133 : * struct irq_common_data - per irq data shared by all irqchips
134 : * @state_use_accessors: status information for irq chip functions.
135 : * Use accessor functions to deal with it
136 : * @node: node index useful for balancing
137 : * @handler_data: per-IRQ data for the irq_chip methods
138 : * @affinity: IRQ affinity on SMP. If this is an IPI
139 : * related irq, then this is the mask of the
140 : * CPUs to which an IPI can be sent.
141 : * @effective_affinity: The effective IRQ affinity on SMP as some irq
142 : * chips do not allow multi CPU destinations.
143 : * A subset of @affinity.
144 : * @msi_desc: MSI descriptor
145 : * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
146 : */
147 : struct irq_common_data {
148 : unsigned int __private state_use_accessors;
149 : #ifdef CONFIG_NUMA
150 : unsigned int node;
151 : #endif
152 : void *handler_data;
153 : struct msi_desc *msi_desc;
154 : #ifdef CONFIG_SMP
155 : cpumask_var_t affinity;
156 : #endif
157 : #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
158 : cpumask_var_t effective_affinity;
159 : #endif
160 : #ifdef CONFIG_GENERIC_IRQ_IPI
161 : unsigned int ipi_offset;
162 : #endif
163 : };
164 :
165 : /**
166 : * struct irq_data - per irq chip data passed down to chip functions
167 : * @mask: precomputed bitmask for accessing the chip registers
168 : * @irq: interrupt number
169 : * @hwirq: hardware interrupt number, local to the interrupt domain
170 : * @common: point to data shared by all irqchips
171 : * @chip: low level interrupt hardware access
172 : * @domain: Interrupt translation domain; responsible for mapping
173 : * between hwirq number and linux irq number.
174 : * @parent_data: pointer to parent struct irq_data to support hierarchy
175 : * irq_domain
176 : * @chip_data: platform-specific per-chip private data for the chip
177 : * methods, to allow shared chip implementations
178 : */
179 : struct irq_data {
180 : u32 mask;
181 : unsigned int irq;
182 : unsigned long hwirq;
183 : struct irq_common_data *common;
184 : struct irq_chip *chip;
185 : struct irq_domain *domain;
186 : #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
187 : struct irq_data *parent_data;
188 : #endif
189 : void *chip_data;
190 : };
191 :
192 : /*
193 : * Bit masks for irq_common_data.state_use_accessors
194 : *
195 : * IRQD_TRIGGER_MASK - Mask for the trigger type bits
196 : * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
197 : * IRQD_ACTIVATED - Interrupt has already been activated
198 : * IRQD_NO_BALANCING - Balancing disabled for this IRQ
199 : * IRQD_PER_CPU - Interrupt is per cpu
200 : * IRQD_AFFINITY_SET - Interrupt affinity was set
201 : * IRQD_LEVEL - Interrupt is level triggered
202 : * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
203 : * from suspend
204 : * IRQD_MOVE_PCNTXT - Interrupt can be moved in process
205 : * context
206 : * IRQD_IRQ_DISABLED - Disabled state of the interrupt
207 : * IRQD_IRQ_MASKED - Masked state of the interrupt
208 : * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
209 : * IRQD_WAKEUP_ARMED - Wakeup mode armed
210 : * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
211 : * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
212 : * IRQD_IRQ_STARTED - Startup state of the interrupt
213 : * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
214 : * mask. Applies only to affinity managed irqs.
215 : * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
216 : * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
217 : * IRQD_CAN_RESERVE - Can use reservation mode
218 : * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change
219 : * required
220 : * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked
221 : * from actual interrupt context.
222 : * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call
223 : * irq_chip::irq_set_affinity() when deactivated.
224 : * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if
225 : * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set.
226 : */
227 : enum {
228 : IRQD_TRIGGER_MASK = 0xf,
229 : IRQD_SETAFFINITY_PENDING = (1 << 8),
230 : IRQD_ACTIVATED = (1 << 9),
231 : IRQD_NO_BALANCING = (1 << 10),
232 : IRQD_PER_CPU = (1 << 11),
233 : IRQD_AFFINITY_SET = (1 << 12),
234 : IRQD_LEVEL = (1 << 13),
235 : IRQD_WAKEUP_STATE = (1 << 14),
236 : IRQD_MOVE_PCNTXT = (1 << 15),
237 : IRQD_IRQ_DISABLED = (1 << 16),
238 : IRQD_IRQ_MASKED = (1 << 17),
239 : IRQD_IRQ_INPROGRESS = (1 << 18),
240 : IRQD_WAKEUP_ARMED = (1 << 19),
241 : IRQD_FORWARDED_TO_VCPU = (1 << 20),
242 : IRQD_AFFINITY_MANAGED = (1 << 21),
243 : IRQD_IRQ_STARTED = (1 << 22),
244 : IRQD_MANAGED_SHUTDOWN = (1 << 23),
245 : IRQD_SINGLE_TARGET = (1 << 24),
246 : IRQD_DEFAULT_TRIGGER_SET = (1 << 25),
247 : IRQD_CAN_RESERVE = (1 << 26),
248 : IRQD_MSI_NOMASK_QUIRK = (1 << 27),
249 : IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28),
250 : IRQD_AFFINITY_ON_ACTIVATE = (1 << 29),
251 : IRQD_IRQ_ENABLED_ON_SUSPEND = (1 << 30),
252 : };
253 :
254 : #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
255 :
256 : static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
257 : {
258 : return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
259 : }
260 :
261 : static inline bool irqd_is_per_cpu(struct irq_data *d)
262 : {
263 : return __irqd_to_state(d) & IRQD_PER_CPU;
264 : }
265 :
266 : static inline bool irqd_can_balance(struct irq_data *d)
267 : {
268 : return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
269 : }
270 :
271 : static inline bool irqd_affinity_was_set(struct irq_data *d)
272 : {
273 : return __irqd_to_state(d) & IRQD_AFFINITY_SET;
274 : }
275 :
276 : static inline void irqd_mark_affinity_was_set(struct irq_data *d)
277 : {
278 : __irqd_to_state(d) |= IRQD_AFFINITY_SET;
279 : }
280 :
281 : static inline bool irqd_trigger_type_was_set(struct irq_data *d)
282 : {
283 0 : return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET;
284 : }
285 :
286 : static inline u32 irqd_get_trigger_type(struct irq_data *d)
287 : {
288 2 : return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
289 : }
290 :
291 : /*
292 : * Must only be called inside irq_chip.irq_set_type() functions or
293 : * from the DT/ACPI setup code.
294 : */
295 : static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
296 : {
297 0 : __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
298 0 : __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
299 0 : __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET;
300 : }
301 :
302 : static inline bool irqd_is_level_type(struct irq_data *d)
303 : {
304 : return __irqd_to_state(d) & IRQD_LEVEL;
305 : }
306 :
307 : /*
308 : * Must only be called of irqchip.irq_set_affinity() or low level
309 : * hierarchy domain allocation functions.
310 : */
311 : static inline void irqd_set_single_target(struct irq_data *d)
312 : {
313 : __irqd_to_state(d) |= IRQD_SINGLE_TARGET;
314 : }
315 :
316 : static inline bool irqd_is_single_target(struct irq_data *d)
317 : {
318 : return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
319 : }
320 :
321 : static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d)
322 : {
323 : __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX;
324 : }
325 :
326 : static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d)
327 : {
328 : return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX;
329 : }
330 :
331 : static inline bool irqd_is_enabled_on_suspend(struct irq_data *d)
332 : {
333 0 : return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND;
334 : }
335 :
336 : static inline bool irqd_is_wakeup_set(struct irq_data *d)
337 : {
338 0 : return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
339 : }
340 :
341 : static inline bool irqd_can_move_in_process_context(struct irq_data *d)
342 : {
343 : return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
344 : }
345 :
346 : static inline bool irqd_irq_disabled(struct irq_data *d)
347 : {
348 2945 : return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
349 : }
350 :
351 : static inline bool irqd_irq_masked(struct irq_data *d)
352 : {
353 0 : return __irqd_to_state(d) & IRQD_IRQ_MASKED;
354 : }
355 :
356 : static inline bool irqd_irq_inprogress(struct irq_data *d)
357 : {
358 0 : return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
359 : }
360 :
361 : static inline bool irqd_is_wakeup_armed(struct irq_data *d)
362 : {
363 0 : return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
364 : }
365 :
366 : static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
367 : {
368 : return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
369 : }
370 :
371 : static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
372 : {
373 : __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
374 : }
375 :
376 : static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
377 : {
378 : __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
379 : }
380 :
381 : static inline bool irqd_affinity_is_managed(struct irq_data *d)
382 : {
383 2 : return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
384 : }
385 :
386 : static inline bool irqd_is_activated(struct irq_data *d)
387 : {
388 4 : return __irqd_to_state(d) & IRQD_ACTIVATED;
389 : }
390 :
391 : static inline void irqd_set_activated(struct irq_data *d)
392 : {
393 2 : __irqd_to_state(d) |= IRQD_ACTIVATED;
394 : }
395 :
396 : static inline void irqd_clr_activated(struct irq_data *d)
397 : {
398 0 : __irqd_to_state(d) &= ~IRQD_ACTIVATED;
399 : }
400 :
401 : static inline bool irqd_is_started(struct irq_data *d)
402 : {
403 2 : return __irqd_to_state(d) & IRQD_IRQ_STARTED;
404 : }
405 :
406 : static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
407 : {
408 : return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
409 : }
410 :
411 : static inline void irqd_set_can_reserve(struct irq_data *d)
412 : {
413 : __irqd_to_state(d) |= IRQD_CAN_RESERVE;
414 : }
415 :
416 : static inline void irqd_clr_can_reserve(struct irq_data *d)
417 : {
418 0 : __irqd_to_state(d) &= ~IRQD_CAN_RESERVE;
419 : }
420 :
421 : static inline bool irqd_can_reserve(struct irq_data *d)
422 : {
423 : return __irqd_to_state(d) & IRQD_CAN_RESERVE;
424 : }
425 :
426 : static inline void irqd_set_msi_nomask_quirk(struct irq_data *d)
427 : {
428 0 : __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK;
429 : }
430 :
431 : static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d)
432 : {
433 : __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK;
434 : }
435 :
436 : static inline bool irqd_msi_nomask_quirk(struct irq_data *d)
437 : {
438 : return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK;
439 : }
440 :
441 : static inline void irqd_set_affinity_on_activate(struct irq_data *d)
442 : {
443 : __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE;
444 : }
445 :
446 : static inline bool irqd_affinity_on_activate(struct irq_data *d)
447 : {
448 : return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE;
449 : }
450 :
451 : #undef __irqd_to_state
452 :
453 : static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
454 : {
455 : return d->hwirq;
456 : }
457 :
458 : /**
459 : * struct irq_chip - hardware interrupt chip descriptor
460 : *
461 : * @name: name for /proc/interrupts
462 : * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
463 : * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
464 : * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
465 : * @irq_disable: disable the interrupt
466 : * @irq_ack: start of a new interrupt
467 : * @irq_mask: mask an interrupt source
468 : * @irq_mask_ack: ack and mask an interrupt source
469 : * @irq_unmask: unmask an interrupt source
470 : * @irq_eoi: end of interrupt
471 : * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
472 : * argument is true, it tells the driver to
473 : * unconditionally apply the affinity setting. Sanity
474 : * checks against the supplied affinity mask are not
475 : * required. This is used for CPU hotplug where the
476 : * target CPU is not yet set in the cpu_online_mask.
477 : * @irq_retrigger: resend an IRQ to the CPU
478 : * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
479 : * @irq_set_wake: enable/disable power-management wake-on of an IRQ
480 : * @irq_bus_lock: function to lock access to slow bus (i2c) chips
481 : * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
482 : * @irq_cpu_online: configure an interrupt source for a secondary CPU
483 : * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
484 : * @irq_suspend: function called from core code on suspend once per
485 : * chip, when one or more interrupts are installed
486 : * @irq_resume: function called from core code on resume once per chip,
487 : * when one ore more interrupts are installed
488 : * @irq_pm_shutdown: function called from core code on shutdown once per chip
489 : * @irq_calc_mask: Optional function to set irq_data.mask for special cases
490 : * @irq_print_chip: optional to print special chip info in show_interrupts
491 : * @irq_request_resources: optional to request resources before calling
492 : * any other callback related to this irq
493 : * @irq_release_resources: optional to release resources acquired with
494 : * irq_request_resources
495 : * @irq_compose_msi_msg: optional to compose message content for MSI
496 : * @irq_write_msi_msg: optional to write message content for MSI
497 : * @irq_get_irqchip_state: return the internal state of an interrupt
498 : * @irq_set_irqchip_state: set the internal state of a interrupt
499 : * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
500 : * @ipi_send_single: send a single IPI to destination cpus
501 : * @ipi_send_mask: send an IPI to destination cpus in cpumask
502 : * @irq_nmi_setup: function called from core code before enabling an NMI
503 : * @irq_nmi_teardown: function called from core code after disabling an NMI
504 : * @flags: chip specific flags
505 : */
506 : struct irq_chip {
507 : const char *name;
508 : unsigned int (*irq_startup)(struct irq_data *data);
509 : void (*irq_shutdown)(struct irq_data *data);
510 : void (*irq_enable)(struct irq_data *data);
511 : void (*irq_disable)(struct irq_data *data);
512 :
513 : void (*irq_ack)(struct irq_data *data);
514 : void (*irq_mask)(struct irq_data *data);
515 : void (*irq_mask_ack)(struct irq_data *data);
516 : void (*irq_unmask)(struct irq_data *data);
517 : void (*irq_eoi)(struct irq_data *data);
518 :
519 : int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
520 : int (*irq_retrigger)(struct irq_data *data);
521 : int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
522 : int (*irq_set_wake)(struct irq_data *data, unsigned int on);
523 :
524 : void (*irq_bus_lock)(struct irq_data *data);
525 : void (*irq_bus_sync_unlock)(struct irq_data *data);
526 :
527 : #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE
528 : void (*irq_cpu_online)(struct irq_data *data);
529 : void (*irq_cpu_offline)(struct irq_data *data);
530 : #endif
531 : void (*irq_suspend)(struct irq_data *data);
532 : void (*irq_resume)(struct irq_data *data);
533 : void (*irq_pm_shutdown)(struct irq_data *data);
534 :
535 : void (*irq_calc_mask)(struct irq_data *data);
536 :
537 : void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
538 : int (*irq_request_resources)(struct irq_data *data);
539 : void (*irq_release_resources)(struct irq_data *data);
540 :
541 : void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
542 : void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
543 :
544 : int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
545 : int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
546 :
547 : int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
548 :
549 : void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
550 : void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
551 :
552 : int (*irq_nmi_setup)(struct irq_data *data);
553 : void (*irq_nmi_teardown)(struct irq_data *data);
554 :
555 : unsigned long flags;
556 : };
557 :
558 : /*
559 : * irq_chip specific flags
560 : *
561 : * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
562 : * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
563 : * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
564 : * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
565 : * when irq enabled
566 : * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
567 : * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
568 : * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
569 : * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs
570 : * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips
571 : * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs
572 : * in the suspend path if they are in disabled state
573 : * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup
574 : * IRQCHIP_IMMUTABLE: Don't ever change anything in this chip
575 : */
576 : enum {
577 : IRQCHIP_SET_TYPE_MASKED = (1 << 0),
578 : IRQCHIP_EOI_IF_HANDLED = (1 << 1),
579 : IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
580 : IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
581 : IRQCHIP_SKIP_SET_WAKE = (1 << 4),
582 : IRQCHIP_ONESHOT_SAFE = (1 << 5),
583 : IRQCHIP_EOI_THREADED = (1 << 6),
584 : IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
585 : IRQCHIP_SUPPORTS_NMI = (1 << 8),
586 : IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9),
587 : IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10),
588 : IRQCHIP_IMMUTABLE = (1 << 11),
589 : };
590 :
591 : #include <linux/irqdesc.h>
592 :
593 : /*
594 : * Pick up the arch-dependent methods:
595 : */
596 : #include <asm/hw_irq.h>
597 :
598 : #ifndef NR_IRQS_LEGACY
599 : # define NR_IRQS_LEGACY 0
600 : #endif
601 :
602 : #ifndef ARCH_IRQ_INIT_FLAGS
603 : # define ARCH_IRQ_INIT_FLAGS 0
604 : #endif
605 :
606 : #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
607 :
608 : struct irqaction;
609 : extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
610 : extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
611 :
612 : #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE
613 : extern void irq_cpu_online(void);
614 : extern void irq_cpu_offline(void);
615 : #endif
616 : extern int irq_set_affinity_locked(struct irq_data *data,
617 : const struct cpumask *cpumask, bool force);
618 : extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
619 :
620 : #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
621 : extern void irq_migrate_all_off_this_cpu(void);
622 : extern int irq_affinity_online_cpu(unsigned int cpu);
623 : #else
624 : # define irq_affinity_online_cpu NULL
625 : #endif
626 :
627 : #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
628 : void __irq_move_irq(struct irq_data *data);
629 : static inline void irq_move_irq(struct irq_data *data)
630 : {
631 : if (unlikely(irqd_is_setaffinity_pending(data)))
632 : __irq_move_irq(data);
633 : }
634 : void irq_move_masked_irq(struct irq_data *data);
635 : void irq_force_complete_move(struct irq_desc *desc);
636 : #else
637 : static inline void irq_move_irq(struct irq_data *data) { }
638 : static inline void irq_move_masked_irq(struct irq_data *data) { }
639 : static inline void irq_force_complete_move(struct irq_desc *desc) { }
640 : #endif
641 :
642 : extern int no_irq_affinity;
643 :
644 : #ifdef CONFIG_HARDIRQS_SW_RESEND
645 : int irq_set_parent(int irq, int parent_irq);
646 : #else
647 : static inline int irq_set_parent(int irq, int parent_irq)
648 : {
649 : return 0;
650 : }
651 : #endif
652 :
653 : /*
654 : * Built-in IRQ handlers for various IRQ types,
655 : * callable via desc->handle_irq()
656 : */
657 : extern void handle_level_irq(struct irq_desc *desc);
658 : extern void handle_fasteoi_irq(struct irq_desc *desc);
659 : extern void handle_edge_irq(struct irq_desc *desc);
660 : extern void handle_edge_eoi_irq(struct irq_desc *desc);
661 : extern void handle_simple_irq(struct irq_desc *desc);
662 : extern void handle_untracked_irq(struct irq_desc *desc);
663 : extern void handle_percpu_irq(struct irq_desc *desc);
664 : extern void handle_percpu_devid_irq(struct irq_desc *desc);
665 : extern void handle_bad_irq(struct irq_desc *desc);
666 : extern void handle_nested_irq(unsigned int irq);
667 :
668 : extern void handle_fasteoi_nmi(struct irq_desc *desc);
669 : extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc);
670 :
671 : extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
672 : extern int irq_chip_pm_get(struct irq_data *data);
673 : extern int irq_chip_pm_put(struct irq_data *data);
674 : #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
675 : extern void handle_fasteoi_ack_irq(struct irq_desc *desc);
676 : extern void handle_fasteoi_mask_irq(struct irq_desc *desc);
677 : extern int irq_chip_set_parent_state(struct irq_data *data,
678 : enum irqchip_irq_state which,
679 : bool val);
680 : extern int irq_chip_get_parent_state(struct irq_data *data,
681 : enum irqchip_irq_state which,
682 : bool *state);
683 : extern void irq_chip_enable_parent(struct irq_data *data);
684 : extern void irq_chip_disable_parent(struct irq_data *data);
685 : extern void irq_chip_ack_parent(struct irq_data *data);
686 : extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
687 : extern void irq_chip_mask_parent(struct irq_data *data);
688 : extern void irq_chip_mask_ack_parent(struct irq_data *data);
689 : extern void irq_chip_unmask_parent(struct irq_data *data);
690 : extern void irq_chip_eoi_parent(struct irq_data *data);
691 : extern int irq_chip_set_affinity_parent(struct irq_data *data,
692 : const struct cpumask *dest,
693 : bool force);
694 : extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
695 : extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
696 : void *vcpu_info);
697 : extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
698 : extern int irq_chip_request_resources_parent(struct irq_data *data);
699 : extern void irq_chip_release_resources_parent(struct irq_data *data);
700 : #endif
701 :
702 : /* Handling of unhandled and spurious interrupts: */
703 : extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
704 :
705 :
706 : /* Enable/disable irq debugging output: */
707 : extern int noirqdebug_setup(char *str);
708 :
709 : /* Checks whether the interrupt can be requested by request_irq(): */
710 : extern int can_request_irq(unsigned int irq, unsigned long irqflags);
711 :
712 : /* Dummy irq-chip implementations: */
713 : extern struct irq_chip no_irq_chip;
714 : extern struct irq_chip dummy_irq_chip;
715 :
716 : extern void
717 : irq_set_chip_and_handler_name(unsigned int irq, const struct irq_chip *chip,
718 : irq_flow_handler_t handle, const char *name);
719 :
720 : static inline void irq_set_chip_and_handler(unsigned int irq,
721 : const struct irq_chip *chip,
722 : irq_flow_handler_t handle)
723 : {
724 64 : irq_set_chip_and_handler_name(irq, chip, handle, NULL);
725 : }
726 :
727 : extern int irq_set_percpu_devid(unsigned int irq);
728 : extern int irq_set_percpu_devid_partition(unsigned int irq,
729 : const struct cpumask *affinity);
730 : extern int irq_get_percpu_devid_partition(unsigned int irq,
731 : struct cpumask *affinity);
732 :
733 : extern void
734 : __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
735 : const char *name);
736 :
737 : static inline void
738 : irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
739 : {
740 0 : __irq_set_handler(irq, handle, 0, NULL);
741 : }
742 :
743 : /*
744 : * Set a highlevel chained flow handler for a given IRQ.
745 : * (a chained handler is automatically enabled and set to
746 : * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
747 : */
748 : static inline void
749 : irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
750 : {
751 : __irq_set_handler(irq, handle, 1, NULL);
752 : }
753 :
754 : /*
755 : * Set a highlevel chained flow handler and its data for a given IRQ.
756 : * (a chained handler is automatically enabled and set to
757 : * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
758 : */
759 : void
760 : irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
761 : void *data);
762 :
763 : void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
764 :
765 : static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
766 : {
767 0 : irq_modify_status(irq, 0, set);
768 : }
769 :
770 : static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
771 : {
772 0 : irq_modify_status(irq, clr, 0);
773 : }
774 :
775 : static inline void irq_set_noprobe(unsigned int irq)
776 : {
777 : irq_modify_status(irq, 0, IRQ_NOPROBE);
778 : }
779 :
780 : static inline void irq_set_probe(unsigned int irq)
781 : {
782 : irq_modify_status(irq, IRQ_NOPROBE, 0);
783 : }
784 :
785 : static inline void irq_set_nothread(unsigned int irq)
786 : {
787 : irq_modify_status(irq, 0, IRQ_NOTHREAD);
788 : }
789 :
790 : static inline void irq_set_thread(unsigned int irq)
791 : {
792 : irq_modify_status(irq, IRQ_NOTHREAD, 0);
793 : }
794 :
795 : static inline void irq_set_nested_thread(unsigned int irq, bool nest)
796 : {
797 : if (nest)
798 : irq_set_status_flags(irq, IRQ_NESTED_THREAD);
799 : else
800 : irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
801 : }
802 :
803 : static inline void irq_set_percpu_devid_flags(unsigned int irq)
804 : {
805 0 : irq_set_status_flags(irq,
806 : IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
807 : IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
808 : }
809 :
810 : /* Set/get chip/data for an IRQ: */
811 : extern int irq_set_chip(unsigned int irq, const struct irq_chip *chip);
812 : extern int irq_set_handler_data(unsigned int irq, void *data);
813 : extern int irq_set_chip_data(unsigned int irq, void *data);
814 : extern int irq_set_irq_type(unsigned int irq, unsigned int type);
815 : extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
816 : extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
817 : struct msi_desc *entry);
818 : extern struct irq_data *irq_get_irq_data(unsigned int irq);
819 :
820 : static inline struct irq_chip *irq_get_chip(unsigned int irq)
821 : {
822 : struct irq_data *d = irq_get_irq_data(irq);
823 : return d ? d->chip : NULL;
824 : }
825 :
826 : static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
827 : {
828 : return d->chip;
829 : }
830 :
831 : static inline void *irq_get_chip_data(unsigned int irq)
832 : {
833 : struct irq_data *d = irq_get_irq_data(irq);
834 : return d ? d->chip_data : NULL;
835 : }
836 :
837 : static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
838 : {
839 : return d->chip_data;
840 : }
841 :
842 : static inline void *irq_get_handler_data(unsigned int irq)
843 : {
844 : struct irq_data *d = irq_get_irq_data(irq);
845 : return d ? d->common->handler_data : NULL;
846 : }
847 :
848 : static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
849 : {
850 : return d->common->handler_data;
851 : }
852 :
853 : static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
854 : {
855 0 : struct irq_data *d = irq_get_irq_data(irq);
856 0 : return d ? d->common->msi_desc : NULL;
857 : }
858 :
859 : static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
860 : {
861 0 : return d->common->msi_desc;
862 : }
863 :
864 : static inline u32 irq_get_trigger_type(unsigned int irq)
865 : {
866 0 : struct irq_data *d = irq_get_irq_data(irq);
867 0 : return d ? irqd_get_trigger_type(d) : 0;
868 : }
869 :
870 : static inline int irq_common_data_get_node(struct irq_common_data *d)
871 : {
872 : #ifdef CONFIG_NUMA
873 : return d->node;
874 : #else
875 : return 0;
876 : #endif
877 : }
878 :
879 : static inline int irq_data_get_node(struct irq_data *d)
880 : {
881 0 : return irq_common_data_get_node(d->common);
882 : }
883 :
884 : static inline
885 : const struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
886 : {
887 : #ifdef CONFIG_SMP
888 : return d->common->affinity;
889 : #else
890 2 : return cpumask_of(0);
891 : #endif
892 : }
893 :
894 : static inline void irq_data_update_affinity(struct irq_data *d,
895 : const struct cpumask *m)
896 : {
897 : #ifdef CONFIG_SMP
898 : cpumask_copy(d->common->affinity, m);
899 : #endif
900 : }
901 :
902 : static inline const struct cpumask *irq_get_affinity_mask(int irq)
903 : {
904 : struct irq_data *d = irq_get_irq_data(irq);
905 :
906 : return d ? irq_data_get_affinity_mask(d) : NULL;
907 : }
908 :
909 : #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
910 : static inline
911 : const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
912 : {
913 : return d->common->effective_affinity;
914 : }
915 : static inline void irq_data_update_effective_affinity(struct irq_data *d,
916 : const struct cpumask *m)
917 : {
918 : cpumask_copy(d->common->effective_affinity, m);
919 : }
920 : #else
921 : static inline void irq_data_update_effective_affinity(struct irq_data *d,
922 : const struct cpumask *m)
923 : {
924 : }
925 : static inline
926 : const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
927 : {
928 : return irq_data_get_affinity_mask(d);
929 : }
930 : #endif
931 :
932 : static inline
933 : const struct cpumask *irq_get_effective_affinity_mask(unsigned int irq)
934 : {
935 : struct irq_data *d = irq_get_irq_data(irq);
936 :
937 : return d ? irq_data_get_effective_affinity_mask(d) : NULL;
938 : }
939 :
940 : unsigned int arch_dynirq_lower_bound(unsigned int from);
941 :
942 : int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
943 : struct module *owner,
944 : const struct irq_affinity_desc *affinity);
945 :
946 : int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
947 : unsigned int cnt, int node, struct module *owner,
948 : const struct irq_affinity_desc *affinity);
949 :
950 : /* use macros to avoid needing export.h for THIS_MODULE */
951 : #define irq_alloc_descs(irq, from, cnt, node) \
952 : __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
953 :
954 : #define irq_alloc_desc(node) \
955 : irq_alloc_descs(-1, 1, 1, node)
956 :
957 : #define irq_alloc_desc_at(at, node) \
958 : irq_alloc_descs(at, at, 1, node)
959 :
960 : #define irq_alloc_desc_from(from, node) \
961 : irq_alloc_descs(-1, from, 1, node)
962 :
963 : #define irq_alloc_descs_from(from, cnt, node) \
964 : irq_alloc_descs(-1, from, cnt, node)
965 :
966 : #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
967 : __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
968 :
969 : #define devm_irq_alloc_desc(dev, node) \
970 : devm_irq_alloc_descs(dev, -1, 1, 1, node)
971 :
972 : #define devm_irq_alloc_desc_at(dev, at, node) \
973 : devm_irq_alloc_descs(dev, at, at, 1, node)
974 :
975 : #define devm_irq_alloc_desc_from(dev, from, node) \
976 : devm_irq_alloc_descs(dev, -1, from, 1, node)
977 :
978 : #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
979 : devm_irq_alloc_descs(dev, -1, from, cnt, node)
980 :
981 : void irq_free_descs(unsigned int irq, unsigned int cnt);
982 : static inline void irq_free_desc(unsigned int irq)
983 : {
984 0 : irq_free_descs(irq, 1);
985 : }
986 :
987 : #ifdef CONFIG_GENERIC_IRQ_LEGACY
988 : void irq_init_desc(unsigned int irq);
989 : #endif
990 :
991 : /**
992 : * struct irq_chip_regs - register offsets for struct irq_gci
993 : * @enable: Enable register offset to reg_base
994 : * @disable: Disable register offset to reg_base
995 : * @mask: Mask register offset to reg_base
996 : * @ack: Ack register offset to reg_base
997 : * @eoi: Eoi register offset to reg_base
998 : * @type: Type configuration register offset to reg_base
999 : * @polarity: Polarity configuration register offset to reg_base
1000 : */
1001 : struct irq_chip_regs {
1002 : unsigned long enable;
1003 : unsigned long disable;
1004 : unsigned long mask;
1005 : unsigned long ack;
1006 : unsigned long eoi;
1007 : unsigned long type;
1008 : unsigned long polarity;
1009 : };
1010 :
1011 : /**
1012 : * struct irq_chip_type - Generic interrupt chip instance for a flow type
1013 : * @chip: The real interrupt chip which provides the callbacks
1014 : * @regs: Register offsets for this chip
1015 : * @handler: Flow handler associated with this chip
1016 : * @type: Chip can handle these flow types
1017 : * @mask_cache_priv: Cached mask register private to the chip type
1018 : * @mask_cache: Pointer to cached mask register
1019 : *
1020 : * A irq_generic_chip can have several instances of irq_chip_type when
1021 : * it requires different functions and register offsets for different
1022 : * flow types.
1023 : */
1024 : struct irq_chip_type {
1025 : struct irq_chip chip;
1026 : struct irq_chip_regs regs;
1027 : irq_flow_handler_t handler;
1028 : u32 type;
1029 : u32 mask_cache_priv;
1030 : u32 *mask_cache;
1031 : };
1032 :
1033 : /**
1034 : * struct irq_chip_generic - Generic irq chip data structure
1035 : * @lock: Lock to protect register and cache data access
1036 : * @reg_base: Register base address (virtual)
1037 : * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
1038 : * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
1039 : * @suspend: Function called from core code on suspend once per
1040 : * chip; can be useful instead of irq_chip::suspend to
1041 : * handle chip details even when no interrupts are in use
1042 : * @resume: Function called from core code on resume once per chip;
1043 : * can be useful instead of irq_chip::suspend to handle
1044 : * chip details even when no interrupts are in use
1045 : * @irq_base: Interrupt base nr for this chip
1046 : * @irq_cnt: Number of interrupts handled by this chip
1047 : * @mask_cache: Cached mask register shared between all chip types
1048 : * @type_cache: Cached type register
1049 : * @polarity_cache: Cached polarity register
1050 : * @wake_enabled: Interrupt can wakeup from suspend
1051 : * @wake_active: Interrupt is marked as an wakeup from suspend source
1052 : * @num_ct: Number of available irq_chip_type instances (usually 1)
1053 : * @private: Private data for non generic chip callbacks
1054 : * @installed: bitfield to denote installed interrupts
1055 : * @unused: bitfield to denote unused interrupts
1056 : * @domain: irq domain pointer
1057 : * @list: List head for keeping track of instances
1058 : * @chip_types: Array of interrupt irq_chip_types
1059 : *
1060 : * Note, that irq_chip_generic can have multiple irq_chip_type
1061 : * implementations which can be associated to a particular irq line of
1062 : * an irq_chip_generic instance. That allows to share and protect
1063 : * state in an irq_chip_generic instance when we need to implement
1064 : * different flow mechanisms (level/edge) for it.
1065 : */
1066 : struct irq_chip_generic {
1067 : raw_spinlock_t lock;
1068 : void __iomem *reg_base;
1069 : u32 (*reg_readl)(void __iomem *addr);
1070 : void (*reg_writel)(u32 val, void __iomem *addr);
1071 : void (*suspend)(struct irq_chip_generic *gc);
1072 : void (*resume)(struct irq_chip_generic *gc);
1073 : unsigned int irq_base;
1074 : unsigned int irq_cnt;
1075 : u32 mask_cache;
1076 : u32 type_cache;
1077 : u32 polarity_cache;
1078 : u32 wake_enabled;
1079 : u32 wake_active;
1080 : unsigned int num_ct;
1081 : void *private;
1082 : unsigned long installed;
1083 : unsigned long unused;
1084 : struct irq_domain *domain;
1085 : struct list_head list;
1086 : struct irq_chip_type chip_types[];
1087 : };
1088 :
1089 : /**
1090 : * enum irq_gc_flags - Initialization flags for generic irq chips
1091 : * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
1092 : * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
1093 : * irq chips which need to call irq_set_wake() on
1094 : * the parent irq. Usually GPIO implementations
1095 : * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
1096 : * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
1097 : * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
1098 : */
1099 : enum irq_gc_flags {
1100 : IRQ_GC_INIT_MASK_CACHE = 1 << 0,
1101 : IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
1102 : IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
1103 : IRQ_GC_NO_MASK = 1 << 3,
1104 : IRQ_GC_BE_IO = 1 << 4,
1105 : };
1106 :
1107 : /*
1108 : * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1109 : * @irqs_per_chip: Number of interrupts per chip
1110 : * @num_chips: Number of chips
1111 : * @irq_flags_to_set: IRQ* flags to set on irq setup
1112 : * @irq_flags_to_clear: IRQ* flags to clear on irq setup
1113 : * @gc_flags: Generic chip specific setup flags
1114 : * @gc: Array of pointers to generic interrupt chips
1115 : */
1116 : struct irq_domain_chip_generic {
1117 : unsigned int irqs_per_chip;
1118 : unsigned int num_chips;
1119 : unsigned int irq_flags_to_clear;
1120 : unsigned int irq_flags_to_set;
1121 : enum irq_gc_flags gc_flags;
1122 : struct irq_chip_generic *gc[];
1123 : };
1124 :
1125 : /* Generic chip callback functions */
1126 : void irq_gc_noop(struct irq_data *d);
1127 : void irq_gc_mask_disable_reg(struct irq_data *d);
1128 : void irq_gc_mask_set_bit(struct irq_data *d);
1129 : void irq_gc_mask_clr_bit(struct irq_data *d);
1130 : void irq_gc_unmask_enable_reg(struct irq_data *d);
1131 : void irq_gc_ack_set_bit(struct irq_data *d);
1132 : void irq_gc_ack_clr_bit(struct irq_data *d);
1133 : void irq_gc_mask_disable_and_ack_set(struct irq_data *d);
1134 : void irq_gc_eoi(struct irq_data *d);
1135 : int irq_gc_set_wake(struct irq_data *d, unsigned int on);
1136 :
1137 : /* Setup functions for irq_chip_generic */
1138 : int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
1139 : irq_hw_number_t hw_irq);
1140 : void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq);
1141 : struct irq_chip_generic *
1142 : irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
1143 : void __iomem *reg_base, irq_flow_handler_t handler);
1144 : void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
1145 : enum irq_gc_flags flags, unsigned int clr,
1146 : unsigned int set);
1147 : int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
1148 : void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
1149 : unsigned int clr, unsigned int set);
1150 :
1151 : struct irq_chip_generic *
1152 : devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
1153 : unsigned int irq_base, void __iomem *reg_base,
1154 : irq_flow_handler_t handler);
1155 : int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
1156 : u32 msk, enum irq_gc_flags flags,
1157 : unsigned int clr, unsigned int set);
1158 :
1159 : struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
1160 :
1161 : int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
1162 : int num_ct, const char *name,
1163 : irq_flow_handler_t handler,
1164 : unsigned int clr, unsigned int set,
1165 : enum irq_gc_flags flags);
1166 :
1167 : #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1168 : handler, clr, set, flags) \
1169 : ({ \
1170 : MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1171 : __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1172 : handler, clr, set, flags); \
1173 : })
1174 :
1175 : static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
1176 : {
1177 : kfree(gc);
1178 : }
1179 :
1180 : static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
1181 : u32 msk, unsigned int clr,
1182 : unsigned int set)
1183 : {
1184 : irq_remove_generic_chip(gc, msk, clr, set);
1185 : irq_free_generic_chip(gc);
1186 : }
1187 :
1188 : static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
1189 : {
1190 : return container_of(d->chip, struct irq_chip_type, chip);
1191 : }
1192 :
1193 : #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1194 :
1195 : #ifdef CONFIG_SMP
1196 : static inline void irq_gc_lock(struct irq_chip_generic *gc)
1197 : {
1198 : raw_spin_lock(&gc->lock);
1199 : }
1200 :
1201 : static inline void irq_gc_unlock(struct irq_chip_generic *gc)
1202 : {
1203 : raw_spin_unlock(&gc->lock);
1204 : }
1205 : #else
1206 : static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
1207 : static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
1208 : #endif
1209 :
1210 : /*
1211 : * The irqsave variants are for usage in non interrupt code. Do not use
1212 : * them in irq_chip callbacks. Use irq_gc_lock() instead.
1213 : */
1214 : #define irq_gc_lock_irqsave(gc, flags) \
1215 : raw_spin_lock_irqsave(&(gc)->lock, flags)
1216 :
1217 : #define irq_gc_unlock_irqrestore(gc, flags) \
1218 : raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1219 :
1220 : static inline void irq_reg_writel(struct irq_chip_generic *gc,
1221 : u32 val, int reg_offset)
1222 : {
1223 : if (gc->reg_writel)
1224 : gc->reg_writel(val, gc->reg_base + reg_offset);
1225 : else
1226 : writel(val, gc->reg_base + reg_offset);
1227 : }
1228 :
1229 : static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1230 : int reg_offset)
1231 : {
1232 : if (gc->reg_readl)
1233 : return gc->reg_readl(gc->reg_base + reg_offset);
1234 : else
1235 : return readl(gc->reg_base + reg_offset);
1236 : }
1237 :
1238 : struct irq_matrix;
1239 : struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits,
1240 : unsigned int alloc_start,
1241 : unsigned int alloc_end);
1242 : void irq_matrix_online(struct irq_matrix *m);
1243 : void irq_matrix_offline(struct irq_matrix *m);
1244 : void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace);
1245 : int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk);
1246 : void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk);
1247 : int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk,
1248 : unsigned int *mapped_cpu);
1249 : void irq_matrix_reserve(struct irq_matrix *m);
1250 : void irq_matrix_remove_reserved(struct irq_matrix *m);
1251 : int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk,
1252 : bool reserved, unsigned int *mapped_cpu);
1253 : void irq_matrix_free(struct irq_matrix *m, unsigned int cpu,
1254 : unsigned int bit, bool managed);
1255 : void irq_matrix_assign(struct irq_matrix *m, unsigned int bit);
1256 : unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown);
1257 : unsigned int irq_matrix_allocated(struct irq_matrix *m);
1258 : unsigned int irq_matrix_reserved(struct irq_matrix *m);
1259 : void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind);
1260 :
1261 : /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1262 : #define INVALID_HWIRQ (~0UL)
1263 : irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
1264 : int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1265 : int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1266 : int ipi_send_single(unsigned int virq, unsigned int cpu);
1267 : int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
1268 :
1269 : void ipi_mux_process(void);
1270 : int ipi_mux_create(unsigned int nr_ipi, void (*mux_send)(unsigned int cpu));
1271 :
1272 : #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1273 : /*
1274 : * Registers a generic IRQ handling function as the top-level IRQ handler in
1275 : * the system, which is generally the first C code called from an assembly
1276 : * architecture-specific interrupt handler.
1277 : *
1278 : * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1279 : * registered.
1280 : */
1281 : int __init set_handle_irq(void (*handle_irq)(struct pt_regs *));
1282 :
1283 : /*
1284 : * Allows interrupt handlers to find the irqchip that's been registered as the
1285 : * top-level IRQ handler.
1286 : */
1287 : extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init;
1288 : asmlinkage void generic_handle_arch_irq(struct pt_regs *regs);
1289 : #else
1290 : #ifndef set_handle_irq
1291 : #define set_handle_irq(handle_irq) \
1292 : do { \
1293 : (void)handle_irq; \
1294 : WARN_ON(1); \
1295 : } while (0)
1296 : #endif
1297 : #endif
1298 :
1299 : #endif /* _LINUX_IRQ_H */
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