Line data Source code
1 : /* SPDX-License-Identifier: GPL-2.0 */
2 : /*
3 : * pci.h
4 : *
5 : * PCI defines and function prototypes
6 : * Copyright 1994, Drew Eckhardt
7 : * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 : *
9 : * PCI Express ASPM defines and function prototypes
10 : * Copyright (c) 2007 Intel Corp.
11 : * Zhang Yanmin (yanmin.zhang@intel.com)
12 : * Shaohua Li (shaohua.li@intel.com)
13 : *
14 : * For more information, please consult the following manuals (look at
15 : * http://www.pcisig.com/ for how to get them):
16 : *
17 : * PCI BIOS Specification
18 : * PCI Local Bus Specification
19 : * PCI to PCI Bridge Specification
20 : * PCI Express Specification
21 : * PCI System Design Guide
22 : */
23 : #ifndef LINUX_PCI_H
24 : #define LINUX_PCI_H
25 :
26 :
27 : #include <linux/mod_devicetable.h>
28 :
29 : #include <linux/types.h>
30 : #include <linux/init.h>
31 : #include <linux/ioport.h>
32 : #include <linux/list.h>
33 : #include <linux/compiler.h>
34 : #include <linux/errno.h>
35 : #include <linux/kobject.h>
36 : #include <linux/atomic.h>
37 : #include <linux/device.h>
38 : #include <linux/interrupt.h>
39 : #include <linux/io.h>
40 : #include <linux/resource_ext.h>
41 : #include <linux/msi_api.h>
42 : #include <uapi/linux/pci.h>
43 :
44 : #include <linux/pci_ids.h>
45 :
46 : #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 : PCI_STATUS_SIG_SYSTEM_ERROR | \
48 : PCI_STATUS_REC_MASTER_ABORT | \
49 : PCI_STATUS_REC_TARGET_ABORT | \
50 : PCI_STATUS_SIG_TARGET_ABORT | \
51 : PCI_STATUS_PARITY)
52 :
53 : /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
54 : #define PCI_NUM_RESET_METHODS 7
55 :
56 : #define PCI_RESET_PROBE true
57 : #define PCI_RESET_DO_RESET false
58 :
59 : /*
60 : * The PCI interface treats multi-function devices as independent
61 : * devices. The slot/function address of each device is encoded
62 : * in a single byte as follows:
63 : *
64 : * 7:3 = slot
65 : * 2:0 = function
66 : *
67 : * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
68 : * In the interest of not exposing interfaces to user-space unnecessarily,
69 : * the following kernel-only defines are being added here.
70 : */
71 : #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
72 : /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73 : #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74 :
75 : /* pci_slot represents a physical slot */
76 : struct pci_slot {
77 : struct pci_bus *bus; /* Bus this slot is on */
78 : struct list_head list; /* Node in list of slots */
79 : struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 : unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
81 : struct kobject kobj;
82 : };
83 :
84 : static inline const char *pci_slot_name(const struct pci_slot *slot)
85 : {
86 0 : return kobject_name(&slot->kobj);
87 : }
88 :
89 : /* File state for mmap()s on /proc/bus/pci/X/Y */
90 : enum pci_mmap_state {
91 : pci_mmap_io,
92 : pci_mmap_mem
93 : };
94 :
95 : /* For PCI devices, the region numbers are assigned this way: */
96 : enum {
97 : /* #0-5: standard PCI resources */
98 : PCI_STD_RESOURCES,
99 : PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
100 :
101 : /* #6: expansion ROM resource */
102 : PCI_ROM_RESOURCE,
103 :
104 : /* Device-specific resources */
105 : #ifdef CONFIG_PCI_IOV
106 : PCI_IOV_RESOURCES,
107 : PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
108 : #endif
109 :
110 : /* PCI-to-PCI (P2P) bridge windows */
111 : #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112 : #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113 : #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114 :
115 : /* CardBus bridge windows */
116 : #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117 : #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118 : #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119 : #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120 :
121 : /* Total number of bridge resources for P2P and CardBus */
122 : #define PCI_BRIDGE_RESOURCE_NUM 4
123 :
124 : /* Resources assigned to buses behind the bridge */
125 : PCI_BRIDGE_RESOURCES,
126 : PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 : PCI_BRIDGE_RESOURCE_NUM - 1,
128 :
129 : /* Total resources associated with a PCI device */
130 : PCI_NUM_RESOURCES,
131 :
132 : /* Preserve this for compatibility */
133 : DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
134 : };
135 :
136 : /**
137 : * enum pci_interrupt_pin - PCI INTx interrupt values
138 : * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 : * @PCI_INTERRUPT_INTA: PCI INTA pin
140 : * @PCI_INTERRUPT_INTB: PCI INTB pin
141 : * @PCI_INTERRUPT_INTC: PCI INTC pin
142 : * @PCI_INTERRUPT_INTD: PCI INTD pin
143 : *
144 : * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 : * PCI_INTERRUPT_PIN register.
146 : */
147 : enum pci_interrupt_pin {
148 : PCI_INTERRUPT_UNKNOWN,
149 : PCI_INTERRUPT_INTA,
150 : PCI_INTERRUPT_INTB,
151 : PCI_INTERRUPT_INTC,
152 : PCI_INTERRUPT_INTD,
153 : };
154 :
155 : /* The number of legacy PCI INTx interrupts */
156 : #define PCI_NUM_INTX 4
157 :
158 : /*
159 : * Reading from a device that doesn't respond typically returns ~0. A
160 : * successful read from a device may also return ~0, so you need additional
161 : * information to reliably identify errors.
162 : */
163 : #define PCI_ERROR_RESPONSE (~0ULL)
164 : #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
165 : #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
166 :
167 : /*
168 : * pci_power_t values must match the bits in the Capabilities PME_Support
169 : * and Control/Status PowerState fields in the Power Management capability.
170 : */
171 : typedef int __bitwise pci_power_t;
172 :
173 : #define PCI_D0 ((pci_power_t __force) 0)
174 : #define PCI_D1 ((pci_power_t __force) 1)
175 : #define PCI_D2 ((pci_power_t __force) 2)
176 : #define PCI_D3hot ((pci_power_t __force) 3)
177 : #define PCI_D3cold ((pci_power_t __force) 4)
178 : #define PCI_UNKNOWN ((pci_power_t __force) 5)
179 : #define PCI_POWER_ERROR ((pci_power_t __force) -1)
180 :
181 : /* Remember to update this when the list above changes! */
182 : extern const char *pci_power_names[];
183 :
184 : static inline const char *pci_power_name(pci_power_t state)
185 : {
186 0 : return pci_power_names[1 + (__force int) state];
187 : }
188 :
189 : /**
190 : * typedef pci_channel_state_t
191 : *
192 : * The pci_channel state describes connectivity between the CPU and
193 : * the PCI device. If some PCI bus between here and the PCI device
194 : * has crashed or locked up, this info is reflected here.
195 : */
196 : typedef unsigned int __bitwise pci_channel_state_t;
197 :
198 : enum {
199 : /* I/O channel is in normal state */
200 : pci_channel_io_normal = (__force pci_channel_state_t) 1,
201 :
202 : /* I/O to channel is blocked */
203 : pci_channel_io_frozen = (__force pci_channel_state_t) 2,
204 :
205 : /* PCI card is dead */
206 : pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
207 : };
208 :
209 : typedef unsigned int __bitwise pcie_reset_state_t;
210 :
211 : enum pcie_reset_state {
212 : /* Reset is NOT asserted (Use to deassert reset) */
213 : pcie_deassert_reset = (__force pcie_reset_state_t) 1,
214 :
215 : /* Use #PERST to reset PCIe device */
216 : pcie_warm_reset = (__force pcie_reset_state_t) 2,
217 :
218 : /* Use PCIe Hot Reset to reset device */
219 : pcie_hot_reset = (__force pcie_reset_state_t) 3
220 : };
221 :
222 : typedef unsigned short __bitwise pci_dev_flags_t;
223 : enum pci_dev_flags {
224 : /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
225 : PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
226 : /* Device configuration is irrevocably lost if disabled into D3 */
227 : PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
228 : /* Provide indication device is assigned by a Virtual Machine Manager */
229 : PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
230 : /* Flag for quirk use to store if quirk-specific ACS is enabled */
231 : PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
232 : /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
233 : PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
234 : /* Do not use bus resets for device */
235 : PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
236 : /* Do not use PM reset even if device advertises NoSoftRst- */
237 : PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
238 : /* Get VPD from function 0 VPD */
239 : PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
240 : /* A non-root bridge where translation occurs, stop alias search here */
241 : PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
242 : /* Do not use FLR even if device advertises PCI_AF_CAP */
243 : PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
244 : /* Don't use Relaxed Ordering for TLPs directed at this device */
245 : PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
246 : /* Device does honor MSI masking despite saying otherwise */
247 : PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
248 : };
249 :
250 : enum pci_irq_reroute_variant {
251 : INTEL_IRQ_REROUTE_VARIANT = 1,
252 : MAX_IRQ_REROUTE_VARIANTS = 3
253 : };
254 :
255 : typedef unsigned short __bitwise pci_bus_flags_t;
256 : enum pci_bus_flags {
257 : PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
258 : PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
259 : PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
260 : PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
261 : };
262 :
263 : /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
264 : enum pcie_link_width {
265 : PCIE_LNK_WIDTH_RESRV = 0x00,
266 : PCIE_LNK_X1 = 0x01,
267 : PCIE_LNK_X2 = 0x02,
268 : PCIE_LNK_X4 = 0x04,
269 : PCIE_LNK_X8 = 0x08,
270 : PCIE_LNK_X12 = 0x0c,
271 : PCIE_LNK_X16 = 0x10,
272 : PCIE_LNK_X32 = 0x20,
273 : PCIE_LNK_WIDTH_UNKNOWN = 0xff,
274 : };
275 :
276 : /* See matching string table in pci_speed_string() */
277 : enum pci_bus_speed {
278 : PCI_SPEED_33MHz = 0x00,
279 : PCI_SPEED_66MHz = 0x01,
280 : PCI_SPEED_66MHz_PCIX = 0x02,
281 : PCI_SPEED_100MHz_PCIX = 0x03,
282 : PCI_SPEED_133MHz_PCIX = 0x04,
283 : PCI_SPEED_66MHz_PCIX_ECC = 0x05,
284 : PCI_SPEED_100MHz_PCIX_ECC = 0x06,
285 : PCI_SPEED_133MHz_PCIX_ECC = 0x07,
286 : PCI_SPEED_66MHz_PCIX_266 = 0x09,
287 : PCI_SPEED_100MHz_PCIX_266 = 0x0a,
288 : PCI_SPEED_133MHz_PCIX_266 = 0x0b,
289 : AGP_UNKNOWN = 0x0c,
290 : AGP_1X = 0x0d,
291 : AGP_2X = 0x0e,
292 : AGP_4X = 0x0f,
293 : AGP_8X = 0x10,
294 : PCI_SPEED_66MHz_PCIX_533 = 0x11,
295 : PCI_SPEED_100MHz_PCIX_533 = 0x12,
296 : PCI_SPEED_133MHz_PCIX_533 = 0x13,
297 : PCIE_SPEED_2_5GT = 0x14,
298 : PCIE_SPEED_5_0GT = 0x15,
299 : PCIE_SPEED_8_0GT = 0x16,
300 : PCIE_SPEED_16_0GT = 0x17,
301 : PCIE_SPEED_32_0GT = 0x18,
302 : PCIE_SPEED_64_0GT = 0x19,
303 : PCI_SPEED_UNKNOWN = 0xff,
304 : };
305 :
306 : enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
307 : enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
308 :
309 : struct pci_vpd {
310 : struct mutex lock;
311 : unsigned int len;
312 : u8 cap;
313 : };
314 :
315 : struct irq_affinity;
316 : struct pcie_link_state;
317 : struct pci_sriov;
318 : struct pci_p2pdma;
319 : struct rcec_ea;
320 :
321 : /* The pci_dev structure describes PCI devices */
322 : struct pci_dev {
323 : struct list_head bus_list; /* Node in per-bus list */
324 : struct pci_bus *bus; /* Bus this device is on */
325 : struct pci_bus *subordinate; /* Bus this device bridges to */
326 :
327 : void *sysdata; /* Hook for sys-specific extension */
328 : struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
329 : struct pci_slot *slot; /* Physical slot this device is in */
330 :
331 : unsigned int devfn; /* Encoded device & function index */
332 : unsigned short vendor;
333 : unsigned short device;
334 : unsigned short subsystem_vendor;
335 : unsigned short subsystem_device;
336 : unsigned int class; /* 3 bytes: (base,sub,prog-if) */
337 : u8 revision; /* PCI revision, low byte of class word */
338 : u8 hdr_type; /* PCI header type (`multi' flag masked out) */
339 : #ifdef CONFIG_PCIEAER
340 : u16 aer_cap; /* AER capability offset */
341 : struct aer_stats *aer_stats; /* AER stats for this device */
342 : #endif
343 : #ifdef CONFIG_PCIEPORTBUS
344 : struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
345 : struct pci_dev *rcec; /* Associated RCEC device */
346 : #endif
347 : u32 devcap; /* PCIe Device Capabilities */
348 : u8 pcie_cap; /* PCIe capability offset */
349 : u8 msi_cap; /* MSI capability offset */
350 : u8 msix_cap; /* MSI-X capability offset */
351 : u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
352 : u8 rom_base_reg; /* Config register controlling ROM */
353 : u8 pin; /* Interrupt pin this device uses */
354 : u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
355 : unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
356 :
357 : struct pci_driver *driver; /* Driver bound to this device */
358 : u64 dma_mask; /* Mask of the bits of bus address this
359 : device implements. Normally this is
360 : 0xffffffff. You only need to change
361 : this if your device has broken DMA
362 : or supports 64-bit transfers. */
363 :
364 : struct device_dma_parameters dma_parms;
365 :
366 : pci_power_t current_state; /* Current operating state. In ACPI,
367 : this is D0-D3, D0 being fully
368 : functional, and D3 being off. */
369 : unsigned int imm_ready:1; /* Supports Immediate Readiness */
370 : u8 pm_cap; /* PM capability offset */
371 : unsigned int pme_support:5; /* Bitmask of states from which PME#
372 : can be generated */
373 : unsigned int pme_poll:1; /* Poll device's PME status bit */
374 : unsigned int d1_support:1; /* Low power state D1 is supported */
375 : unsigned int d2_support:1; /* Low power state D2 is supported */
376 : unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
377 : unsigned int no_d3cold:1; /* D3cold is forbidden */
378 : unsigned int bridge_d3:1; /* Allow D3 for bridge */
379 : unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
380 : unsigned int mmio_always_on:1; /* Disallow turning off io/mem
381 : decoding during BAR sizing */
382 : unsigned int wakeup_prepared:1;
383 : unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
384 : unsigned int ignore_hotplug:1; /* Ignore hotplug events */
385 : unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
386 : controlled exclusively by
387 : user sysfs */
388 : unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
389 : bit manually */
390 : unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
391 : unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
392 :
393 : #ifdef CONFIG_PCIEASPM
394 : struct pcie_link_state *link_state; /* ASPM link state */
395 : unsigned int ltr_path:1; /* Latency Tolerance Reporting
396 : supported from root to here */
397 : u16 l1ss; /* L1SS Capability pointer */
398 : #endif
399 : unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
400 : unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
401 :
402 : pci_channel_state_t error_state; /* Current connectivity state */
403 : struct device dev; /* Generic device interface */
404 :
405 : int cfg_size; /* Size of config space */
406 :
407 : /*
408 : * Instead of touching interrupt line and base address registers
409 : * directly, use the values stored here. They might be different!
410 : */
411 : unsigned int irq;
412 : struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
413 : struct resource driver_exclusive_resource; /* driver exclusive resource ranges */
414 :
415 : bool match_driver; /* Skip attaching driver */
416 :
417 : unsigned int transparent:1; /* Subtractive decode bridge */
418 : unsigned int io_window:1; /* Bridge has I/O window */
419 : unsigned int pref_window:1; /* Bridge has pref mem window */
420 : unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
421 : unsigned int multifunction:1; /* Multi-function device */
422 :
423 : unsigned int is_busmaster:1; /* Is busmaster */
424 : unsigned int no_msi:1; /* May not use MSI */
425 : unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
426 : unsigned int block_cfg_access:1; /* Config space access blocked */
427 : unsigned int broken_parity_status:1; /* Generates false positive parity */
428 : unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
429 : unsigned int msi_enabled:1;
430 : unsigned int msix_enabled:1;
431 : unsigned int ari_enabled:1; /* ARI forwarding */
432 : unsigned int ats_enabled:1; /* Address Translation Svc */
433 : unsigned int pasid_enabled:1; /* Process Address Space ID */
434 : unsigned int pri_enabled:1; /* Page Request Interface */
435 : unsigned int is_managed:1; /* Managed via devres */
436 : unsigned int is_msi_managed:1; /* MSI release via devres installed */
437 : unsigned int needs_freset:1; /* Requires fundamental reset */
438 : unsigned int state_saved:1;
439 : unsigned int is_physfn:1;
440 : unsigned int is_virtfn:1;
441 : unsigned int is_hotplug_bridge:1;
442 : unsigned int shpc_managed:1; /* SHPC owned by shpchp */
443 : unsigned int is_thunderbolt:1; /* Thunderbolt controller */
444 : /*
445 : * Devices marked being untrusted are the ones that can potentially
446 : * execute DMA attacks and similar. They are typically connected
447 : * through external ports such as Thunderbolt but not limited to
448 : * that. When an IOMMU is enabled they should be getting full
449 : * mappings to make sure they cannot access arbitrary memory.
450 : */
451 : unsigned int untrusted:1;
452 : /*
453 : * Info from the platform, e.g., ACPI or device tree, may mark a
454 : * device as "external-facing". An external-facing device is
455 : * itself internal but devices downstream from it are external.
456 : */
457 : unsigned int external_facing:1;
458 : unsigned int broken_intx_masking:1; /* INTx masking can't be used */
459 : unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
460 : unsigned int irq_managed:1;
461 : unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
462 : unsigned int is_probed:1; /* Device probing in progress */
463 : unsigned int link_active_reporting:1;/* Device capable of reporting link active */
464 : unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
465 : unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
466 : unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
467 : pci_dev_flags_t dev_flags;
468 : atomic_t enable_cnt; /* pci_enable_device has been called */
469 :
470 : u32 saved_config_space[16]; /* Config space saved at suspend time */
471 : struct hlist_head saved_cap_space;
472 : int rom_attr_enabled; /* Display of ROM attribute enabled? */
473 : struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
474 : struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
475 :
476 : #ifdef CONFIG_HOTPLUG_PCI_PCIE
477 : unsigned int broken_cmd_compl:1; /* No compl for some cmds */
478 : #endif
479 : #ifdef CONFIG_PCIE_PTM
480 : u16 ptm_cap; /* PTM Capability */
481 : unsigned int ptm_root:1;
482 : unsigned int ptm_enabled:1;
483 : u8 ptm_granularity;
484 : #endif
485 : #ifdef CONFIG_PCI_MSI
486 : void __iomem *msix_base;
487 : raw_spinlock_t msi_lock;
488 : #endif
489 : struct pci_vpd vpd;
490 : #ifdef CONFIG_PCIE_DPC
491 : u16 dpc_cap;
492 : unsigned int dpc_rp_extensions:1;
493 : u8 dpc_rp_log_size;
494 : #endif
495 : #ifdef CONFIG_PCI_ATS
496 : union {
497 : struct pci_sriov *sriov; /* PF: SR-IOV info */
498 : struct pci_dev *physfn; /* VF: related PF */
499 : };
500 : u16 ats_cap; /* ATS Capability offset */
501 : u8 ats_stu; /* ATS Smallest Translation Unit */
502 : #endif
503 : #ifdef CONFIG_PCI_PRI
504 : u16 pri_cap; /* PRI Capability offset */
505 : u32 pri_reqs_alloc; /* Number of PRI requests allocated */
506 : unsigned int pasid_required:1; /* PRG Response PASID Required */
507 : #endif
508 : #ifdef CONFIG_PCI_PASID
509 : u16 pasid_cap; /* PASID Capability offset */
510 : u16 pasid_features;
511 : #endif
512 : #ifdef CONFIG_PCI_P2PDMA
513 : struct pci_p2pdma __rcu *p2pdma;
514 : #endif
515 : #ifdef CONFIG_PCI_DOE
516 : struct xarray doe_mbs; /* Data Object Exchange mailboxes */
517 : #endif
518 : u16 acs_cap; /* ACS Capability offset */
519 : phys_addr_t rom; /* Physical address if not from BAR */
520 : size_t romlen; /* Length if not from BAR */
521 : /*
522 : * Driver name to force a match. Do not set directly, because core
523 : * frees it. Use driver_set_override() to set or clear it.
524 : */
525 : const char *driver_override;
526 :
527 : unsigned long priv_flags; /* Private flags for the PCI driver */
528 :
529 : /* These methods index pci_reset_fn_methods[] */
530 : u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
531 : };
532 :
533 : static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
534 : {
535 : #ifdef CONFIG_PCI_IOV
536 : if (dev->is_virtfn)
537 : dev = dev->physfn;
538 : #endif
539 : return dev;
540 : }
541 :
542 : struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
543 :
544 : #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
545 : #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
546 :
547 : static inline int pci_channel_offline(struct pci_dev *pdev)
548 : {
549 : return (pdev->error_state != pci_channel_io_normal);
550 : }
551 :
552 : /*
553 : * Currently in ACPI spec, for each PCI host bridge, PCI Segment
554 : * Group number is limited to a 16-bit value, therefore (int)-1 is
555 : * not a valid PCI domain number, and can be used as a sentinel
556 : * value indicating ->domain_nr is not set by the driver (and
557 : * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
558 : * pci_bus_find_domain_nr()).
559 : */
560 : #define PCI_DOMAIN_NR_NOT_SET (-1)
561 :
562 : struct pci_host_bridge {
563 : struct device dev;
564 : struct pci_bus *bus; /* Root bus */
565 : struct pci_ops *ops;
566 : struct pci_ops *child_ops;
567 : void *sysdata;
568 : int busnr;
569 : int domain_nr;
570 : struct list_head windows; /* resource_entry */
571 : struct list_head dma_ranges; /* dma ranges resource list */
572 : u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
573 : int (*map_irq)(const struct pci_dev *, u8, u8);
574 : void (*release_fn)(struct pci_host_bridge *);
575 : void *release_data;
576 : unsigned int ignore_reset_delay:1; /* For entire hierarchy */
577 : unsigned int no_ext_tags:1; /* No Extended Tags */
578 : unsigned int no_inc_mrrs:1; /* No Increase MRRS */
579 : unsigned int native_aer:1; /* OS may use PCIe AER */
580 : unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
581 : unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
582 : unsigned int native_pme:1; /* OS may use PCIe PME */
583 : unsigned int native_ltr:1; /* OS may use PCIe LTR */
584 : unsigned int native_dpc:1; /* OS may use PCIe DPC */
585 : unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
586 : unsigned int preserve_config:1; /* Preserve FW resource setup */
587 : unsigned int size_windows:1; /* Enable root bus sizing */
588 : unsigned int msi_domain:1; /* Bridge wants MSI domain */
589 :
590 : /* Resource alignment requirements */
591 : resource_size_t (*align_resource)(struct pci_dev *dev,
592 : const struct resource *res,
593 : resource_size_t start,
594 : resource_size_t size,
595 : resource_size_t align);
596 : unsigned long private[] ____cacheline_aligned;
597 : };
598 :
599 : #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
600 :
601 : static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
602 : {
603 : return (void *)bridge->private;
604 : }
605 :
606 : static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
607 : {
608 : return container_of(priv, struct pci_host_bridge, private);
609 : }
610 :
611 : struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
612 : struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
613 : size_t priv);
614 : void pci_free_host_bridge(struct pci_host_bridge *bridge);
615 : struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
616 :
617 : void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
618 : void (*release_fn)(struct pci_host_bridge *),
619 : void *release_data);
620 :
621 : int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
622 :
623 : /*
624 : * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
625 : * to P2P or CardBus bridge windows) go in a table. Additional ones (for
626 : * buses below host bridges or subtractive decode bridges) go in the list.
627 : * Use pci_bus_for_each_resource() to iterate through all the resources.
628 : */
629 :
630 : /*
631 : * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
632 : * and there's no way to program the bridge with the details of the window.
633 : * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
634 : * decode bit set, because they are explicit and can be programmed with _SRS.
635 : */
636 : #define PCI_SUBTRACTIVE_DECODE 0x1
637 :
638 : struct pci_bus_resource {
639 : struct list_head list;
640 : struct resource *res;
641 : unsigned int flags;
642 : };
643 :
644 : #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
645 :
646 : struct pci_bus {
647 : struct list_head node; /* Node in list of buses */
648 : struct pci_bus *parent; /* Parent bus this bridge is on */
649 : struct list_head children; /* List of child buses */
650 : struct list_head devices; /* List of devices on this bus */
651 : struct pci_dev *self; /* Bridge device as seen by parent */
652 : struct list_head slots; /* List of slots on this bus;
653 : protected by pci_slot_mutex */
654 : struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
655 : struct list_head resources; /* Address space routed to this bus */
656 : struct resource busn_res; /* Bus numbers routed to this bus */
657 :
658 : struct pci_ops *ops; /* Configuration access functions */
659 : void *sysdata; /* Hook for sys-specific extension */
660 : struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
661 :
662 : unsigned char number; /* Bus number */
663 : unsigned char primary; /* Number of primary bridge */
664 : unsigned char max_bus_speed; /* enum pci_bus_speed */
665 : unsigned char cur_bus_speed; /* enum pci_bus_speed */
666 : #ifdef CONFIG_PCI_DOMAINS_GENERIC
667 : int domain_nr;
668 : #endif
669 :
670 : char name[48];
671 :
672 : unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
673 : pci_bus_flags_t bus_flags; /* Inherited by child buses */
674 : struct device *bridge;
675 : struct device dev;
676 : struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
677 : struct bin_attribute *legacy_mem; /* Legacy mem */
678 : unsigned int is_added:1;
679 : unsigned int unsafe_warn:1; /* warned about RW1C config write */
680 : };
681 :
682 : #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
683 :
684 : static inline u16 pci_dev_id(struct pci_dev *dev)
685 : {
686 0 : return PCI_DEVID(dev->bus->number, dev->devfn);
687 : }
688 :
689 : /*
690 : * Returns true if the PCI bus is root (behind host-PCI bridge),
691 : * false otherwise
692 : *
693 : * Some code assumes that "bus->self == NULL" means that bus is a root bus.
694 : * This is incorrect because "virtual" buses added for SR-IOV (via
695 : * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
696 : */
697 : static inline bool pci_is_root_bus(struct pci_bus *pbus)
698 : {
699 : return !(pbus->parent);
700 : }
701 :
702 : /**
703 : * pci_is_bridge - check if the PCI device is a bridge
704 : * @dev: PCI device
705 : *
706 : * Return true if the PCI device is bridge whether it has subordinate
707 : * or not.
708 : */
709 : static inline bool pci_is_bridge(struct pci_dev *dev)
710 : {
711 0 : return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
712 : dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
713 : }
714 :
715 : #define for_each_pci_bridge(dev, bus) \
716 : list_for_each_entry(dev, &bus->devices, bus_list) \
717 : if (!pci_is_bridge(dev)) {} else
718 :
719 : static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
720 : {
721 0 : dev = pci_physfn(dev);
722 0 : if (pci_is_root_bus(dev->bus))
723 : return NULL;
724 :
725 0 : return dev->bus->self;
726 : }
727 :
728 : #ifdef CONFIG_PCI_MSI
729 : static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
730 : {
731 : return pci_dev->msi_enabled || pci_dev->msix_enabled;
732 : }
733 : #else
734 : static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
735 : #endif
736 :
737 : /* Error values that may be returned by PCI functions */
738 : #define PCIBIOS_SUCCESSFUL 0x00
739 : #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
740 : #define PCIBIOS_BAD_VENDOR_ID 0x83
741 : #define PCIBIOS_DEVICE_NOT_FOUND 0x86
742 : #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
743 : #define PCIBIOS_SET_FAILED 0x88
744 : #define PCIBIOS_BUFFER_TOO_SMALL 0x89
745 :
746 : /* Translate above to generic errno for passing back through non-PCI code */
747 : static inline int pcibios_err_to_errno(int err)
748 : {
749 0 : if (err <= PCIBIOS_SUCCESSFUL)
750 : return err; /* Assume already errno */
751 :
752 0 : switch (err) {
753 : case PCIBIOS_FUNC_NOT_SUPPORTED:
754 : return -ENOENT;
755 : case PCIBIOS_BAD_VENDOR_ID:
756 : return -ENOTTY;
757 : case PCIBIOS_DEVICE_NOT_FOUND:
758 : return -ENODEV;
759 : case PCIBIOS_BAD_REGISTER_NUMBER:
760 : return -EFAULT;
761 : case PCIBIOS_SET_FAILED:
762 : return -EIO;
763 : case PCIBIOS_BUFFER_TOO_SMALL:
764 : return -ENOSPC;
765 : }
766 :
767 : return -ERANGE;
768 : }
769 :
770 : /* Low-level architecture-dependent routines */
771 :
772 : struct pci_ops {
773 : int (*add_bus)(struct pci_bus *bus);
774 : void (*remove_bus)(struct pci_bus *bus);
775 : void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
776 : int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
777 : int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
778 : };
779 :
780 : /*
781 : * ACPI needs to be able to access PCI config space before we've done a
782 : * PCI bus scan and created pci_bus structures.
783 : */
784 : int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
785 : int reg, int len, u32 *val);
786 : int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
787 : int reg, int len, u32 val);
788 :
789 : #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
790 : typedef u64 pci_bus_addr_t;
791 : #else
792 : typedef u32 pci_bus_addr_t;
793 : #endif
794 :
795 : struct pci_bus_region {
796 : pci_bus_addr_t start;
797 : pci_bus_addr_t end;
798 : };
799 :
800 : struct pci_dynids {
801 : spinlock_t lock; /* Protects list, index */
802 : struct list_head list; /* For IDs added at runtime */
803 : };
804 :
805 :
806 : /*
807 : * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
808 : * a set of callbacks in struct pci_error_handlers, that device driver
809 : * will be notified of PCI bus errors, and will be driven to recovery
810 : * when an error occurs.
811 : */
812 :
813 : typedef unsigned int __bitwise pci_ers_result_t;
814 :
815 : enum pci_ers_result {
816 : /* No result/none/not supported in device driver */
817 : PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
818 :
819 : /* Device driver can recover without slot reset */
820 : PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
821 :
822 : /* Device driver wants slot to be reset */
823 : PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
824 :
825 : /* Device has completely failed, is unrecoverable */
826 : PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
827 :
828 : /* Device driver is fully recovered and operational */
829 : PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
830 :
831 : /* No AER capabilities registered for the driver */
832 : PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
833 : };
834 :
835 : /* PCI bus error event callbacks */
836 : struct pci_error_handlers {
837 : /* PCI bus error detected on this device */
838 : pci_ers_result_t (*error_detected)(struct pci_dev *dev,
839 : pci_channel_state_t error);
840 :
841 : /* MMIO has been re-enabled, but not DMA */
842 : pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
843 :
844 : /* PCI slot has been reset */
845 : pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
846 :
847 : /* PCI function reset prepare or completed */
848 : void (*reset_prepare)(struct pci_dev *dev);
849 : void (*reset_done)(struct pci_dev *dev);
850 :
851 : /* Device driver may resume normal operations */
852 : void (*resume)(struct pci_dev *dev);
853 :
854 : /* Allow device driver to record more details of a correctable error */
855 : void (*cor_error_detected)(struct pci_dev *dev);
856 : };
857 :
858 :
859 : struct module;
860 :
861 : /**
862 : * struct pci_driver - PCI driver structure
863 : * @node: List of driver structures.
864 : * @name: Driver name.
865 : * @id_table: Pointer to table of device IDs the driver is
866 : * interested in. Most drivers should export this
867 : * table using MODULE_DEVICE_TABLE(pci,...).
868 : * @probe: This probing function gets called (during execution
869 : * of pci_register_driver() for already existing
870 : * devices or later if a new device gets inserted) for
871 : * all PCI devices which match the ID table and are not
872 : * "owned" by the other drivers yet. This function gets
873 : * passed a "struct pci_dev \*" for each device whose
874 : * entry in the ID table matches the device. The probe
875 : * function returns zero when the driver chooses to
876 : * take "ownership" of the device or an error code
877 : * (negative number) otherwise.
878 : * The probe function always gets called from process
879 : * context, so it can sleep.
880 : * @remove: The remove() function gets called whenever a device
881 : * being handled by this driver is removed (either during
882 : * deregistration of the driver or when it's manually
883 : * pulled out of a hot-pluggable slot).
884 : * The remove function always gets called from process
885 : * context, so it can sleep.
886 : * @suspend: Put device into low power state.
887 : * @resume: Wake device from low power state.
888 : * (Please see Documentation/power/pci.rst for descriptions
889 : * of PCI Power Management and the related functions.)
890 : * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
891 : * Intended to stop any idling DMA operations.
892 : * Useful for enabling wake-on-lan (NIC) or changing
893 : * the power state of a device before reboot.
894 : * e.g. drivers/net/e100.c.
895 : * @sriov_configure: Optional driver callback to allow configuration of
896 : * number of VFs to enable via sysfs "sriov_numvfs" file.
897 : * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
898 : * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
899 : * This will change MSI-X Table Size in the VF Message Control
900 : * registers.
901 : * @sriov_get_vf_total_msix: PF driver callback to get the total number of
902 : * MSI-X vectors available for distribution to the VFs.
903 : * @err_handler: See Documentation/PCI/pci-error-recovery.rst
904 : * @groups: Sysfs attribute groups.
905 : * @dev_groups: Attributes attached to the device that will be
906 : * created once it is bound to the driver.
907 : * @driver: Driver model structure.
908 : * @dynids: List of dynamically added device IDs.
909 : * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
910 : * For most device drivers, no need to care about this flag
911 : * as long as all DMAs are handled through the kernel DMA API.
912 : * For some special ones, for example VFIO drivers, they know
913 : * how to manage the DMA themselves and set this flag so that
914 : * the IOMMU layer will allow them to setup and manage their
915 : * own I/O address space.
916 : */
917 : struct pci_driver {
918 : struct list_head node;
919 : const char *name;
920 : const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
921 : int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
922 : void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
923 : int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
924 : int (*resume)(struct pci_dev *dev); /* Device woken up */
925 : void (*shutdown)(struct pci_dev *dev);
926 : int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
927 : int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
928 : u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
929 : const struct pci_error_handlers *err_handler;
930 : const struct attribute_group **groups;
931 : const struct attribute_group **dev_groups;
932 : struct device_driver driver;
933 : struct pci_dynids dynids;
934 : bool driver_managed_dma;
935 : };
936 :
937 : static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
938 : {
939 0 : return drv ? container_of(drv, struct pci_driver, driver) : NULL;
940 : }
941 :
942 : /**
943 : * PCI_DEVICE - macro used to describe a specific PCI device
944 : * @vend: the 16 bit PCI Vendor ID
945 : * @dev: the 16 bit PCI Device ID
946 : *
947 : * This macro is used to create a struct pci_device_id that matches a
948 : * specific device. The subvendor and subdevice fields will be set to
949 : * PCI_ANY_ID.
950 : */
951 : #define PCI_DEVICE(vend,dev) \
952 : .vendor = (vend), .device = (dev), \
953 : .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
954 :
955 : /**
956 : * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
957 : * override_only flags.
958 : * @vend: the 16 bit PCI Vendor ID
959 : * @dev: the 16 bit PCI Device ID
960 : * @driver_override: the 32 bit PCI Device override_only
961 : *
962 : * This macro is used to create a struct pci_device_id that matches only a
963 : * driver_override device. The subvendor and subdevice fields will be set to
964 : * PCI_ANY_ID.
965 : */
966 : #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
967 : .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
968 : .subdevice = PCI_ANY_ID, .override_only = (driver_override)
969 :
970 : /**
971 : * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
972 : * "driver_override" PCI device.
973 : * @vend: the 16 bit PCI Vendor ID
974 : * @dev: the 16 bit PCI Device ID
975 : *
976 : * This macro is used to create a struct pci_device_id that matches a
977 : * specific device. The subvendor and subdevice fields will be set to
978 : * PCI_ANY_ID and the driver_override will be set to
979 : * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
980 : */
981 : #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
982 : PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
983 :
984 : /**
985 : * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
986 : * @vend: the 16 bit PCI Vendor ID
987 : * @dev: the 16 bit PCI Device ID
988 : * @subvend: the 16 bit PCI Subvendor ID
989 : * @subdev: the 16 bit PCI Subdevice ID
990 : *
991 : * This macro is used to create a struct pci_device_id that matches a
992 : * specific device with subsystem information.
993 : */
994 : #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
995 : .vendor = (vend), .device = (dev), \
996 : .subvendor = (subvend), .subdevice = (subdev)
997 :
998 : /**
999 : * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1000 : * @dev_class: the class, subclass, prog-if triple for this device
1001 : * @dev_class_mask: the class mask for this device
1002 : *
1003 : * This macro is used to create a struct pci_device_id that matches a
1004 : * specific PCI class. The vendor, device, subvendor, and subdevice
1005 : * fields will be set to PCI_ANY_ID.
1006 : */
1007 : #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
1008 : .class = (dev_class), .class_mask = (dev_class_mask), \
1009 : .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1010 : .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1011 :
1012 : /**
1013 : * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1014 : * @vend: the vendor name
1015 : * @dev: the 16 bit PCI Device ID
1016 : *
1017 : * This macro is used to create a struct pci_device_id that matches a
1018 : * specific PCI device. The subvendor, and subdevice fields will be set
1019 : * to PCI_ANY_ID. The macro allows the next field to follow as the device
1020 : * private data.
1021 : */
1022 : #define PCI_VDEVICE(vend, dev) \
1023 : .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1024 : .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1025 :
1026 : /**
1027 : * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1028 : * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1029 : * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1030 : * @data: the driver data to be filled
1031 : *
1032 : * This macro is used to create a struct pci_device_id that matches a
1033 : * specific PCI device. The subvendor, and subdevice fields will be set
1034 : * to PCI_ANY_ID.
1035 : */
1036 : #define PCI_DEVICE_DATA(vend, dev, data) \
1037 : .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1038 : .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1039 : .driver_data = (kernel_ulong_t)(data)
1040 :
1041 : enum {
1042 : PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1043 : PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1044 : PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1045 : PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1046 : PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1047 : PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1048 : PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1049 : };
1050 :
1051 : #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1052 : #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1053 : #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1054 : #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1055 :
1056 : /* These external functions are only available when PCI support is enabled */
1057 : #ifdef CONFIG_PCI
1058 :
1059 : extern unsigned int pci_flags;
1060 :
1061 : static inline void pci_set_flags(int flags) { pci_flags = flags; }
1062 0 : static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1063 : static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1064 0 : static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1065 :
1066 : void pcie_bus_configure_settings(struct pci_bus *bus);
1067 :
1068 : enum pcie_bus_config_types {
1069 : PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1070 : PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1071 : PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1072 : PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1073 : PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1074 : };
1075 :
1076 : extern enum pcie_bus_config_types pcie_bus_config;
1077 :
1078 : extern struct bus_type pci_bus_type;
1079 :
1080 : /* Do NOT directly access these two variables, unless you are arch-specific PCI
1081 : * code, or PCI core code. */
1082 : extern struct list_head pci_root_buses; /* List of all known PCI buses */
1083 : /* Some device drivers need know if PCI is initiated */
1084 : int no_pci_devices(void);
1085 :
1086 : void pcibios_resource_survey_bus(struct pci_bus *bus);
1087 : void pcibios_bus_add_device(struct pci_dev *pdev);
1088 : void pcibios_add_bus(struct pci_bus *bus);
1089 : void pcibios_remove_bus(struct pci_bus *bus);
1090 : void pcibios_fixup_bus(struct pci_bus *);
1091 : int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1092 : /* Architecture-specific versions may override this (weak) */
1093 : char *pcibios_setup(char *str);
1094 :
1095 : /* Used only when drivers/pci/setup.c is used */
1096 : resource_size_t pcibios_align_resource(void *, const struct resource *,
1097 : resource_size_t,
1098 : resource_size_t);
1099 :
1100 : /* Weak but can be overridden by arch */
1101 : void pci_fixup_cardbus(struct pci_bus *);
1102 :
1103 : /* Generic PCI functions used internally */
1104 :
1105 : void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1106 : struct resource *res);
1107 : void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1108 : struct pci_bus_region *region);
1109 : void pcibios_scan_specific_bus(int busn);
1110 : struct pci_bus *pci_find_bus(int domain, int busnr);
1111 : void pci_bus_add_devices(const struct pci_bus *bus);
1112 : struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1113 : struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1114 : struct pci_ops *ops, void *sysdata,
1115 : struct list_head *resources);
1116 : int pci_host_probe(struct pci_host_bridge *bridge);
1117 : int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1118 : int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1119 : void pci_bus_release_busn_res(struct pci_bus *b);
1120 : struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1121 : struct pci_ops *ops, void *sysdata,
1122 : struct list_head *resources);
1123 : int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1124 : struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1125 : int busnr);
1126 : struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1127 : const char *name,
1128 : struct hotplug_slot *hotplug);
1129 : void pci_destroy_slot(struct pci_slot *slot);
1130 : #ifdef CONFIG_SYSFS
1131 : void pci_dev_assign_slot(struct pci_dev *dev);
1132 : #else
1133 : static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1134 : #endif
1135 : int pci_scan_slot(struct pci_bus *bus, int devfn);
1136 : struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1137 : void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1138 : unsigned int pci_scan_child_bus(struct pci_bus *bus);
1139 : void pci_bus_add_device(struct pci_dev *dev);
1140 : void pci_read_bridge_bases(struct pci_bus *child);
1141 : struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1142 : struct resource *res);
1143 : u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1144 : int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1145 : u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1146 : struct pci_dev *pci_dev_get(struct pci_dev *dev);
1147 : void pci_dev_put(struct pci_dev *dev);
1148 : void pci_remove_bus(struct pci_bus *b);
1149 : void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1150 : void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1151 : void pci_stop_root_bus(struct pci_bus *bus);
1152 : void pci_remove_root_bus(struct pci_bus *bus);
1153 : void pci_setup_cardbus(struct pci_bus *bus);
1154 : void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1155 : void pci_sort_breadthfirst(void);
1156 : #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1157 : #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1158 :
1159 : /* Generic PCI functions exported to card drivers */
1160 :
1161 : u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1162 : u8 pci_find_capability(struct pci_dev *dev, int cap);
1163 : u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1164 : u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1165 : u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1166 : u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1167 : u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1168 : struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1169 : u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1170 : u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1171 :
1172 : u64 pci_get_dsn(struct pci_dev *dev);
1173 :
1174 : struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1175 : struct pci_dev *from);
1176 : struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1177 : unsigned int ss_vendor, unsigned int ss_device,
1178 : struct pci_dev *from);
1179 : struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1180 : struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1181 : unsigned int devfn);
1182 : struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1183 : int pci_dev_present(const struct pci_device_id *ids);
1184 :
1185 : int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1186 : int where, u8 *val);
1187 : int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1188 : int where, u16 *val);
1189 : int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1190 : int where, u32 *val);
1191 : int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1192 : int where, u8 val);
1193 : int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1194 : int where, u16 val);
1195 : int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1196 : int where, u32 val);
1197 :
1198 : int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1199 : int where, int size, u32 *val);
1200 : int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1201 : int where, int size, u32 val);
1202 : int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1203 : int where, int size, u32 *val);
1204 : int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1205 : int where, int size, u32 val);
1206 :
1207 : struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1208 :
1209 : int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1210 : int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1211 : int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1212 : int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1213 : int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1214 : int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1215 :
1216 : int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1217 : int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1218 : int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1219 : int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1220 : int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1221 : u16 clear, u16 set);
1222 : int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1223 : u32 clear, u32 set);
1224 :
1225 : static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1226 : u16 set)
1227 : {
1228 0 : return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1229 : }
1230 :
1231 : static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1232 : u32 set)
1233 : {
1234 0 : return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1235 : }
1236 :
1237 : static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1238 : u16 clear)
1239 : {
1240 0 : return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1241 : }
1242 :
1243 : static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1244 : u32 clear)
1245 : {
1246 : return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1247 : }
1248 :
1249 : /* User-space driven config access */
1250 : int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1251 : int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1252 : int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1253 : int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1254 : int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1255 : int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1256 :
1257 : int __must_check pci_enable_device(struct pci_dev *dev);
1258 : int __must_check pci_enable_device_io(struct pci_dev *dev);
1259 : int __must_check pci_enable_device_mem(struct pci_dev *dev);
1260 : int __must_check pci_reenable_device(struct pci_dev *);
1261 : int __must_check pcim_enable_device(struct pci_dev *pdev);
1262 : void pcim_pin_device(struct pci_dev *pdev);
1263 :
1264 : static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1265 : {
1266 : /*
1267 : * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1268 : * writable and no quirk has marked the feature broken.
1269 : */
1270 : return !pdev->broken_intx_masking;
1271 : }
1272 :
1273 : static inline int pci_is_enabled(struct pci_dev *pdev)
1274 : {
1275 0 : return (atomic_read(&pdev->enable_cnt) > 0);
1276 : }
1277 :
1278 : static inline int pci_is_managed(struct pci_dev *pdev)
1279 : {
1280 0 : return pdev->is_managed;
1281 : }
1282 :
1283 : void pci_disable_device(struct pci_dev *dev);
1284 :
1285 : extern unsigned int pcibios_max_latency;
1286 : void pci_set_master(struct pci_dev *dev);
1287 : void pci_clear_master(struct pci_dev *dev);
1288 :
1289 : int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1290 : int pci_set_cacheline_size(struct pci_dev *dev);
1291 : int __must_check pci_set_mwi(struct pci_dev *dev);
1292 : int __must_check pcim_set_mwi(struct pci_dev *dev);
1293 : int pci_try_set_mwi(struct pci_dev *dev);
1294 : void pci_clear_mwi(struct pci_dev *dev);
1295 : void pci_disable_parity(struct pci_dev *dev);
1296 : void pci_intx(struct pci_dev *dev, int enable);
1297 : bool pci_check_and_mask_intx(struct pci_dev *dev);
1298 : bool pci_check_and_unmask_intx(struct pci_dev *dev);
1299 : int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1300 : int pci_wait_for_pending_transaction(struct pci_dev *dev);
1301 : int pcix_get_max_mmrbc(struct pci_dev *dev);
1302 : int pcix_get_mmrbc(struct pci_dev *dev);
1303 : int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1304 : int pcie_get_readrq(struct pci_dev *dev);
1305 : int pcie_set_readrq(struct pci_dev *dev, int rq);
1306 : int pcie_get_mps(struct pci_dev *dev);
1307 : int pcie_set_mps(struct pci_dev *dev, int mps);
1308 : u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1309 : enum pci_bus_speed *speed,
1310 : enum pcie_link_width *width);
1311 : void pcie_print_link_status(struct pci_dev *dev);
1312 : int pcie_reset_flr(struct pci_dev *dev, bool probe);
1313 : int pcie_flr(struct pci_dev *dev);
1314 : int __pci_reset_function_locked(struct pci_dev *dev);
1315 : int pci_reset_function(struct pci_dev *dev);
1316 : int pci_reset_function_locked(struct pci_dev *dev);
1317 : int pci_try_reset_function(struct pci_dev *dev);
1318 : int pci_probe_reset_slot(struct pci_slot *slot);
1319 : int pci_probe_reset_bus(struct pci_bus *bus);
1320 : int pci_reset_bus(struct pci_dev *dev);
1321 : void pci_reset_secondary_bus(struct pci_dev *dev);
1322 : void pcibios_reset_secondary_bus(struct pci_dev *dev);
1323 : void pci_update_resource(struct pci_dev *dev, int resno);
1324 : int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1325 : int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1326 : void pci_release_resource(struct pci_dev *dev, int resno);
1327 0 : static inline int pci_rebar_bytes_to_size(u64 bytes)
1328 : {
1329 0 : bytes = roundup_pow_of_two(bytes);
1330 :
1331 : /* Return BAR size as defined in the resizable BAR specification */
1332 0 : return max(ilog2(bytes), 20) - 20;
1333 : }
1334 :
1335 : u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1336 : int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1337 : int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1338 : bool pci_device_is_present(struct pci_dev *pdev);
1339 : void pci_ignore_hotplug(struct pci_dev *dev);
1340 : struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1341 : int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1342 :
1343 : int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1344 : irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1345 : const char *fmt, ...);
1346 : void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1347 :
1348 : /* ROM control related routines */
1349 : int pci_enable_rom(struct pci_dev *pdev);
1350 : void pci_disable_rom(struct pci_dev *pdev);
1351 : void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1352 : void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1353 :
1354 : /* Power management related routines */
1355 : int pci_save_state(struct pci_dev *dev);
1356 : void pci_restore_state(struct pci_dev *dev);
1357 : struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1358 : int pci_load_saved_state(struct pci_dev *dev,
1359 : struct pci_saved_state *state);
1360 : int pci_load_and_free_saved_state(struct pci_dev *dev,
1361 : struct pci_saved_state **state);
1362 : int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1363 : int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1364 : pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1365 : bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1366 : void pci_pme_active(struct pci_dev *dev, bool enable);
1367 : int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1368 : int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1369 : int pci_prepare_to_sleep(struct pci_dev *dev);
1370 : int pci_back_from_sleep(struct pci_dev *dev);
1371 : bool pci_dev_run_wake(struct pci_dev *dev);
1372 : void pci_d3cold_enable(struct pci_dev *dev);
1373 : void pci_d3cold_disable(struct pci_dev *dev);
1374 : bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1375 : void pci_resume_bus(struct pci_bus *bus);
1376 : void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1377 :
1378 : /* For use by arch with custom probe code */
1379 : void set_pcie_port_type(struct pci_dev *pdev);
1380 : void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1381 :
1382 : /* Functions for PCI Hotplug drivers to use */
1383 : unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1384 : unsigned int pci_rescan_bus(struct pci_bus *bus);
1385 : void pci_lock_rescan_remove(void);
1386 : void pci_unlock_rescan_remove(void);
1387 :
1388 : /* Vital Product Data routines */
1389 : ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1390 : ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1391 : ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1392 : ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1393 :
1394 : /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1395 : resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1396 : void pci_bus_assign_resources(const struct pci_bus *bus);
1397 : void pci_bus_claim_resources(struct pci_bus *bus);
1398 : void pci_bus_size_bridges(struct pci_bus *bus);
1399 : int pci_claim_resource(struct pci_dev *, int);
1400 : int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1401 : void pci_assign_unassigned_resources(void);
1402 : void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1403 : void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1404 : void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1405 : int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1406 : void pdev_enable_device(struct pci_dev *);
1407 : int pci_enable_resources(struct pci_dev *, int mask);
1408 : void pci_assign_irq(struct pci_dev *dev);
1409 : struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1410 : #define HAVE_PCI_REQ_REGIONS 2
1411 : int __must_check pci_request_regions(struct pci_dev *, const char *);
1412 : int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1413 : void pci_release_regions(struct pci_dev *);
1414 : int __must_check pci_request_region(struct pci_dev *, int, const char *);
1415 : void pci_release_region(struct pci_dev *, int);
1416 : int pci_request_selected_regions(struct pci_dev *, int, const char *);
1417 : int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1418 : void pci_release_selected_regions(struct pci_dev *, int);
1419 :
1420 : static inline __must_check struct resource *
1421 : pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset,
1422 : unsigned int len, const char *name)
1423 : {
1424 : return __request_region(&pdev->driver_exclusive_resource, offset, len,
1425 : name, IORESOURCE_EXCLUSIVE);
1426 : }
1427 :
1428 : static inline void pci_release_config_region(struct pci_dev *pdev,
1429 : unsigned int offset,
1430 : unsigned int len)
1431 : {
1432 : __release_region(&pdev->driver_exclusive_resource, offset, len);
1433 : }
1434 :
1435 : /* drivers/pci/bus.c */
1436 : void pci_add_resource(struct list_head *resources, struct resource *res);
1437 : void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1438 : resource_size_t offset);
1439 : void pci_free_resource_list(struct list_head *resources);
1440 : void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1441 : unsigned int flags);
1442 : struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1443 : void pci_bus_remove_resources(struct pci_bus *bus);
1444 : void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res);
1445 : int devm_request_pci_bus_resources(struct device *dev,
1446 : struct list_head *resources);
1447 :
1448 : /* Temporary until new and working PCI SBR API in place */
1449 : int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1450 :
1451 : #define __pci_bus_for_each_res0(bus, res, ...) \
1452 : for (unsigned int __b = 0; \
1453 : (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1454 : __b++)
1455 :
1456 : #define __pci_bus_for_each_res1(bus, res, __b) \
1457 : for (__b = 0; \
1458 : (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1459 : __b++)
1460 :
1461 : /**
1462 : * pci_bus_for_each_resource - iterate over PCI bus resources
1463 : * @bus: the PCI bus
1464 : * @res: pointer to the current resource
1465 : * @...: optional index of the current resource
1466 : *
1467 : * Iterate over PCI bus resources. The first part is to go over PCI bus
1468 : * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries.
1469 : * After that continue with the separate list of the additional resources,
1470 : * if not empty. That's why the Logical OR is being used.
1471 : *
1472 : * Possible usage:
1473 : *
1474 : * struct pci_bus *bus = ...;
1475 : * struct resource *res;
1476 : * unsigned int i;
1477 : *
1478 : * // With optional index
1479 : * pci_bus_for_each_resource(bus, res, i)
1480 : * pr_info("PCI bus resource[%u]: %pR\n", i, res);
1481 : *
1482 : * // Without index
1483 : * pci_bus_for_each_resource(bus, res)
1484 : * _do_something_(res);
1485 : */
1486 : #define pci_bus_for_each_resource(bus, res, ...) \
1487 : CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
1488 : (bus, res, __VA_ARGS__)
1489 :
1490 : int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1491 : struct resource *res, resource_size_t size,
1492 : resource_size_t align, resource_size_t min,
1493 : unsigned long type_mask,
1494 : resource_size_t (*alignf)(void *,
1495 : const struct resource *,
1496 : resource_size_t,
1497 : resource_size_t),
1498 : void *alignf_data);
1499 :
1500 :
1501 : int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1502 : resource_size_t size);
1503 : unsigned long pci_address_to_pio(phys_addr_t addr);
1504 : phys_addr_t pci_pio_to_address(unsigned long pio);
1505 : int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1506 : int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1507 : phys_addr_t phys_addr);
1508 : void pci_unmap_iospace(struct resource *res);
1509 : void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1510 : resource_size_t offset,
1511 : resource_size_t size);
1512 : void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1513 : struct resource *res);
1514 :
1515 : static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1516 : {
1517 : struct pci_bus_region region;
1518 :
1519 : pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1520 : return region.start;
1521 : }
1522 :
1523 : /* Proper probing supporting hot-pluggable devices */
1524 : int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1525 : const char *mod_name);
1526 :
1527 : /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1528 : #define pci_register_driver(driver) \
1529 : __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1530 :
1531 : void pci_unregister_driver(struct pci_driver *dev);
1532 :
1533 : /**
1534 : * module_pci_driver() - Helper macro for registering a PCI driver
1535 : * @__pci_driver: pci_driver struct
1536 : *
1537 : * Helper macro for PCI drivers which do not do anything special in module
1538 : * init/exit. This eliminates a lot of boilerplate. Each module may only
1539 : * use this macro once, and calling it replaces module_init() and module_exit()
1540 : */
1541 : #define module_pci_driver(__pci_driver) \
1542 : module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1543 :
1544 : /**
1545 : * builtin_pci_driver() - Helper macro for registering a PCI driver
1546 : * @__pci_driver: pci_driver struct
1547 : *
1548 : * Helper macro for PCI drivers which do not do anything special in their
1549 : * init code. This eliminates a lot of boilerplate. Each driver may only
1550 : * use this macro once, and calling it replaces device_initcall(...)
1551 : */
1552 : #define builtin_pci_driver(__pci_driver) \
1553 : builtin_driver(__pci_driver, pci_register_driver)
1554 :
1555 : struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1556 : int pci_add_dynid(struct pci_driver *drv,
1557 : unsigned int vendor, unsigned int device,
1558 : unsigned int subvendor, unsigned int subdevice,
1559 : unsigned int class, unsigned int class_mask,
1560 : unsigned long driver_data);
1561 : const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1562 : struct pci_dev *dev);
1563 : int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1564 : int pass);
1565 :
1566 : void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1567 : void *userdata);
1568 : int pci_cfg_space_size(struct pci_dev *dev);
1569 : unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1570 : void pci_setup_bridge(struct pci_bus *bus);
1571 : resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1572 : unsigned long type);
1573 :
1574 : #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1575 : #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1576 :
1577 : int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1578 : unsigned int command_bits, u32 flags);
1579 :
1580 : /*
1581 : * Virtual interrupts allow for more interrupts to be allocated
1582 : * than the device has interrupts for. These are not programmed
1583 : * into the device's MSI-X table and must be handled by some
1584 : * other driver means.
1585 : */
1586 : #define PCI_IRQ_VIRTUAL (1 << 4)
1587 :
1588 : #define PCI_IRQ_ALL_TYPES \
1589 : (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1590 :
1591 : #include <linux/dmapool.h>
1592 :
1593 : struct msix_entry {
1594 : u32 vector; /* Kernel uses to write allocated vector */
1595 : u16 entry; /* Driver uses to specify entry, OS writes */
1596 : };
1597 :
1598 : #ifdef CONFIG_PCI_MSI
1599 : int pci_msi_vec_count(struct pci_dev *dev);
1600 : void pci_disable_msi(struct pci_dev *dev);
1601 : int pci_msix_vec_count(struct pci_dev *dev);
1602 : void pci_disable_msix(struct pci_dev *dev);
1603 : void pci_restore_msi_state(struct pci_dev *dev);
1604 : int pci_msi_enabled(void);
1605 : int pci_enable_msi(struct pci_dev *dev);
1606 : int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1607 : int minvec, int maxvec);
1608 : static inline int pci_enable_msix_exact(struct pci_dev *dev,
1609 : struct msix_entry *entries, int nvec)
1610 : {
1611 : int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1612 : if (rc < 0)
1613 : return rc;
1614 : return 0;
1615 : }
1616 : int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1617 : unsigned int max_vecs, unsigned int flags);
1618 : int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1619 : unsigned int max_vecs, unsigned int flags,
1620 : struct irq_affinity *affd);
1621 :
1622 : bool pci_msix_can_alloc_dyn(struct pci_dev *dev);
1623 : struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1624 : const struct irq_affinity_desc *affdesc);
1625 : void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
1626 :
1627 : void pci_free_irq_vectors(struct pci_dev *dev);
1628 : int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1629 : const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1630 :
1631 : #else
1632 : static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1633 : static inline void pci_disable_msi(struct pci_dev *dev) { }
1634 : static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1635 : static inline void pci_disable_msix(struct pci_dev *dev) { }
1636 : static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1637 : static inline int pci_msi_enabled(void) { return 0; }
1638 : static inline int pci_enable_msi(struct pci_dev *dev)
1639 : { return -ENOSYS; }
1640 : static inline int pci_enable_msix_range(struct pci_dev *dev,
1641 : struct msix_entry *entries, int minvec, int maxvec)
1642 : { return -ENOSYS; }
1643 : static inline int pci_enable_msix_exact(struct pci_dev *dev,
1644 : struct msix_entry *entries, int nvec)
1645 : { return -ENOSYS; }
1646 :
1647 : static inline int
1648 : pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1649 : unsigned int max_vecs, unsigned int flags,
1650 : struct irq_affinity *aff_desc)
1651 : {
1652 : if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1653 : return 1;
1654 : return -ENOSPC;
1655 : }
1656 : static inline int
1657 : pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1658 : unsigned int max_vecs, unsigned int flags)
1659 : {
1660 : return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,
1661 : flags, NULL);
1662 : }
1663 :
1664 : static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev)
1665 : { return false; }
1666 : static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1667 : const struct irq_affinity_desc *affdesc)
1668 : {
1669 : struct msi_map map = { .index = -ENOSYS, };
1670 :
1671 : return map;
1672 : }
1673 :
1674 : static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map)
1675 : {
1676 : }
1677 :
1678 : static inline void pci_free_irq_vectors(struct pci_dev *dev)
1679 : {
1680 : }
1681 :
1682 : static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1683 : {
1684 : if (WARN_ON_ONCE(nr > 0))
1685 : return -EINVAL;
1686 : return dev->irq;
1687 : }
1688 : static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1689 : int vec)
1690 : {
1691 : return cpu_possible_mask;
1692 : }
1693 : #endif
1694 :
1695 : /**
1696 : * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1697 : * @d: the INTx IRQ domain
1698 : * @node: the DT node for the device whose interrupt we're translating
1699 : * @intspec: the interrupt specifier data from the DT
1700 : * @intsize: the number of entries in @intspec
1701 : * @out_hwirq: pointer at which to write the hwirq number
1702 : * @out_type: pointer at which to write the interrupt type
1703 : *
1704 : * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1705 : * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1706 : * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1707 : * INTx value to obtain the hwirq number.
1708 : *
1709 : * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1710 : */
1711 : static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1712 : struct device_node *node,
1713 : const u32 *intspec,
1714 : unsigned int intsize,
1715 : unsigned long *out_hwirq,
1716 : unsigned int *out_type)
1717 : {
1718 : const u32 intx = intspec[0];
1719 :
1720 : if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1721 : return -EINVAL;
1722 :
1723 : *out_hwirq = intx - PCI_INTERRUPT_INTA;
1724 : return 0;
1725 : }
1726 :
1727 : #ifdef CONFIG_PCIEPORTBUS
1728 : extern bool pcie_ports_disabled;
1729 : extern bool pcie_ports_native;
1730 : #else
1731 : #define pcie_ports_disabled true
1732 : #define pcie_ports_native false
1733 : #endif
1734 :
1735 : #define PCIE_LINK_STATE_L0S BIT(0)
1736 : #define PCIE_LINK_STATE_L1 BIT(1)
1737 : #define PCIE_LINK_STATE_CLKPM BIT(2)
1738 : #define PCIE_LINK_STATE_L1_1 BIT(3)
1739 : #define PCIE_LINK_STATE_L1_2 BIT(4)
1740 : #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1741 : #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1742 : #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |\
1743 : PCIE_LINK_STATE_CLKPM | PCIE_LINK_STATE_L1_1 |\
1744 : PCIE_LINK_STATE_L1_2 | PCIE_LINK_STATE_L1_1_PCIPM |\
1745 : PCIE_LINK_STATE_L1_2_PCIPM)
1746 :
1747 : #ifdef CONFIG_PCIEASPM
1748 : int pci_disable_link_state(struct pci_dev *pdev, int state);
1749 : int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1750 : int pci_enable_link_state(struct pci_dev *pdev, int state);
1751 : void pcie_no_aspm(void);
1752 : bool pcie_aspm_support_enabled(void);
1753 : bool pcie_aspm_enabled(struct pci_dev *pdev);
1754 : #else
1755 : static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1756 : { return 0; }
1757 : static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1758 : { return 0; }
1759 : static inline int pci_enable_link_state(struct pci_dev *pdev, int state)
1760 : { return 0; }
1761 : static inline void pcie_no_aspm(void) { }
1762 : static inline bool pcie_aspm_support_enabled(void) { return false; }
1763 : static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1764 : #endif
1765 :
1766 : #ifdef CONFIG_PCIEAER
1767 : bool pci_aer_available(void);
1768 : #else
1769 : static inline bool pci_aer_available(void) { return false; }
1770 : #endif
1771 :
1772 : bool pci_ats_disabled(void);
1773 :
1774 : #ifdef CONFIG_PCIE_PTM
1775 : int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1776 : void pci_disable_ptm(struct pci_dev *dev);
1777 : bool pcie_ptm_enabled(struct pci_dev *dev);
1778 : #else
1779 : static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1780 : { return -EINVAL; }
1781 : static inline void pci_disable_ptm(struct pci_dev *dev) { }
1782 : static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1783 : { return false; }
1784 : #endif
1785 :
1786 : void pci_cfg_access_lock(struct pci_dev *dev);
1787 : bool pci_cfg_access_trylock(struct pci_dev *dev);
1788 : void pci_cfg_access_unlock(struct pci_dev *dev);
1789 :
1790 : void pci_dev_lock(struct pci_dev *dev);
1791 : int pci_dev_trylock(struct pci_dev *dev);
1792 : void pci_dev_unlock(struct pci_dev *dev);
1793 :
1794 : /*
1795 : * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1796 : * a PCI domain is defined to be a set of PCI buses which share
1797 : * configuration space.
1798 : */
1799 : #ifdef CONFIG_PCI_DOMAINS
1800 : extern int pci_domains_supported;
1801 : #else
1802 : enum { pci_domains_supported = 0 };
1803 : static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1804 : static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1805 : #endif /* CONFIG_PCI_DOMAINS */
1806 :
1807 : /*
1808 : * Generic implementation for PCI domain support. If your
1809 : * architecture does not need custom management of PCI
1810 : * domains then this implementation will be used
1811 : */
1812 : #ifdef CONFIG_PCI_DOMAINS_GENERIC
1813 : static inline int pci_domain_nr(struct pci_bus *bus)
1814 : {
1815 : return bus->domain_nr;
1816 : }
1817 : #ifdef CONFIG_ACPI
1818 : int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1819 : #else
1820 : static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1821 : { return 0; }
1822 : #endif
1823 : int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1824 : void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent);
1825 : #endif
1826 :
1827 : /* Some architectures require additional setup to direct VGA traffic */
1828 : typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1829 : unsigned int command_bits, u32 flags);
1830 : void pci_register_set_vga_state(arch_set_vga_state_t func);
1831 :
1832 : static inline int
1833 : pci_request_io_regions(struct pci_dev *pdev, const char *name)
1834 : {
1835 : return pci_request_selected_regions(pdev,
1836 : pci_select_bars(pdev, IORESOURCE_IO), name);
1837 : }
1838 :
1839 : static inline void
1840 : pci_release_io_regions(struct pci_dev *pdev)
1841 : {
1842 : return pci_release_selected_regions(pdev,
1843 : pci_select_bars(pdev, IORESOURCE_IO));
1844 : }
1845 :
1846 : static inline int
1847 : pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1848 : {
1849 : return pci_request_selected_regions(pdev,
1850 : pci_select_bars(pdev, IORESOURCE_MEM), name);
1851 : }
1852 :
1853 : static inline void
1854 : pci_release_mem_regions(struct pci_dev *pdev)
1855 : {
1856 : return pci_release_selected_regions(pdev,
1857 : pci_select_bars(pdev, IORESOURCE_MEM));
1858 : }
1859 :
1860 : #else /* CONFIG_PCI is not enabled */
1861 :
1862 : static inline void pci_set_flags(int flags) { }
1863 : static inline void pci_add_flags(int flags) { }
1864 : static inline void pci_clear_flags(int flags) { }
1865 : static inline int pci_has_flag(int flag) { return 0; }
1866 :
1867 : /*
1868 : * If the system does not have PCI, clearly these return errors. Define
1869 : * these as simple inline functions to avoid hair in drivers.
1870 : */
1871 : #define _PCI_NOP(o, s, t) \
1872 : static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1873 : int where, t val) \
1874 : { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1875 :
1876 : #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1877 : _PCI_NOP(o, word, u16 x) \
1878 : _PCI_NOP(o, dword, u32 x)
1879 : _PCI_NOP_ALL(read, *)
1880 : _PCI_NOP_ALL(write,)
1881 :
1882 : static inline struct pci_dev *pci_get_device(unsigned int vendor,
1883 : unsigned int device,
1884 : struct pci_dev *from)
1885 : { return NULL; }
1886 :
1887 : static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1888 : unsigned int device,
1889 : unsigned int ss_vendor,
1890 : unsigned int ss_device,
1891 : struct pci_dev *from)
1892 : { return NULL; }
1893 :
1894 : static inline struct pci_dev *pci_get_class(unsigned int class,
1895 : struct pci_dev *from)
1896 : { return NULL; }
1897 :
1898 :
1899 : static inline int pci_dev_present(const struct pci_device_id *ids)
1900 : { return 0; }
1901 :
1902 : #define no_pci_devices() (1)
1903 : #define pci_dev_put(dev) do { } while (0)
1904 :
1905 : static inline void pci_set_master(struct pci_dev *dev) { }
1906 : static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1907 : static inline void pci_disable_device(struct pci_dev *dev) { }
1908 : static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1909 : static inline int pci_assign_resource(struct pci_dev *dev, int i)
1910 : { return -EBUSY; }
1911 : static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1912 : struct module *owner,
1913 : const char *mod_name)
1914 : { return 0; }
1915 : static inline int pci_register_driver(struct pci_driver *drv)
1916 : { return 0; }
1917 : static inline void pci_unregister_driver(struct pci_driver *drv) { }
1918 : static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1919 : { return 0; }
1920 : static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1921 : int cap)
1922 : { return 0; }
1923 : static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1924 : { return 0; }
1925 :
1926 : static inline u64 pci_get_dsn(struct pci_dev *dev)
1927 : { return 0; }
1928 :
1929 : /* Power management related routines */
1930 : static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1931 : static inline void pci_restore_state(struct pci_dev *dev) { }
1932 : static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1933 : { return 0; }
1934 : static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1935 : { return 0; }
1936 : static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1937 : pm_message_t state)
1938 : { return PCI_D0; }
1939 : static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1940 : int enable)
1941 : { return 0; }
1942 :
1943 : static inline struct resource *pci_find_resource(struct pci_dev *dev,
1944 : struct resource *res)
1945 : { return NULL; }
1946 : static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1947 : { return -EIO; }
1948 : static inline void pci_release_regions(struct pci_dev *dev) { }
1949 :
1950 : static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1951 : phys_addr_t addr, resource_size_t size)
1952 : { return -EINVAL; }
1953 :
1954 : static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1955 :
1956 : static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1957 : { return NULL; }
1958 : static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1959 : unsigned int devfn)
1960 : { return NULL; }
1961 : static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1962 : unsigned int bus, unsigned int devfn)
1963 : { return NULL; }
1964 :
1965 : static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1966 : static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1967 :
1968 : #define dev_is_pci(d) (false)
1969 : #define dev_is_pf(d) (false)
1970 : static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1971 : { return false; }
1972 : static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1973 : struct device_node *node,
1974 : const u32 *intspec,
1975 : unsigned int intsize,
1976 : unsigned long *out_hwirq,
1977 : unsigned int *out_type)
1978 : { return -EINVAL; }
1979 :
1980 : static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1981 : struct pci_dev *dev)
1982 : { return NULL; }
1983 : static inline bool pci_ats_disabled(void) { return true; }
1984 :
1985 : static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1986 : {
1987 : return -EINVAL;
1988 : }
1989 :
1990 : static inline int
1991 : pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1992 : unsigned int max_vecs, unsigned int flags,
1993 : struct irq_affinity *aff_desc)
1994 : {
1995 : return -ENOSPC;
1996 : }
1997 : static inline int
1998 : pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1999 : unsigned int max_vecs, unsigned int flags)
2000 : {
2001 : return -ENOSPC;
2002 : }
2003 : #endif /* CONFIG_PCI */
2004 :
2005 : /* Include architecture-dependent settings and functions */
2006 :
2007 : #include <asm/pci.h>
2008 :
2009 : /*
2010 : * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
2011 : * is expected to be an offset within that region.
2012 : *
2013 : */
2014 : int pci_mmap_resource_range(struct pci_dev *dev, int bar,
2015 : struct vm_area_struct *vma,
2016 : enum pci_mmap_state mmap_state, int write_combine);
2017 :
2018 : #ifndef arch_can_pci_mmap_wc
2019 : #define arch_can_pci_mmap_wc() 0
2020 : #endif
2021 :
2022 : #ifndef arch_can_pci_mmap_io
2023 : #define arch_can_pci_mmap_io() 0
2024 : #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
2025 : #else
2026 : int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
2027 : #endif
2028 :
2029 : #ifndef pci_root_bus_fwnode
2030 : #define pci_root_bus_fwnode(bus) NULL
2031 : #endif
2032 :
2033 : /*
2034 : * These helpers provide future and backwards compatibility
2035 : * for accessing popular PCI BAR info
2036 : */
2037 : #define pci_resource_n(dev, bar) (&(dev)->resource[(bar)])
2038 : #define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start)
2039 : #define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end)
2040 : #define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags)
2041 : #define pci_resource_len(dev,bar) \
2042 : (pci_resource_end((dev), (bar)) ? \
2043 : resource_size(pci_resource_n((dev), (bar))) : 0)
2044 :
2045 : #define __pci_dev_for_each_res0(dev, res, ...) \
2046 : for (unsigned int __b = 0; \
2047 : res = pci_resource_n(dev, __b), __b < PCI_NUM_RESOURCES; \
2048 : __b++)
2049 :
2050 : #define __pci_dev_for_each_res1(dev, res, __b) \
2051 : for (__b = 0; \
2052 : res = pci_resource_n(dev, __b), __b < PCI_NUM_RESOURCES; \
2053 : __b++)
2054 :
2055 : #define pci_dev_for_each_resource(dev, res, ...) \
2056 : CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
2057 : (dev, res, __VA_ARGS__)
2058 :
2059 : /*
2060 : * Similar to the helpers above, these manipulate per-pci_dev
2061 : * driver-specific data. They are really just a wrapper around
2062 : * the generic device structure functions of these calls.
2063 : */
2064 : static inline void *pci_get_drvdata(struct pci_dev *pdev)
2065 : {
2066 : return dev_get_drvdata(&pdev->dev);
2067 : }
2068 :
2069 : static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
2070 : {
2071 : dev_set_drvdata(&pdev->dev, data);
2072 : }
2073 :
2074 : static inline const char *pci_name(const struct pci_dev *pdev)
2075 : {
2076 0 : return dev_name(&pdev->dev);
2077 : }
2078 :
2079 : void pci_resource_to_user(const struct pci_dev *dev, int bar,
2080 : const struct resource *rsrc,
2081 : resource_size_t *start, resource_size_t *end);
2082 :
2083 : /*
2084 : * The world is not perfect and supplies us with broken PCI devices.
2085 : * For at least a part of these bugs we need a work-around, so both
2086 : * generic (drivers/pci/quirks.c) and per-architecture code can define
2087 : * fixup hooks to be called for particular buggy devices.
2088 : */
2089 :
2090 : struct pci_fixup {
2091 : u16 vendor; /* Or PCI_ANY_ID */
2092 : u16 device; /* Or PCI_ANY_ID */
2093 : u32 class; /* Or PCI_ANY_ID */
2094 : unsigned int class_shift; /* should be 0, 8, 16 */
2095 : #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2096 : int hook_offset;
2097 : #else
2098 : void (*hook)(struct pci_dev *dev);
2099 : #endif
2100 : };
2101 :
2102 : enum pci_fixup_pass {
2103 : pci_fixup_early, /* Before probing BARs */
2104 : pci_fixup_header, /* After reading configuration header */
2105 : pci_fixup_final, /* Final phase of device fixups */
2106 : pci_fixup_enable, /* pci_enable_device() time */
2107 : pci_fixup_resume, /* pci_device_resume() */
2108 : pci_fixup_suspend, /* pci_device_suspend() */
2109 : pci_fixup_resume_early, /* pci_device_resume_early() */
2110 : pci_fixup_suspend_late, /* pci_device_suspend_late() */
2111 : };
2112 :
2113 : #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2114 : #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2115 : class_shift, hook) \
2116 : __ADDRESSABLE(hook) \
2117 : asm(".section " #sec ", \"a\" \n" \
2118 : ".balign 16 \n" \
2119 : ".short " #vendor ", " #device " \n" \
2120 : ".long " #class ", " #class_shift " \n" \
2121 : ".long " #hook " - . \n" \
2122 : ".previous \n");
2123 :
2124 : /*
2125 : * Clang's LTO may rename static functions in C, but has no way to
2126 : * handle such renamings when referenced from inline asm. To work
2127 : * around this, create global C stubs for these cases.
2128 : */
2129 : #ifdef CONFIG_LTO_CLANG
2130 : #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2131 : class_shift, hook, stub) \
2132 : void stub(struct pci_dev *dev); \
2133 : void stub(struct pci_dev *dev) \
2134 : { \
2135 : hook(dev); \
2136 : } \
2137 : ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2138 : class_shift, stub)
2139 : #else
2140 : #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2141 : class_shift, hook, stub) \
2142 : ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2143 : class_shift, hook)
2144 : #endif
2145 :
2146 : #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2147 : class_shift, hook) \
2148 : __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2149 : class_shift, hook, __UNIQUE_ID(hook))
2150 : #else
2151 : /* Anonymous variables would be nice... */
2152 : #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2153 : class_shift, hook) \
2154 : static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2155 : __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2156 : = { vendor, device, class, class_shift, hook };
2157 : #endif
2158 :
2159 : #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2160 : class_shift, hook) \
2161 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2162 : hook, vendor, device, class, class_shift, hook)
2163 : #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2164 : class_shift, hook) \
2165 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2166 : hook, vendor, device, class, class_shift, hook)
2167 : #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2168 : class_shift, hook) \
2169 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2170 : hook, vendor, device, class, class_shift, hook)
2171 : #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2172 : class_shift, hook) \
2173 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2174 : hook, vendor, device, class, class_shift, hook)
2175 : #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2176 : class_shift, hook) \
2177 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2178 : resume##hook, vendor, device, class, class_shift, hook)
2179 : #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2180 : class_shift, hook) \
2181 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2182 : resume_early##hook, vendor, device, class, class_shift, hook)
2183 : #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2184 : class_shift, hook) \
2185 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2186 : suspend##hook, vendor, device, class, class_shift, hook)
2187 : #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2188 : class_shift, hook) \
2189 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2190 : suspend_late##hook, vendor, device, class, class_shift, hook)
2191 :
2192 : #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2193 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2194 : hook, vendor, device, PCI_ANY_ID, 0, hook)
2195 : #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2196 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2197 : hook, vendor, device, PCI_ANY_ID, 0, hook)
2198 : #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2199 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2200 : hook, vendor, device, PCI_ANY_ID, 0, hook)
2201 : #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2202 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2203 : hook, vendor, device, PCI_ANY_ID, 0, hook)
2204 : #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2205 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2206 : resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2207 : #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2208 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2209 : resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2210 : #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2211 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2212 : suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2213 : #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2214 : DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2215 : suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2216 :
2217 : #ifdef CONFIG_PCI_QUIRKS
2218 : void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2219 : #else
2220 : static inline void pci_fixup_device(enum pci_fixup_pass pass,
2221 : struct pci_dev *dev) { }
2222 : #endif
2223 :
2224 : void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2225 : void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2226 : void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2227 : int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2228 : int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2229 : const char *name);
2230 : void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2231 :
2232 : extern int pci_pci_problems;
2233 : #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2234 : #define PCIPCI_TRITON 2
2235 : #define PCIPCI_NATOMA 4
2236 : #define PCIPCI_VIAETBF 8
2237 : #define PCIPCI_VSFX 16
2238 : #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2239 : #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2240 :
2241 : extern unsigned long pci_cardbus_io_size;
2242 : extern unsigned long pci_cardbus_mem_size;
2243 : extern u8 pci_dfl_cache_line_size;
2244 : extern u8 pci_cache_line_size;
2245 :
2246 : /* Architecture-specific versions may override these (weak) */
2247 : void pcibios_disable_device(struct pci_dev *dev);
2248 : void pcibios_set_master(struct pci_dev *dev);
2249 : int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2250 : enum pcie_reset_state state);
2251 : int pcibios_device_add(struct pci_dev *dev);
2252 : void pcibios_release_device(struct pci_dev *dev);
2253 : #ifdef CONFIG_PCI
2254 : void pcibios_penalize_isa_irq(int irq, int active);
2255 : #else
2256 : static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2257 : #endif
2258 : int pcibios_alloc_irq(struct pci_dev *dev);
2259 : void pcibios_free_irq(struct pci_dev *dev);
2260 : resource_size_t pcibios_default_alignment(void);
2261 :
2262 : #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2263 : void __init pci_mmcfg_early_init(void);
2264 : void __init pci_mmcfg_late_init(void);
2265 : #else
2266 : static inline void pci_mmcfg_early_init(void) { }
2267 : static inline void pci_mmcfg_late_init(void) { }
2268 : #endif
2269 :
2270 : int pci_ext_cfg_avail(void);
2271 :
2272 : void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2273 : void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2274 :
2275 : #ifdef CONFIG_PCI_IOV
2276 : int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2277 : int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2278 : int pci_iov_vf_id(struct pci_dev *dev);
2279 : void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
2280 : int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2281 : void pci_disable_sriov(struct pci_dev *dev);
2282 :
2283 : int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2284 : int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2285 : void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2286 : int pci_num_vf(struct pci_dev *dev);
2287 : int pci_vfs_assigned(struct pci_dev *dev);
2288 : int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2289 : int pci_sriov_get_totalvfs(struct pci_dev *dev);
2290 : int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2291 : resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2292 : void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2293 :
2294 : /* Arch may override these (weak) */
2295 : int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2296 : int pcibios_sriov_disable(struct pci_dev *pdev);
2297 : resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2298 : #else
2299 : static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2300 : {
2301 : return -ENOSYS;
2302 : }
2303 : static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2304 : {
2305 : return -ENOSYS;
2306 : }
2307 :
2308 : static inline int pci_iov_vf_id(struct pci_dev *dev)
2309 : {
2310 : return -ENOSYS;
2311 : }
2312 :
2313 : static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2314 : struct pci_driver *pf_driver)
2315 : {
2316 : return ERR_PTR(-EINVAL);
2317 : }
2318 :
2319 : static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2320 : { return -ENODEV; }
2321 :
2322 : static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2323 : struct pci_dev *virtfn, int id)
2324 : {
2325 : return -ENODEV;
2326 : }
2327 : static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2328 : {
2329 : return -ENOSYS;
2330 : }
2331 : static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2332 : int id) { }
2333 : static inline void pci_disable_sriov(struct pci_dev *dev) { }
2334 : static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2335 : static inline int pci_vfs_assigned(struct pci_dev *dev)
2336 : { return 0; }
2337 : static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2338 : { return 0; }
2339 : static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2340 : { return 0; }
2341 : #define pci_sriov_configure_simple NULL
2342 : static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2343 : { return 0; }
2344 : static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2345 : #endif
2346 :
2347 : #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2348 : void pci_hp_create_module_link(struct pci_slot *pci_slot);
2349 : void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2350 : #endif
2351 :
2352 : /**
2353 : * pci_pcie_cap - get the saved PCIe capability offset
2354 : * @dev: PCI device
2355 : *
2356 : * PCIe capability offset is calculated at PCI device initialization
2357 : * time and saved in the data structure. This function returns saved
2358 : * PCIe capability offset. Using this instead of pci_find_capability()
2359 : * reduces unnecessary search in the PCI configuration space. If you
2360 : * need to calculate PCIe capability offset from raw device for some
2361 : * reasons, please use pci_find_capability() instead.
2362 : */
2363 : static inline int pci_pcie_cap(struct pci_dev *dev)
2364 : {
2365 0 : return dev->pcie_cap;
2366 : }
2367 :
2368 : /**
2369 : * pci_is_pcie - check if the PCI device is PCI Express capable
2370 : * @dev: PCI device
2371 : *
2372 : * Returns: true if the PCI device is PCI Express capable, false otherwise.
2373 : */
2374 : static inline bool pci_is_pcie(struct pci_dev *dev)
2375 : {
2376 0 : return pci_pcie_cap(dev);
2377 : }
2378 :
2379 : /**
2380 : * pcie_caps_reg - get the PCIe Capabilities Register
2381 : * @dev: PCI device
2382 : */
2383 : static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2384 : {
2385 : return dev->pcie_flags_reg;
2386 : }
2387 :
2388 : /**
2389 : * pci_pcie_type - get the PCIe device/port type
2390 : * @dev: PCI device
2391 : */
2392 : static inline int pci_pcie_type(const struct pci_dev *dev)
2393 : {
2394 0 : return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2395 : }
2396 :
2397 : /**
2398 : * pcie_find_root_port - Get the PCIe root port device
2399 : * @dev: PCI device
2400 : *
2401 : * Traverse up the parent chain and return the PCIe Root Port PCI Device
2402 : * for a given PCI/PCIe Device.
2403 : */
2404 : static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2405 : {
2406 0 : while (dev) {
2407 0 : if (pci_is_pcie(dev) &&
2408 0 : pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2409 : return dev;
2410 0 : dev = pci_upstream_bridge(dev);
2411 : }
2412 :
2413 : return NULL;
2414 : }
2415 :
2416 : void pci_request_acs(void);
2417 : bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2418 : bool pci_acs_path_enabled(struct pci_dev *start,
2419 : struct pci_dev *end, u16 acs_flags);
2420 : int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2421 :
2422 : #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2423 : #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2424 :
2425 : /* Large Resource Data Type Tag Item Names */
2426 : #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2427 : #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2428 : #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2429 :
2430 : #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2431 : #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2432 : #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2433 :
2434 : #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2435 : #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2436 : #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2437 : #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2438 : #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2439 :
2440 : /**
2441 : * pci_vpd_alloc - Allocate buffer and read VPD into it
2442 : * @dev: PCI device
2443 : * @size: pointer to field where VPD length is returned
2444 : *
2445 : * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2446 : */
2447 : void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2448 :
2449 : /**
2450 : * pci_vpd_find_id_string - Locate id string in VPD
2451 : * @buf: Pointer to buffered VPD data
2452 : * @len: The length of the buffer area in which to search
2453 : * @size: Pointer to field where length of id string is returned
2454 : *
2455 : * Returns the index of the id string or -ENOENT if not found.
2456 : */
2457 : int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2458 :
2459 : /**
2460 : * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2461 : * @buf: Pointer to buffered VPD data
2462 : * @len: The length of the buffer area in which to search
2463 : * @kw: The keyword to search for
2464 : * @size: Pointer to field where length of found keyword data is returned
2465 : *
2466 : * Returns the index of the information field keyword data or -ENOENT if
2467 : * not found.
2468 : */
2469 : int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2470 : const char *kw, unsigned int *size);
2471 :
2472 : /**
2473 : * pci_vpd_check_csum - Check VPD checksum
2474 : * @buf: Pointer to buffered VPD data
2475 : * @len: VPD size
2476 : *
2477 : * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2478 : */
2479 : int pci_vpd_check_csum(const void *buf, unsigned int len);
2480 :
2481 : /* PCI <-> OF binding helpers */
2482 : #ifdef CONFIG_OF
2483 : struct device_node;
2484 : struct irq_domain;
2485 : struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2486 : bool pci_host_of_has_msi_map(struct device *dev);
2487 :
2488 : /* Arch may override this (weak) */
2489 : struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2490 :
2491 : #else /* CONFIG_OF */
2492 : static inline struct irq_domain *
2493 : pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2494 : static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2495 : #endif /* CONFIG_OF */
2496 :
2497 : static inline struct device_node *
2498 : pci_device_to_OF_node(const struct pci_dev *pdev)
2499 : {
2500 : return pdev ? pdev->dev.of_node : NULL;
2501 : }
2502 :
2503 : static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2504 : {
2505 : return bus ? bus->dev.of_node : NULL;
2506 : }
2507 :
2508 : #ifdef CONFIG_ACPI
2509 : struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2510 :
2511 : void
2512 : pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2513 : bool pci_pr3_present(struct pci_dev *pdev);
2514 : #else
2515 : static inline struct irq_domain *
2516 : pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2517 : static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2518 : #endif
2519 :
2520 : #ifdef CONFIG_EEH
2521 : static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2522 : {
2523 : return pdev->dev.archdata.edev;
2524 : }
2525 : #endif
2526 :
2527 : void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2528 : bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2529 : int pci_for_each_dma_alias(struct pci_dev *pdev,
2530 : int (*fn)(struct pci_dev *pdev,
2531 : u16 alias, void *data), void *data);
2532 :
2533 : /* Helper functions for operation of device flag */
2534 : static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2535 : {
2536 : pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2537 : }
2538 : static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2539 : {
2540 : pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2541 : }
2542 : static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2543 : {
2544 : return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2545 : }
2546 :
2547 : /**
2548 : * pci_ari_enabled - query ARI forwarding status
2549 : * @bus: the PCI bus
2550 : *
2551 : * Returns true if ARI forwarding is enabled.
2552 : */
2553 : static inline bool pci_ari_enabled(struct pci_bus *bus)
2554 : {
2555 0 : return bus->self && bus->self->ari_enabled;
2556 : }
2557 :
2558 : /**
2559 : * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2560 : * @pdev: PCI device to check
2561 : *
2562 : * Walk upwards from @pdev and check for each encountered bridge if it's part
2563 : * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2564 : * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2565 : */
2566 : static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2567 : {
2568 : struct pci_dev *parent = pdev;
2569 :
2570 : if (pdev->is_thunderbolt)
2571 : return true;
2572 :
2573 : while ((parent = pci_upstream_bridge(parent)))
2574 : if (parent->is_thunderbolt)
2575 : return true;
2576 :
2577 : return false;
2578 : }
2579 :
2580 : #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2581 : void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2582 : #endif
2583 :
2584 : struct msi_domain_template;
2585 :
2586 : bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
2587 : unsigned int hwsize, void *data);
2588 : struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie,
2589 : const struct irq_affinity_desc *affdesc);
2590 : void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map);
2591 :
2592 : #include <linux/dma-mapping.h>
2593 :
2594 : #define pci_printk(level, pdev, fmt, arg...) \
2595 : dev_printk(level, &(pdev)->dev, fmt, ##arg)
2596 :
2597 : #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2598 : #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2599 : #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2600 : #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2601 : #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2602 : #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg)
2603 : #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2604 : #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2605 : #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2606 :
2607 : #define pci_notice_ratelimited(pdev, fmt, arg...) \
2608 : dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2609 :
2610 : #define pci_info_ratelimited(pdev, fmt, arg...) \
2611 : dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2612 :
2613 : #define pci_WARN(pdev, condition, fmt, arg...) \
2614 : WARN(condition, "%s %s: " fmt, \
2615 : dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2616 :
2617 : #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2618 : WARN_ONCE(condition, "%s %s: " fmt, \
2619 : dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2620 :
2621 : #endif /* LINUX_PCI_H */
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