Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0
2 : /*
3 : * PCI Bus Services, see include/linux/pci.h for further explanation.
4 : *
5 : * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 : * David Mosberger-Tang
7 : *
8 : * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
9 : */
10 :
11 : #include <linux/acpi.h>
12 : #include <linux/kernel.h>
13 : #include <linux/delay.h>
14 : #include <linux/dmi.h>
15 : #include <linux/init.h>
16 : #include <linux/msi.h>
17 : #include <linux/of.h>
18 : #include <linux/pci.h>
19 : #include <linux/pm.h>
20 : #include <linux/slab.h>
21 : #include <linux/module.h>
22 : #include <linux/spinlock.h>
23 : #include <linux/string.h>
24 : #include <linux/log2.h>
25 : #include <linux/logic_pio.h>
26 : #include <linux/pm_wakeup.h>
27 : #include <linux/interrupt.h>
28 : #include <linux/device.h>
29 : #include <linux/pm_runtime.h>
30 : #include <linux/pci_hotplug.h>
31 : #include <linux/vmalloc.h>
32 : #include <asm/dma.h>
33 : #include <linux/aer.h>
34 : #include <linux/bitfield.h>
35 : #include "pci.h"
36 :
37 : DEFINE_MUTEX(pci_slot_mutex);
38 :
39 : const char *pci_power_names[] = {
40 : "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
41 : };
42 : EXPORT_SYMBOL_GPL(pci_power_names);
43 :
44 : #ifdef CONFIG_X86_32
45 : int isa_dma_bridge_buggy;
46 : EXPORT_SYMBOL(isa_dma_bridge_buggy);
47 : #endif
48 :
49 : int pci_pci_problems;
50 : EXPORT_SYMBOL(pci_pci_problems);
51 :
52 : unsigned int pci_pm_d3hot_delay;
53 :
54 : static void pci_pme_list_scan(struct work_struct *work);
55 :
56 : static LIST_HEAD(pci_pme_list);
57 : static DEFINE_MUTEX(pci_pme_list_mutex);
58 : static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
59 :
60 : struct pci_pme_device {
61 : struct list_head list;
62 : struct pci_dev *dev;
63 : };
64 :
65 : #define PME_TIMEOUT 1000 /* How long between PME checks */
66 :
67 0 : static void pci_dev_d3_sleep(struct pci_dev *dev)
68 : {
69 0 : unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
70 : unsigned int upper;
71 :
72 0 : if (delay_ms) {
73 : /* Use a 20% upper bound, 1ms minimum */
74 0 : upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U);
75 0 : usleep_range(delay_ms * USEC_PER_MSEC,
76 0 : (delay_ms + upper) * USEC_PER_MSEC);
77 : }
78 0 : }
79 :
80 0 : bool pci_reset_supported(struct pci_dev *dev)
81 : {
82 0 : return dev->reset_methods[0] != 0;
83 : }
84 :
85 : #ifdef CONFIG_PCI_DOMAINS
86 : int pci_domains_supported = 1;
87 : #endif
88 :
89 : #define DEFAULT_CARDBUS_IO_SIZE (256)
90 : #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
91 : /* pci=cbmemsize=nnM,cbiosize=nn can override this */
92 : unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
93 : unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
94 :
95 : #define DEFAULT_HOTPLUG_IO_SIZE (256)
96 : #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
97 : #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
98 : /* hpiosize=nn can override this */
99 : unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
100 : /*
101 : * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
102 : * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
103 : * pci=hpmemsize=nnM overrides both
104 : */
105 : unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
106 : unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
107 :
108 : #define DEFAULT_HOTPLUG_BUS_SIZE 1
109 : unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
110 :
111 :
112 : /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
113 : #ifdef CONFIG_PCIE_BUS_TUNE_OFF
114 : enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
115 : #elif defined CONFIG_PCIE_BUS_SAFE
116 : enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
117 : #elif defined CONFIG_PCIE_BUS_PERFORMANCE
118 : enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
119 : #elif defined CONFIG_PCIE_BUS_PEER2PEER
120 : enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
121 : #else
122 : enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
123 : #endif
124 :
125 : /*
126 : * The default CLS is used if arch didn't set CLS explicitly and not
127 : * all pci devices agree on the same value. Arch can override either
128 : * the dfl or actual value as it sees fit. Don't forget this is
129 : * measured in 32-bit words, not bytes.
130 : */
131 : u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
132 : u8 pci_cache_line_size;
133 :
134 : /*
135 : * If we set up a device for bus mastering, we need to check the latency
136 : * timer as certain BIOSes forget to set it properly.
137 : */
138 : unsigned int pcibios_max_latency = 255;
139 :
140 : /* If set, the PCIe ARI capability will not be used. */
141 : static bool pcie_ari_disabled;
142 :
143 : /* If set, the PCIe ATS capability will not be used. */
144 : static bool pcie_ats_disabled;
145 :
146 : /* If set, the PCI config space of each device is printed during boot. */
147 : bool pci_early_dump;
148 :
149 0 : bool pci_ats_disabled(void)
150 : {
151 0 : return pcie_ats_disabled;
152 : }
153 : EXPORT_SYMBOL_GPL(pci_ats_disabled);
154 :
155 : /* Disable bridge_d3 for all PCIe ports */
156 : static bool pci_bridge_d3_disable;
157 : /* Force bridge_d3 for all PCIe ports */
158 : static bool pci_bridge_d3_force;
159 :
160 0 : static int __init pcie_port_pm_setup(char *str)
161 : {
162 0 : if (!strcmp(str, "off"))
163 0 : pci_bridge_d3_disable = true;
164 0 : else if (!strcmp(str, "force"))
165 0 : pci_bridge_d3_force = true;
166 0 : return 1;
167 : }
168 : __setup("pcie_port_pm=", pcie_port_pm_setup);
169 :
170 : /**
171 : * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
172 : * @bus: pointer to PCI bus structure to search
173 : *
174 : * Given a PCI bus, returns the highest PCI bus number present in the set
175 : * including the given PCI bus and its list of child PCI buses.
176 : */
177 0 : unsigned char pci_bus_max_busnr(struct pci_bus *bus)
178 : {
179 : struct pci_bus *tmp;
180 : unsigned char max, n;
181 :
182 0 : max = bus->busn_res.end;
183 0 : list_for_each_entry(tmp, &bus->children, node) {
184 0 : n = pci_bus_max_busnr(tmp);
185 0 : if (n > max)
186 0 : max = n;
187 : }
188 0 : return max;
189 : }
190 : EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
191 :
192 : /**
193 : * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
194 : * @pdev: the PCI device
195 : *
196 : * Returns error bits set in PCI_STATUS and clears them.
197 : */
198 0 : int pci_status_get_and_clear_errors(struct pci_dev *pdev)
199 : {
200 : u16 status;
201 : int ret;
202 :
203 0 : ret = pci_read_config_word(pdev, PCI_STATUS, &status);
204 0 : if (ret != PCIBIOS_SUCCESSFUL)
205 : return -EIO;
206 :
207 0 : status &= PCI_STATUS_ERROR_BITS;
208 0 : if (status)
209 0 : pci_write_config_word(pdev, PCI_STATUS, status);
210 :
211 0 : return status;
212 : }
213 : EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
214 :
215 : #ifdef CONFIG_HAS_IOMEM
216 0 : static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar,
217 : bool write_combine)
218 : {
219 0 : struct resource *res = &pdev->resource[bar];
220 0 : resource_size_t start = res->start;
221 0 : resource_size_t size = resource_size(res);
222 :
223 : /*
224 : * Make sure the BAR is actually a memory resource, not an IO resource
225 : */
226 0 : if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
227 0 : pci_err(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
228 0 : return NULL;
229 : }
230 :
231 0 : if (write_combine)
232 0 : return ioremap_wc(start, size);
233 :
234 0 : return ioremap(start, size);
235 : }
236 :
237 0 : void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
238 : {
239 0 : return __pci_ioremap_resource(pdev, bar, false);
240 : }
241 : EXPORT_SYMBOL_GPL(pci_ioremap_bar);
242 :
243 0 : void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
244 : {
245 0 : return __pci_ioremap_resource(pdev, bar, true);
246 : }
247 : EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
248 : #endif
249 :
250 : /**
251 : * pci_dev_str_match_path - test if a path string matches a device
252 : * @dev: the PCI device to test
253 : * @path: string to match the device against
254 : * @endptr: pointer to the string after the match
255 : *
256 : * Test if a string (typically from a kernel parameter) formatted as a
257 : * path of device/function addresses matches a PCI device. The string must
258 : * be of the form:
259 : *
260 : * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
261 : *
262 : * A path for a device can be obtained using 'lspci -t'. Using a path
263 : * is more robust against bus renumbering than using only a single bus,
264 : * device and function address.
265 : *
266 : * Returns 1 if the string matches the device, 0 if it does not and
267 : * a negative error code if it fails to parse the string.
268 : */
269 0 : static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
270 : const char **endptr)
271 : {
272 : int ret;
273 : unsigned int seg, bus, slot, func;
274 : char *wpath, *p;
275 : char end;
276 :
277 0 : *endptr = strchrnul(path, ';');
278 :
279 0 : wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
280 0 : if (!wpath)
281 : return -ENOMEM;
282 :
283 : while (1) {
284 0 : p = strrchr(wpath, '/');
285 0 : if (!p)
286 : break;
287 0 : ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
288 0 : if (ret != 2) {
289 : ret = -EINVAL;
290 : goto free_and_exit;
291 : }
292 :
293 0 : if (dev->devfn != PCI_DEVFN(slot, func)) {
294 : ret = 0;
295 : goto free_and_exit;
296 : }
297 :
298 : /*
299 : * Note: we don't need to get a reference to the upstream
300 : * bridge because we hold a reference to the top level
301 : * device which should hold a reference to the bridge,
302 : * and so on.
303 : */
304 0 : dev = pci_upstream_bridge(dev);
305 0 : if (!dev) {
306 : ret = 0;
307 : goto free_and_exit;
308 : }
309 :
310 0 : *p = 0;
311 : }
312 :
313 0 : ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
314 : &func, &end);
315 0 : if (ret != 4) {
316 0 : seg = 0;
317 0 : ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
318 0 : if (ret != 3) {
319 : ret = -EINVAL;
320 : goto free_and_exit;
321 : }
322 : }
323 :
324 0 : ret = (seg == pci_domain_nr(dev->bus) &&
325 0 : bus == dev->bus->number &&
326 0 : dev->devfn == PCI_DEVFN(slot, func));
327 :
328 : free_and_exit:
329 0 : kfree(wpath);
330 0 : return ret;
331 : }
332 :
333 : /**
334 : * pci_dev_str_match - test if a string matches a device
335 : * @dev: the PCI device to test
336 : * @p: string to match the device against
337 : * @endptr: pointer to the string after the match
338 : *
339 : * Test if a string (typically from a kernel parameter) matches a specified
340 : * PCI device. The string may be of one of the following formats:
341 : *
342 : * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
343 : * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
344 : *
345 : * The first format specifies a PCI bus/device/function address which
346 : * may change if new hardware is inserted, if motherboard firmware changes,
347 : * or due to changes caused in kernel parameters. If the domain is
348 : * left unspecified, it is taken to be 0. In order to be robust against
349 : * bus renumbering issues, a path of PCI device/function numbers may be used
350 : * to address the specific device. The path for a device can be determined
351 : * through the use of 'lspci -t'.
352 : *
353 : * The second format matches devices using IDs in the configuration
354 : * space which may match multiple devices in the system. A value of 0
355 : * for any field will match all devices. (Note: this differs from
356 : * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
357 : * legacy reasons and convenience so users don't have to specify
358 : * FFFFFFFFs on the command line.)
359 : *
360 : * Returns 1 if the string matches the device, 0 if it does not and
361 : * a negative error code if the string cannot be parsed.
362 : */
363 0 : static int pci_dev_str_match(struct pci_dev *dev, const char *p,
364 : const char **endptr)
365 : {
366 : int ret;
367 : int count;
368 : unsigned short vendor, device, subsystem_vendor, subsystem_device;
369 :
370 0 : if (strncmp(p, "pci:", 4) == 0) {
371 : /* PCI vendor/device (subvendor/subdevice) IDs are specified */
372 0 : p += 4;
373 0 : ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
374 : &subsystem_vendor, &subsystem_device, &count);
375 0 : if (ret != 4) {
376 0 : ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
377 0 : if (ret != 2)
378 : return -EINVAL;
379 :
380 0 : subsystem_vendor = 0;
381 0 : subsystem_device = 0;
382 : }
383 :
384 0 : p += count;
385 :
386 0 : if ((!vendor || vendor == dev->vendor) &&
387 0 : (!device || device == dev->device) &&
388 0 : (!subsystem_vendor ||
389 0 : subsystem_vendor == dev->subsystem_vendor) &&
390 0 : (!subsystem_device ||
391 0 : subsystem_device == dev->subsystem_device))
392 : goto found;
393 : } else {
394 : /*
395 : * PCI Bus, Device, Function IDs are specified
396 : * (optionally, may include a path of devfns following it)
397 : */
398 0 : ret = pci_dev_str_match_path(dev, p, &p);
399 0 : if (ret < 0)
400 : return ret;
401 0 : else if (ret)
402 : goto found;
403 : }
404 :
405 0 : *endptr = p;
406 0 : return 0;
407 :
408 : found:
409 0 : *endptr = p;
410 0 : return 1;
411 : }
412 :
413 0 : static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
414 : u8 pos, int cap, int *ttl)
415 : {
416 : u8 id;
417 : u16 ent;
418 :
419 0 : pci_bus_read_config_byte(bus, devfn, pos, &pos);
420 :
421 0 : while ((*ttl)--) {
422 0 : if (pos < 0x40)
423 : break;
424 0 : pos &= ~3;
425 0 : pci_bus_read_config_word(bus, devfn, pos, &ent);
426 :
427 0 : id = ent & 0xff;
428 0 : if (id == 0xff)
429 : break;
430 0 : if (id == cap)
431 0 : return pos;
432 0 : pos = (ent >> 8);
433 : }
434 : return 0;
435 : }
436 :
437 : static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
438 : u8 pos, int cap)
439 : {
440 0 : int ttl = PCI_FIND_CAP_TTL;
441 :
442 0 : return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
443 : }
444 :
445 0 : u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
446 : {
447 0 : return __pci_find_next_cap(dev->bus, dev->devfn,
448 0 : pos + PCI_CAP_LIST_NEXT, cap);
449 : }
450 : EXPORT_SYMBOL_GPL(pci_find_next_capability);
451 :
452 0 : static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
453 : unsigned int devfn, u8 hdr_type)
454 : {
455 : u16 status;
456 :
457 0 : pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
458 0 : if (!(status & PCI_STATUS_CAP_LIST))
459 : return 0;
460 :
461 0 : switch (hdr_type) {
462 : case PCI_HEADER_TYPE_NORMAL:
463 : case PCI_HEADER_TYPE_BRIDGE:
464 : return PCI_CAPABILITY_LIST;
465 : case PCI_HEADER_TYPE_CARDBUS:
466 0 : return PCI_CB_CAPABILITY_LIST;
467 : }
468 :
469 0 : return 0;
470 : }
471 :
472 : /**
473 : * pci_find_capability - query for devices' capabilities
474 : * @dev: PCI device to query
475 : * @cap: capability code
476 : *
477 : * Tell if a device supports a given PCI capability.
478 : * Returns the address of the requested capability structure within the
479 : * device's PCI configuration space or 0 in case the device does not
480 : * support it. Possible values for @cap include:
481 : *
482 : * %PCI_CAP_ID_PM Power Management
483 : * %PCI_CAP_ID_AGP Accelerated Graphics Port
484 : * %PCI_CAP_ID_VPD Vital Product Data
485 : * %PCI_CAP_ID_SLOTID Slot Identification
486 : * %PCI_CAP_ID_MSI Message Signalled Interrupts
487 : * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
488 : * %PCI_CAP_ID_PCIX PCI-X
489 : * %PCI_CAP_ID_EXP PCI Express
490 : */
491 0 : u8 pci_find_capability(struct pci_dev *dev, int cap)
492 : {
493 : u8 pos;
494 :
495 0 : pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
496 0 : if (pos)
497 0 : pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
498 :
499 0 : return pos;
500 : }
501 : EXPORT_SYMBOL(pci_find_capability);
502 :
503 : /**
504 : * pci_bus_find_capability - query for devices' capabilities
505 : * @bus: the PCI bus to query
506 : * @devfn: PCI device to query
507 : * @cap: capability code
508 : *
509 : * Like pci_find_capability() but works for PCI devices that do not have a
510 : * pci_dev structure set up yet.
511 : *
512 : * Returns the address of the requested capability structure within the
513 : * device's PCI configuration space or 0 in case the device does not
514 : * support it.
515 : */
516 0 : u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
517 : {
518 : u8 hdr_type, pos;
519 :
520 0 : pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
521 :
522 0 : pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
523 0 : if (pos)
524 0 : pos = __pci_find_next_cap(bus, devfn, pos, cap);
525 :
526 0 : return pos;
527 : }
528 : EXPORT_SYMBOL(pci_bus_find_capability);
529 :
530 : /**
531 : * pci_find_next_ext_capability - Find an extended capability
532 : * @dev: PCI device to query
533 : * @start: address at which to start looking (0 to start at beginning of list)
534 : * @cap: capability code
535 : *
536 : * Returns the address of the next matching extended capability structure
537 : * within the device's PCI configuration space or 0 if the device does
538 : * not support it. Some capabilities can occur several times, e.g., the
539 : * vendor-specific capability, and this provides a way to find them all.
540 : */
541 0 : u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
542 : {
543 : u32 header;
544 : int ttl;
545 0 : u16 pos = PCI_CFG_SPACE_SIZE;
546 :
547 : /* minimum 8 bytes per capability */
548 0 : ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
549 :
550 0 : if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
551 : return 0;
552 :
553 0 : if (start)
554 0 : pos = start;
555 :
556 0 : if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
557 : return 0;
558 :
559 : /*
560 : * If we have no capabilities, this is indicated by cap ID,
561 : * cap version and next pointer all being 0.
562 : */
563 0 : if (header == 0)
564 : return 0;
565 :
566 0 : while (ttl-- > 0) {
567 0 : if (PCI_EXT_CAP_ID(header) == cap && pos != start)
568 : return pos;
569 :
570 0 : pos = PCI_EXT_CAP_NEXT(header);
571 0 : if (pos < PCI_CFG_SPACE_SIZE)
572 : break;
573 :
574 0 : if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
575 : break;
576 : }
577 :
578 : return 0;
579 : }
580 : EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
581 :
582 : /**
583 : * pci_find_ext_capability - Find an extended capability
584 : * @dev: PCI device to query
585 : * @cap: capability code
586 : *
587 : * Returns the address of the requested extended capability structure
588 : * within the device's PCI configuration space or 0 if the device does
589 : * not support it. Possible values for @cap include:
590 : *
591 : * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
592 : * %PCI_EXT_CAP_ID_VC Virtual Channel
593 : * %PCI_EXT_CAP_ID_DSN Device Serial Number
594 : * %PCI_EXT_CAP_ID_PWR Power Budgeting
595 : */
596 0 : u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
597 : {
598 0 : return pci_find_next_ext_capability(dev, 0, cap);
599 : }
600 : EXPORT_SYMBOL_GPL(pci_find_ext_capability);
601 :
602 : /**
603 : * pci_get_dsn - Read and return the 8-byte Device Serial Number
604 : * @dev: PCI device to query
605 : *
606 : * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
607 : * Number.
608 : *
609 : * Returns the DSN, or zero if the capability does not exist.
610 : */
611 0 : u64 pci_get_dsn(struct pci_dev *dev)
612 : {
613 : u32 dword;
614 : u64 dsn;
615 : int pos;
616 :
617 0 : pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
618 0 : if (!pos)
619 : return 0;
620 :
621 : /*
622 : * The Device Serial Number is two dwords offset 4 bytes from the
623 : * capability position. The specification says that the first dword is
624 : * the lower half, and the second dword is the upper half.
625 : */
626 0 : pos += 4;
627 0 : pci_read_config_dword(dev, pos, &dword);
628 0 : dsn = (u64)dword;
629 0 : pci_read_config_dword(dev, pos + 4, &dword);
630 0 : dsn |= ((u64)dword) << 32;
631 :
632 0 : return dsn;
633 : }
634 : EXPORT_SYMBOL_GPL(pci_get_dsn);
635 :
636 0 : static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
637 : {
638 0 : int rc, ttl = PCI_FIND_CAP_TTL;
639 : u8 cap, mask;
640 :
641 0 : if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
642 : mask = HT_3BIT_CAP_MASK;
643 : else
644 0 : mask = HT_5BIT_CAP_MASK;
645 :
646 0 : pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
647 : PCI_CAP_ID_HT, &ttl);
648 0 : while (pos) {
649 0 : rc = pci_read_config_byte(dev, pos + 3, &cap);
650 0 : if (rc != PCIBIOS_SUCCESSFUL)
651 : return 0;
652 :
653 0 : if ((cap & mask) == ht_cap)
654 : return pos;
655 :
656 0 : pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
657 0 : pos + PCI_CAP_LIST_NEXT,
658 : PCI_CAP_ID_HT, &ttl);
659 : }
660 :
661 : return 0;
662 : }
663 :
664 : /**
665 : * pci_find_next_ht_capability - query a device's HyperTransport capabilities
666 : * @dev: PCI device to query
667 : * @pos: Position from which to continue searching
668 : * @ht_cap: HyperTransport capability code
669 : *
670 : * To be used in conjunction with pci_find_ht_capability() to search for
671 : * all capabilities matching @ht_cap. @pos should always be a value returned
672 : * from pci_find_ht_capability().
673 : *
674 : * NB. To be 100% safe against broken PCI devices, the caller should take
675 : * steps to avoid an infinite loop.
676 : */
677 0 : u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
678 : {
679 0 : return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
680 : }
681 : EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
682 :
683 : /**
684 : * pci_find_ht_capability - query a device's HyperTransport capabilities
685 : * @dev: PCI device to query
686 : * @ht_cap: HyperTransport capability code
687 : *
688 : * Tell if a device supports a given HyperTransport capability.
689 : * Returns an address within the device's PCI configuration space
690 : * or 0 in case the device does not support the request capability.
691 : * The address points to the PCI capability, of type PCI_CAP_ID_HT,
692 : * which has a HyperTransport capability matching @ht_cap.
693 : */
694 0 : u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
695 : {
696 : u8 pos;
697 :
698 0 : pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
699 0 : if (pos)
700 0 : pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
701 :
702 0 : return pos;
703 : }
704 : EXPORT_SYMBOL_GPL(pci_find_ht_capability);
705 :
706 : /**
707 : * pci_find_vsec_capability - Find a vendor-specific extended capability
708 : * @dev: PCI device to query
709 : * @vendor: Vendor ID for which capability is defined
710 : * @cap: Vendor-specific capability ID
711 : *
712 : * If @dev has Vendor ID @vendor, search for a VSEC capability with
713 : * VSEC ID @cap. If found, return the capability offset in
714 : * config space; otherwise return 0.
715 : */
716 0 : u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
717 : {
718 0 : u16 vsec = 0;
719 : u32 header;
720 :
721 0 : if (vendor != dev->vendor)
722 : return 0;
723 :
724 0 : while ((vsec = pci_find_next_ext_capability(dev, vsec,
725 : PCI_EXT_CAP_ID_VNDR))) {
726 0 : if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER,
727 0 : &header) == PCIBIOS_SUCCESSFUL &&
728 0 : PCI_VNDR_HEADER_ID(header) == cap)
729 : return vsec;
730 : }
731 :
732 : return 0;
733 : }
734 : EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
735 :
736 : /**
737 : * pci_find_dvsec_capability - Find DVSEC for vendor
738 : * @dev: PCI device to query
739 : * @vendor: Vendor ID to match for the DVSEC
740 : * @dvsec: Designated Vendor-specific capability ID
741 : *
742 : * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability
743 : * offset in config space; otherwise return 0.
744 : */
745 0 : u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec)
746 : {
747 : int pos;
748 :
749 0 : pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DVSEC);
750 0 : if (!pos)
751 : return 0;
752 :
753 0 : while (pos) {
754 : u16 v, id;
755 :
756 0 : pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v);
757 0 : pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id);
758 0 : if (vendor == v && dvsec == id)
759 0 : return pos;
760 :
761 0 : pos = pci_find_next_ext_capability(dev, pos, PCI_EXT_CAP_ID_DVSEC);
762 : }
763 :
764 : return 0;
765 : }
766 : EXPORT_SYMBOL_GPL(pci_find_dvsec_capability);
767 :
768 : /**
769 : * pci_find_parent_resource - return resource region of parent bus of given
770 : * region
771 : * @dev: PCI device structure contains resources to be searched
772 : * @res: child resource record for which parent is sought
773 : *
774 : * For given resource region of given device, return the resource region of
775 : * parent bus the given region is contained in.
776 : */
777 0 : struct resource *pci_find_parent_resource(const struct pci_dev *dev,
778 : struct resource *res)
779 : {
780 0 : const struct pci_bus *bus = dev->bus;
781 : struct resource *r;
782 : int i;
783 :
784 0 : pci_bus_for_each_resource(bus, r, i) {
785 0 : if (!r)
786 0 : continue;
787 0 : if (resource_contains(r, res)) {
788 :
789 : /*
790 : * If the window is prefetchable but the BAR is
791 : * not, the allocator made a mistake.
792 : */
793 0 : if (r->flags & IORESOURCE_PREFETCH &&
794 0 : !(res->flags & IORESOURCE_PREFETCH))
795 : return NULL;
796 :
797 : /*
798 : * If we're below a transparent bridge, there may
799 : * be both a positively-decoded aperture and a
800 : * subtractively-decoded region that contain the BAR.
801 : * We want the positively-decoded one, so this depends
802 : * on pci_bus_for_each_resource() giving us those
803 : * first.
804 : */
805 0 : return r;
806 : }
807 : }
808 : return NULL;
809 : }
810 : EXPORT_SYMBOL(pci_find_parent_resource);
811 :
812 : /**
813 : * pci_find_resource - Return matching PCI device resource
814 : * @dev: PCI device to query
815 : * @res: Resource to look for
816 : *
817 : * Goes over standard PCI resources (BARs) and checks if the given resource
818 : * is partially or fully contained in any of them. In that case the
819 : * matching resource is returned, %NULL otherwise.
820 : */
821 0 : struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
822 : {
823 : int i;
824 :
825 0 : for (i = 0; i < PCI_STD_NUM_BARS; i++) {
826 0 : struct resource *r = &dev->resource[i];
827 :
828 0 : if (r->start && resource_contains(r, res))
829 : return r;
830 : }
831 :
832 : return NULL;
833 : }
834 : EXPORT_SYMBOL(pci_find_resource);
835 :
836 : /**
837 : * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
838 : * @dev: the PCI device to operate on
839 : * @pos: config space offset of status word
840 : * @mask: mask of bit(s) to care about in status word
841 : *
842 : * Return 1 when mask bit(s) in status word clear, 0 otherwise.
843 : */
844 0 : int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
845 : {
846 : int i;
847 :
848 : /* Wait for Transaction Pending bit clean */
849 0 : for (i = 0; i < 4; i++) {
850 : u16 status;
851 0 : if (i)
852 0 : msleep((1 << (i - 1)) * 100);
853 :
854 0 : pci_read_config_word(dev, pos, &status);
855 0 : if (!(status & mask))
856 0 : return 1;
857 : }
858 :
859 : return 0;
860 : }
861 :
862 : static int pci_acs_enable;
863 :
864 : /**
865 : * pci_request_acs - ask for ACS to be enabled if supported
866 : */
867 0 : void pci_request_acs(void)
868 : {
869 0 : pci_acs_enable = 1;
870 0 : }
871 :
872 : static const char *disable_acs_redir_param;
873 :
874 : /**
875 : * pci_disable_acs_redir - disable ACS redirect capabilities
876 : * @dev: the PCI device
877 : *
878 : * For only devices specified in the disable_acs_redir parameter.
879 : */
880 0 : static void pci_disable_acs_redir(struct pci_dev *dev)
881 : {
882 0 : int ret = 0;
883 : const char *p;
884 : int pos;
885 : u16 ctrl;
886 :
887 0 : if (!disable_acs_redir_param)
888 0 : return;
889 :
890 0 : p = disable_acs_redir_param;
891 0 : while (*p) {
892 0 : ret = pci_dev_str_match(dev, p, &p);
893 0 : if (ret < 0) {
894 0 : pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
895 : disable_acs_redir_param);
896 :
897 : break;
898 0 : } else if (ret == 1) {
899 : /* Found a match */
900 : break;
901 : }
902 :
903 0 : if (*p != ';' && *p != ',') {
904 : /* End of param or invalid format */
905 : break;
906 : }
907 0 : p++;
908 : }
909 :
910 0 : if (ret != 1)
911 : return;
912 :
913 0 : if (!pci_dev_specific_disable_acs_redir(dev))
914 : return;
915 :
916 0 : pos = dev->acs_cap;
917 0 : if (!pos) {
918 0 : pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
919 0 : return;
920 : }
921 :
922 0 : pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
923 :
924 : /* P2P Request & Completion Redirect */
925 0 : ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
926 :
927 0 : pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
928 :
929 0 : pci_info(dev, "disabled ACS redirect\n");
930 : }
931 :
932 : /**
933 : * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
934 : * @dev: the PCI device
935 : */
936 0 : static void pci_std_enable_acs(struct pci_dev *dev)
937 : {
938 : int pos;
939 : u16 cap;
940 : u16 ctrl;
941 :
942 0 : pos = dev->acs_cap;
943 0 : if (!pos)
944 0 : return;
945 :
946 0 : pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
947 0 : pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
948 :
949 : /* Source Validation */
950 0 : ctrl |= (cap & PCI_ACS_SV);
951 :
952 : /* P2P Request Redirect */
953 0 : ctrl |= (cap & PCI_ACS_RR);
954 :
955 : /* P2P Completion Redirect */
956 0 : ctrl |= (cap & PCI_ACS_CR);
957 :
958 : /* Upstream Forwarding */
959 0 : ctrl |= (cap & PCI_ACS_UF);
960 :
961 : /* Enable Translation Blocking for external devices and noats */
962 0 : if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
963 0 : ctrl |= (cap & PCI_ACS_TB);
964 :
965 0 : pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
966 : }
967 :
968 : /**
969 : * pci_enable_acs - enable ACS if hardware support it
970 : * @dev: the PCI device
971 : */
972 0 : static void pci_enable_acs(struct pci_dev *dev)
973 : {
974 0 : if (!pci_acs_enable)
975 : goto disable_acs_redir;
976 :
977 0 : if (!pci_dev_specific_enable_acs(dev))
978 : goto disable_acs_redir;
979 :
980 0 : pci_std_enable_acs(dev);
981 :
982 : disable_acs_redir:
983 : /*
984 : * Note: pci_disable_acs_redir() must be called even if ACS was not
985 : * enabled by the kernel because it may have been enabled by
986 : * platform firmware. So if we are told to disable it, we should
987 : * always disable it after setting the kernel's default
988 : * preferences.
989 : */
990 0 : pci_disable_acs_redir(dev);
991 0 : }
992 :
993 : /**
994 : * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
995 : * @dev: PCI device to have its BARs restored
996 : *
997 : * Restore the BAR values for a given device, so as to make it
998 : * accessible by its driver.
999 : */
1000 : static void pci_restore_bars(struct pci_dev *dev)
1001 : {
1002 : int i;
1003 :
1004 0 : for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
1005 0 : pci_update_resource(dev, i);
1006 : }
1007 :
1008 : static inline bool platform_pci_power_manageable(struct pci_dev *dev)
1009 : {
1010 : if (pci_use_mid_pm())
1011 : return true;
1012 :
1013 0 : return acpi_pci_power_manageable(dev);
1014 : }
1015 :
1016 : static inline int platform_pci_set_power_state(struct pci_dev *dev,
1017 : pci_power_t t)
1018 : {
1019 : if (pci_use_mid_pm())
1020 : return mid_pci_set_power_state(dev, t);
1021 :
1022 0 : return acpi_pci_set_power_state(dev, t);
1023 : }
1024 :
1025 : static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
1026 : {
1027 : if (pci_use_mid_pm())
1028 : return mid_pci_get_power_state(dev);
1029 :
1030 0 : return acpi_pci_get_power_state(dev);
1031 : }
1032 :
1033 : static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
1034 : {
1035 : if (!pci_use_mid_pm())
1036 : acpi_pci_refresh_power_state(dev);
1037 : }
1038 :
1039 : static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1040 : {
1041 : if (pci_use_mid_pm())
1042 : return PCI_POWER_ERROR;
1043 :
1044 : return acpi_pci_choose_state(dev);
1045 : }
1046 :
1047 : static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1048 : {
1049 : if (pci_use_mid_pm())
1050 : return PCI_POWER_ERROR;
1051 :
1052 0 : return acpi_pci_wakeup(dev, enable);
1053 : }
1054 :
1055 : static inline bool platform_pci_need_resume(struct pci_dev *dev)
1056 : {
1057 : if (pci_use_mid_pm())
1058 : return false;
1059 :
1060 0 : return acpi_pci_need_resume(dev);
1061 : }
1062 :
1063 : static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1064 : {
1065 : if (pci_use_mid_pm())
1066 : return false;
1067 :
1068 0 : return acpi_pci_bridge_d3(dev);
1069 : }
1070 :
1071 : /**
1072 : * pci_update_current_state - Read power state of given device and cache it
1073 : * @dev: PCI device to handle.
1074 : * @state: State to cache in case the device doesn't have the PM capability
1075 : *
1076 : * The power state is read from the PMCSR register, which however is
1077 : * inaccessible in D3cold. The platform firmware is therefore queried first
1078 : * to detect accessibility of the register. In case the platform firmware
1079 : * reports an incorrect state or the device isn't power manageable by the
1080 : * platform at all, we try to detect D3cold by testing accessibility of the
1081 : * vendor ID in config space.
1082 : */
1083 0 : void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1084 : {
1085 0 : if (platform_pci_get_power_state(dev) == PCI_D3cold) {
1086 : dev->current_state = PCI_D3cold;
1087 0 : } else if (dev->pm_cap) {
1088 : u16 pmcsr;
1089 :
1090 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1091 0 : if (PCI_POSSIBLE_ERROR(pmcsr)) {
1092 0 : dev->current_state = PCI_D3cold;
1093 0 : return;
1094 : }
1095 0 : dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1096 : } else {
1097 0 : dev->current_state = state;
1098 : }
1099 : }
1100 :
1101 : /**
1102 : * pci_refresh_power_state - Refresh the given device's power state data
1103 : * @dev: Target PCI device.
1104 : *
1105 : * Ask the platform to refresh the devices power state information and invoke
1106 : * pci_update_current_state() to update its current PCI power state.
1107 : */
1108 0 : void pci_refresh_power_state(struct pci_dev *dev)
1109 : {
1110 0 : platform_pci_refresh_power_state(dev);
1111 0 : pci_update_current_state(dev, dev->current_state);
1112 0 : }
1113 :
1114 : /**
1115 : * pci_platform_power_transition - Use platform to change device power state
1116 : * @dev: PCI device to handle.
1117 : * @state: State to put the device into.
1118 : */
1119 0 : int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1120 : {
1121 : int error;
1122 :
1123 0 : error = platform_pci_set_power_state(dev, state);
1124 : if (!error)
1125 : pci_update_current_state(dev, state);
1126 0 : else if (!dev->pm_cap) /* Fall back to PCI_D0 */
1127 0 : dev->current_state = PCI_D0;
1128 :
1129 0 : return error;
1130 : }
1131 : EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1132 :
1133 0 : static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1134 : {
1135 0 : pm_request_resume(&pci_dev->dev);
1136 0 : return 0;
1137 : }
1138 :
1139 : /**
1140 : * pci_resume_bus - Walk given bus and runtime resume devices on it
1141 : * @bus: Top bus of the subtree to walk.
1142 : */
1143 0 : void pci_resume_bus(struct pci_bus *bus)
1144 : {
1145 0 : if (bus)
1146 0 : pci_walk_bus(bus, pci_resume_one, NULL);
1147 0 : }
1148 :
1149 0 : static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1150 : {
1151 0 : int delay = 1;
1152 : u32 id;
1153 :
1154 : /*
1155 : * After reset, the device should not silently discard config
1156 : * requests, but it may still indicate that it needs more time by
1157 : * responding to them with CRS completions. The Root Port will
1158 : * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
1159 : * the read (except when CRS SV is enabled and the read was for the
1160 : * Vendor ID; in that case it synthesizes 0x0001 data).
1161 : *
1162 : * Wait for the device to return a non-CRS completion. Read the
1163 : * Command register instead of Vendor ID so we don't have to
1164 : * contend with the CRS SV value.
1165 : */
1166 0 : pci_read_config_dword(dev, PCI_COMMAND, &id);
1167 0 : while (PCI_POSSIBLE_ERROR(id)) {
1168 0 : if (delay > timeout) {
1169 0 : pci_warn(dev, "not ready %dms after %s; giving up\n",
1170 : delay - 1, reset_type);
1171 0 : return -ENOTTY;
1172 : }
1173 :
1174 0 : if (delay > PCI_RESET_WAIT)
1175 0 : pci_info(dev, "not ready %dms after %s; waiting\n",
1176 : delay - 1, reset_type);
1177 :
1178 0 : msleep(delay);
1179 0 : delay *= 2;
1180 0 : pci_read_config_dword(dev, PCI_COMMAND, &id);
1181 : }
1182 :
1183 0 : if (delay > PCI_RESET_WAIT)
1184 0 : pci_info(dev, "ready %dms after %s\n", delay - 1,
1185 : reset_type);
1186 :
1187 : return 0;
1188 : }
1189 :
1190 : /**
1191 : * pci_power_up - Put the given device into D0
1192 : * @dev: PCI device to power up
1193 : *
1194 : * On success, return 0 or 1, depending on whether or not it is necessary to
1195 : * restore the device's BARs subsequently (1 is returned in that case).
1196 : */
1197 0 : int pci_power_up(struct pci_dev *dev)
1198 : {
1199 : bool need_restore;
1200 : pci_power_t state;
1201 : u16 pmcsr;
1202 :
1203 0 : platform_pci_set_power_state(dev, PCI_D0);
1204 :
1205 0 : if (!dev->pm_cap) {
1206 0 : state = platform_pci_get_power_state(dev);
1207 : if (state == PCI_UNKNOWN)
1208 0 : dev->current_state = PCI_D0;
1209 : else
1210 : dev->current_state = state;
1211 :
1212 : if (state == PCI_D0)
1213 : return 0;
1214 :
1215 : return -EIO;
1216 : }
1217 :
1218 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1219 0 : if (PCI_POSSIBLE_ERROR(pmcsr)) {
1220 0 : pci_err(dev, "Unable to change power state from %s to D0, device inaccessible\n",
1221 : pci_power_name(dev->current_state));
1222 0 : dev->current_state = PCI_D3cold;
1223 0 : return -EIO;
1224 : }
1225 :
1226 0 : state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1227 :
1228 0 : need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) &&
1229 : !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET);
1230 :
1231 0 : if (state == PCI_D0)
1232 : goto end;
1233 :
1234 : /*
1235 : * Force the entire word to 0. This doesn't affect PME_Status, disables
1236 : * PME_En, and sets PowerState to 0.
1237 : */
1238 0 : pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);
1239 :
1240 : /* Mandatory transition delays; see PCI PM 1.2. */
1241 0 : if (state == PCI_D3hot)
1242 0 : pci_dev_d3_sleep(dev);
1243 0 : else if (state == PCI_D2)
1244 : udelay(PCI_PM_D2_DELAY);
1245 :
1246 : end:
1247 0 : dev->current_state = PCI_D0;
1248 0 : if (need_restore)
1249 : return 1;
1250 :
1251 0 : return 0;
1252 : }
1253 :
1254 : /**
1255 : * pci_set_full_power_state - Put a PCI device into D0 and update its state
1256 : * @dev: PCI device to power up
1257 : *
1258 : * Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register
1259 : * to confirm the state change, restore its BARs if they might be lost and
1260 : * reconfigure ASPM in acordance with the new power state.
1261 : *
1262 : * If pci_restore_state() is going to be called right after a power state change
1263 : * to D0, it is more efficient to use pci_power_up() directly instead of this
1264 : * function.
1265 : */
1266 0 : static int pci_set_full_power_state(struct pci_dev *dev)
1267 : {
1268 : u16 pmcsr;
1269 : int ret;
1270 :
1271 0 : ret = pci_power_up(dev);
1272 0 : if (ret < 0)
1273 : return ret;
1274 :
1275 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1276 0 : dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1277 0 : if (dev->current_state != PCI_D0) {
1278 0 : pci_info_ratelimited(dev, "Refused to change power state from %s to D0\n",
1279 : pci_power_name(dev->current_state));
1280 0 : } else if (ret > 0) {
1281 : /*
1282 : * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1283 : * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1284 : * from D3hot to D0 _may_ perform an internal reset, thereby
1285 : * going to "D0 Uninitialized" rather than "D0 Initialized".
1286 : * For example, at least some versions of the 3c905B and the
1287 : * 3c556B exhibit this behaviour.
1288 : *
1289 : * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1290 : * devices in a D3hot state at boot. Consequently, we need to
1291 : * restore at least the BARs so that the device will be
1292 : * accessible to its driver.
1293 : */
1294 : pci_restore_bars(dev);
1295 : }
1296 :
1297 : return 0;
1298 : }
1299 :
1300 : /**
1301 : * __pci_dev_set_current_state - Set current state of a PCI device
1302 : * @dev: Device to handle
1303 : * @data: pointer to state to be set
1304 : */
1305 0 : static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1306 : {
1307 0 : pci_power_t state = *(pci_power_t *)data;
1308 :
1309 0 : dev->current_state = state;
1310 0 : return 0;
1311 : }
1312 :
1313 : /**
1314 : * pci_bus_set_current_state - Walk given bus and set current state of devices
1315 : * @bus: Top bus of the subtree to walk.
1316 : * @state: state to be set
1317 : */
1318 0 : void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1319 : {
1320 0 : if (bus)
1321 0 : pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1322 0 : }
1323 :
1324 : /**
1325 : * pci_set_low_power_state - Put a PCI device into a low-power state.
1326 : * @dev: PCI device to handle.
1327 : * @state: PCI power state (D1, D2, D3hot) to put the device into.
1328 : *
1329 : * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1330 : *
1331 : * RETURN VALUE:
1332 : * -EINVAL if the requested state is invalid.
1333 : * -EIO if device does not support PCI PM or its PM capabilities register has a
1334 : * wrong version, or device doesn't support the requested state.
1335 : * 0 if device already is in the requested state.
1336 : * 0 if device's power state has been successfully changed.
1337 : */
1338 0 : static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state)
1339 : {
1340 : u16 pmcsr;
1341 :
1342 0 : if (!dev->pm_cap)
1343 : return -EIO;
1344 :
1345 : /*
1346 : * Validate transition: We can enter D0 from any state, but if
1347 : * we're already in a low-power state, we can only go deeper. E.g.,
1348 : * we can go from D1 to D3, but we can't go directly from D3 to D1;
1349 : * we'd have to go from D3 to D0, then to D1.
1350 : */
1351 0 : if (dev->current_state <= PCI_D3cold && dev->current_state > state) {
1352 : pci_dbg(dev, "Invalid power transition (from %s to %s)\n",
1353 : pci_power_name(dev->current_state),
1354 : pci_power_name(state));
1355 : return -EINVAL;
1356 : }
1357 :
1358 : /* Check if this device supports the desired state */
1359 0 : if ((state == PCI_D1 && !dev->d1_support)
1360 0 : || (state == PCI_D2 && !dev->d2_support))
1361 : return -EIO;
1362 :
1363 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1364 0 : if (PCI_POSSIBLE_ERROR(pmcsr)) {
1365 0 : pci_err(dev, "Unable to change power state from %s to %s, device inaccessible\n",
1366 : pci_power_name(dev->current_state),
1367 : pci_power_name(state));
1368 0 : dev->current_state = PCI_D3cold;
1369 0 : return -EIO;
1370 : }
1371 :
1372 0 : pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1373 0 : pmcsr |= state;
1374 :
1375 : /* Enter specified state */
1376 0 : pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1377 :
1378 : /* Mandatory power management transition delays; see PCI PM 1.2. */
1379 0 : if (state == PCI_D3hot)
1380 0 : pci_dev_d3_sleep(dev);
1381 0 : else if (state == PCI_D2)
1382 : udelay(PCI_PM_D2_DELAY);
1383 :
1384 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1385 0 : dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1386 0 : if (dev->current_state != state)
1387 0 : pci_info_ratelimited(dev, "Refused to change power state from %s to %s\n",
1388 : pci_power_name(dev->current_state),
1389 : pci_power_name(state));
1390 :
1391 : return 0;
1392 : }
1393 :
1394 : /**
1395 : * pci_set_power_state - Set the power state of a PCI device
1396 : * @dev: PCI device to handle.
1397 : * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1398 : *
1399 : * Transition a device to a new power state, using the platform firmware and/or
1400 : * the device's PCI PM registers.
1401 : *
1402 : * RETURN VALUE:
1403 : * -EINVAL if the requested state is invalid.
1404 : * -EIO if device does not support PCI PM or its PM capabilities register has a
1405 : * wrong version, or device doesn't support the requested state.
1406 : * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1407 : * 0 if device already is in the requested state.
1408 : * 0 if the transition is to D3 but D3 is not supported.
1409 : * 0 if device's power state has been successfully changed.
1410 : */
1411 0 : int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1412 : {
1413 : int error;
1414 :
1415 : /* Bound the state we're entering */
1416 0 : if (state > PCI_D3cold)
1417 : state = PCI_D3cold;
1418 0 : else if (state < PCI_D0)
1419 : state = PCI_D0;
1420 0 : else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1421 :
1422 : /*
1423 : * If the device or the parent bridge do not support PCI
1424 : * PM, ignore the request if we're doing anything other
1425 : * than putting it into D0 (which would only happen on
1426 : * boot).
1427 : */
1428 : return 0;
1429 :
1430 : /* Check if we're already there */
1431 0 : if (dev->current_state == state)
1432 : return 0;
1433 :
1434 0 : if (state == PCI_D0)
1435 0 : return pci_set_full_power_state(dev);
1436 :
1437 : /*
1438 : * This device is quirked not to be put into D3, so don't put it in
1439 : * D3
1440 : */
1441 0 : if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1442 : return 0;
1443 :
1444 0 : if (state == PCI_D3cold) {
1445 : /*
1446 : * To put the device in D3cold, put it into D3hot in the native
1447 : * way, then put it into D3cold using platform ops.
1448 : */
1449 0 : error = pci_set_low_power_state(dev, PCI_D3hot);
1450 :
1451 : if (pci_platform_power_transition(dev, PCI_D3cold))
1452 : return error;
1453 :
1454 : /* Powering off a bridge may power off the whole hierarchy */
1455 : if (dev->current_state == PCI_D3cold)
1456 : pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1457 : } else {
1458 0 : error = pci_set_low_power_state(dev, state);
1459 :
1460 : if (pci_platform_power_transition(dev, state))
1461 : return error;
1462 : }
1463 :
1464 : return 0;
1465 : }
1466 : EXPORT_SYMBOL(pci_set_power_state);
1467 :
1468 : #define PCI_EXP_SAVE_REGS 7
1469 :
1470 : static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1471 : u16 cap, bool extended)
1472 : {
1473 : struct pci_cap_saved_state *tmp;
1474 :
1475 0 : hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1476 0 : if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1477 : return tmp;
1478 : }
1479 : return NULL;
1480 : }
1481 :
1482 0 : struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1483 : {
1484 0 : return _pci_find_saved_cap(dev, cap, false);
1485 : }
1486 :
1487 0 : struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1488 : {
1489 0 : return _pci_find_saved_cap(dev, cap, true);
1490 : }
1491 :
1492 0 : static int pci_save_pcie_state(struct pci_dev *dev)
1493 : {
1494 0 : int i = 0;
1495 : struct pci_cap_saved_state *save_state;
1496 : u16 *cap;
1497 :
1498 0 : if (!pci_is_pcie(dev))
1499 : return 0;
1500 :
1501 0 : save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1502 0 : if (!save_state) {
1503 0 : pci_err(dev, "buffer not found in %s\n", __func__);
1504 0 : return -ENOMEM;
1505 : }
1506 :
1507 0 : cap = (u16 *)&save_state->cap.data[0];
1508 0 : pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1509 0 : pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1510 0 : pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1511 0 : pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1512 0 : pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1513 0 : pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1514 0 : pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1515 :
1516 0 : return 0;
1517 : }
1518 :
1519 0 : void pci_bridge_reconfigure_ltr(struct pci_dev *dev)
1520 : {
1521 : #ifdef CONFIG_PCIEASPM
1522 : struct pci_dev *bridge;
1523 : u32 ctl;
1524 :
1525 0 : bridge = pci_upstream_bridge(dev);
1526 0 : if (bridge && bridge->ltr_path) {
1527 0 : pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1528 0 : if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1529 : pci_dbg(bridge, "re-enabling LTR\n");
1530 : pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1531 : PCI_EXP_DEVCTL2_LTR_EN);
1532 : }
1533 : }
1534 : #endif
1535 0 : }
1536 :
1537 0 : static void pci_restore_pcie_state(struct pci_dev *dev)
1538 : {
1539 0 : int i = 0;
1540 : struct pci_cap_saved_state *save_state;
1541 : u16 *cap;
1542 :
1543 0 : save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1544 0 : if (!save_state)
1545 : return;
1546 :
1547 : /*
1548 : * Downstream ports reset the LTR enable bit when link goes down.
1549 : * Check and re-configure the bit here before restoring device.
1550 : * PCIe r5.0, sec 7.5.3.16.
1551 : */
1552 0 : pci_bridge_reconfigure_ltr(dev);
1553 :
1554 0 : cap = (u16 *)&save_state->cap.data[0];
1555 0 : pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1556 0 : pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1557 0 : pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1558 0 : pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1559 0 : pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1560 0 : pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1561 0 : pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1562 : }
1563 :
1564 0 : static int pci_save_pcix_state(struct pci_dev *dev)
1565 : {
1566 : int pos;
1567 : struct pci_cap_saved_state *save_state;
1568 :
1569 0 : pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1570 0 : if (!pos)
1571 : return 0;
1572 :
1573 0 : save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1574 0 : if (!save_state) {
1575 0 : pci_err(dev, "buffer not found in %s\n", __func__);
1576 0 : return -ENOMEM;
1577 : }
1578 :
1579 0 : pci_read_config_word(dev, pos + PCI_X_CMD,
1580 0 : (u16 *)save_state->cap.data);
1581 :
1582 0 : return 0;
1583 : }
1584 :
1585 0 : static void pci_restore_pcix_state(struct pci_dev *dev)
1586 : {
1587 0 : int i = 0, pos;
1588 : struct pci_cap_saved_state *save_state;
1589 : u16 *cap;
1590 :
1591 0 : save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1592 0 : pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1593 0 : if (!save_state || !pos)
1594 : return;
1595 0 : cap = (u16 *)&save_state->cap.data[0];
1596 :
1597 0 : pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1598 : }
1599 :
1600 0 : static void pci_save_ltr_state(struct pci_dev *dev)
1601 : {
1602 : int ltr;
1603 : struct pci_cap_saved_state *save_state;
1604 : u32 *cap;
1605 :
1606 0 : if (!pci_is_pcie(dev))
1607 : return;
1608 :
1609 0 : ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1610 0 : if (!ltr)
1611 : return;
1612 :
1613 0 : save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1614 0 : if (!save_state) {
1615 0 : pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1616 0 : return;
1617 : }
1618 :
1619 : /* Some broken devices only support dword access to LTR */
1620 0 : cap = &save_state->cap.data[0];
1621 0 : pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
1622 : }
1623 :
1624 0 : static void pci_restore_ltr_state(struct pci_dev *dev)
1625 : {
1626 : struct pci_cap_saved_state *save_state;
1627 : int ltr;
1628 : u32 *cap;
1629 :
1630 0 : save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1631 0 : ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1632 0 : if (!save_state || !ltr)
1633 : return;
1634 :
1635 : /* Some broken devices only support dword access to LTR */
1636 0 : cap = &save_state->cap.data[0];
1637 0 : pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
1638 : }
1639 :
1640 : /**
1641 : * pci_save_state - save the PCI configuration space of a device before
1642 : * suspending
1643 : * @dev: PCI device that we're dealing with
1644 : */
1645 0 : int pci_save_state(struct pci_dev *dev)
1646 : {
1647 : int i;
1648 : /* XXX: 100% dword access ok here? */
1649 0 : for (i = 0; i < 16; i++) {
1650 0 : pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1651 : pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1652 : i * 4, dev->saved_config_space[i]);
1653 : }
1654 0 : dev->state_saved = true;
1655 :
1656 0 : i = pci_save_pcie_state(dev);
1657 0 : if (i != 0)
1658 : return i;
1659 :
1660 0 : i = pci_save_pcix_state(dev);
1661 0 : if (i != 0)
1662 : return i;
1663 :
1664 0 : pci_save_ltr_state(dev);
1665 0 : pci_save_dpc_state(dev);
1666 0 : pci_save_aer_state(dev);
1667 0 : pci_save_ptm_state(dev);
1668 0 : return pci_save_vc_state(dev);
1669 : }
1670 : EXPORT_SYMBOL(pci_save_state);
1671 :
1672 0 : static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1673 : u32 saved_val, int retry, bool force)
1674 : {
1675 : u32 val;
1676 :
1677 0 : pci_read_config_dword(pdev, offset, &val);
1678 0 : if (!force && val == saved_val)
1679 : return;
1680 :
1681 : for (;;) {
1682 : pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1683 : offset, val, saved_val);
1684 0 : pci_write_config_dword(pdev, offset, saved_val);
1685 0 : if (retry-- <= 0)
1686 : return;
1687 :
1688 0 : pci_read_config_dword(pdev, offset, &val);
1689 0 : if (val == saved_val)
1690 : return;
1691 :
1692 : mdelay(1);
1693 : }
1694 : }
1695 :
1696 : static void pci_restore_config_space_range(struct pci_dev *pdev,
1697 : int start, int end, int retry,
1698 : bool force)
1699 : {
1700 : int index;
1701 :
1702 0 : for (index = end; index >= start; index--)
1703 0 : pci_restore_config_dword(pdev, 4 * index,
1704 : pdev->saved_config_space[index],
1705 : retry, force);
1706 : }
1707 :
1708 0 : static void pci_restore_config_space(struct pci_dev *pdev)
1709 : {
1710 0 : if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1711 : pci_restore_config_space_range(pdev, 10, 15, 0, false);
1712 : /* Restore BARs before the command register. */
1713 : pci_restore_config_space_range(pdev, 4, 9, 10, false);
1714 : pci_restore_config_space_range(pdev, 0, 3, 0, false);
1715 0 : } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1716 : pci_restore_config_space_range(pdev, 12, 15, 0, false);
1717 :
1718 : /*
1719 : * Force rewriting of prefetch registers to avoid S3 resume
1720 : * issues on Intel PCI bridges that occur when these
1721 : * registers are not explicitly written.
1722 : */
1723 : pci_restore_config_space_range(pdev, 9, 11, 0, true);
1724 : pci_restore_config_space_range(pdev, 0, 8, 0, false);
1725 : } else {
1726 : pci_restore_config_space_range(pdev, 0, 15, 0, false);
1727 : }
1728 0 : }
1729 :
1730 0 : static void pci_restore_rebar_state(struct pci_dev *pdev)
1731 : {
1732 : unsigned int pos, nbars, i;
1733 : u32 ctrl;
1734 :
1735 0 : pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1736 0 : if (!pos)
1737 0 : return;
1738 :
1739 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1740 0 : nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1741 : PCI_REBAR_CTRL_NBAR_SHIFT;
1742 :
1743 0 : for (i = 0; i < nbars; i++, pos += 8) {
1744 : struct resource *res;
1745 : int bar_idx, size;
1746 :
1747 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1748 0 : bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1749 0 : res = pdev->resource + bar_idx;
1750 0 : size = pci_rebar_bytes_to_size(resource_size(res));
1751 0 : ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1752 0 : ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1753 0 : pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1754 : }
1755 : }
1756 :
1757 : /**
1758 : * pci_restore_state - Restore the saved state of a PCI device
1759 : * @dev: PCI device that we're dealing with
1760 : */
1761 0 : void pci_restore_state(struct pci_dev *dev)
1762 : {
1763 0 : if (!dev->state_saved)
1764 : return;
1765 :
1766 : /*
1767 : * Restore max latencies (in the LTR capability) before enabling
1768 : * LTR itself (in the PCIe capability).
1769 : */
1770 0 : pci_restore_ltr_state(dev);
1771 :
1772 0 : pci_restore_pcie_state(dev);
1773 0 : pci_restore_pasid_state(dev);
1774 0 : pci_restore_pri_state(dev);
1775 0 : pci_restore_ats_state(dev);
1776 0 : pci_restore_vc_state(dev);
1777 0 : pci_restore_rebar_state(dev);
1778 0 : pci_restore_dpc_state(dev);
1779 0 : pci_restore_ptm_state(dev);
1780 :
1781 0 : pci_aer_clear_status(dev);
1782 0 : pci_restore_aer_state(dev);
1783 :
1784 0 : pci_restore_config_space(dev);
1785 :
1786 0 : pci_restore_pcix_state(dev);
1787 0 : pci_restore_msi_state(dev);
1788 :
1789 : /* Restore ACS and IOV configuration state */
1790 0 : pci_enable_acs(dev);
1791 0 : pci_restore_iov_state(dev);
1792 :
1793 0 : dev->state_saved = false;
1794 : }
1795 : EXPORT_SYMBOL(pci_restore_state);
1796 :
1797 : struct pci_saved_state {
1798 : u32 config_space[16];
1799 : struct pci_cap_saved_data cap[];
1800 : };
1801 :
1802 : /**
1803 : * pci_store_saved_state - Allocate and return an opaque struct containing
1804 : * the device saved state.
1805 : * @dev: PCI device that we're dealing with
1806 : *
1807 : * Return NULL if no state or error.
1808 : */
1809 0 : struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1810 : {
1811 : struct pci_saved_state *state;
1812 : struct pci_cap_saved_state *tmp;
1813 : struct pci_cap_saved_data *cap;
1814 : size_t size;
1815 :
1816 0 : if (!dev->state_saved)
1817 : return NULL;
1818 :
1819 0 : size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1820 :
1821 0 : hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1822 0 : size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1823 :
1824 0 : state = kzalloc(size, GFP_KERNEL);
1825 0 : if (!state)
1826 : return NULL;
1827 :
1828 0 : memcpy(state->config_space, dev->saved_config_space,
1829 : sizeof(state->config_space));
1830 :
1831 0 : cap = state->cap;
1832 0 : hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1833 0 : size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1834 0 : memcpy(cap, &tmp->cap, len);
1835 0 : cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1836 : }
1837 : /* Empty cap_save terminates list */
1838 :
1839 : return state;
1840 : }
1841 : EXPORT_SYMBOL_GPL(pci_store_saved_state);
1842 :
1843 : /**
1844 : * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1845 : * @dev: PCI device that we're dealing with
1846 : * @state: Saved state returned from pci_store_saved_state()
1847 : */
1848 0 : int pci_load_saved_state(struct pci_dev *dev,
1849 : struct pci_saved_state *state)
1850 : {
1851 : struct pci_cap_saved_data *cap;
1852 :
1853 0 : dev->state_saved = false;
1854 :
1855 0 : if (!state)
1856 : return 0;
1857 :
1858 0 : memcpy(dev->saved_config_space, state->config_space,
1859 : sizeof(state->config_space));
1860 :
1861 0 : cap = state->cap;
1862 0 : while (cap->size) {
1863 : struct pci_cap_saved_state *tmp;
1864 :
1865 0 : tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1866 0 : if (!tmp || tmp->cap.size != cap->size)
1867 : return -EINVAL;
1868 :
1869 0 : memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1870 0 : cap = (struct pci_cap_saved_data *)((u8 *)cap +
1871 0 : sizeof(struct pci_cap_saved_data) + cap->size);
1872 : }
1873 :
1874 0 : dev->state_saved = true;
1875 0 : return 0;
1876 : }
1877 : EXPORT_SYMBOL_GPL(pci_load_saved_state);
1878 :
1879 : /**
1880 : * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1881 : * and free the memory allocated for it.
1882 : * @dev: PCI device that we're dealing with
1883 : * @state: Pointer to saved state returned from pci_store_saved_state()
1884 : */
1885 0 : int pci_load_and_free_saved_state(struct pci_dev *dev,
1886 : struct pci_saved_state **state)
1887 : {
1888 0 : int ret = pci_load_saved_state(dev, *state);
1889 0 : kfree(*state);
1890 0 : *state = NULL;
1891 0 : return ret;
1892 : }
1893 : EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1894 :
1895 0 : int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1896 : {
1897 0 : return pci_enable_resources(dev, bars);
1898 : }
1899 :
1900 0 : static int do_pci_enable_device(struct pci_dev *dev, int bars)
1901 : {
1902 : int err;
1903 : struct pci_dev *bridge;
1904 : u16 cmd;
1905 : u8 pin;
1906 :
1907 0 : err = pci_set_power_state(dev, PCI_D0);
1908 0 : if (err < 0 && err != -EIO)
1909 : return err;
1910 :
1911 0 : bridge = pci_upstream_bridge(dev);
1912 0 : if (bridge)
1913 0 : pcie_aspm_powersave_config_link(bridge);
1914 :
1915 0 : err = pcibios_enable_device(dev, bars);
1916 0 : if (err < 0)
1917 : return err;
1918 0 : pci_fixup_device(pci_fixup_enable, dev);
1919 :
1920 0 : if (dev->msi_enabled || dev->msix_enabled)
1921 : return 0;
1922 :
1923 0 : pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1924 0 : if (pin) {
1925 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
1926 0 : if (cmd & PCI_COMMAND_INTX_DISABLE)
1927 0 : pci_write_config_word(dev, PCI_COMMAND,
1928 : cmd & ~PCI_COMMAND_INTX_DISABLE);
1929 : }
1930 :
1931 : return 0;
1932 : }
1933 :
1934 : /**
1935 : * pci_reenable_device - Resume abandoned device
1936 : * @dev: PCI device to be resumed
1937 : *
1938 : * NOTE: This function is a backend of pci_default_resume() and is not supposed
1939 : * to be called by normal code, write proper resume handler and use it instead.
1940 : */
1941 0 : int pci_reenable_device(struct pci_dev *dev)
1942 : {
1943 0 : if (pci_is_enabled(dev))
1944 0 : return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1945 : return 0;
1946 : }
1947 : EXPORT_SYMBOL(pci_reenable_device);
1948 :
1949 0 : static void pci_enable_bridge(struct pci_dev *dev)
1950 : {
1951 : struct pci_dev *bridge;
1952 : int retval;
1953 :
1954 0 : bridge = pci_upstream_bridge(dev);
1955 0 : if (bridge)
1956 0 : pci_enable_bridge(bridge);
1957 :
1958 0 : if (pci_is_enabled(dev)) {
1959 0 : if (!dev->is_busmaster)
1960 : pci_set_master(dev);
1961 : return;
1962 : }
1963 :
1964 0 : retval = pci_enable_device(dev);
1965 0 : if (retval)
1966 0 : pci_err(dev, "Error enabling bridge (%d), continuing\n",
1967 : retval);
1968 : pci_set_master(dev);
1969 : }
1970 :
1971 0 : static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1972 : {
1973 : struct pci_dev *bridge;
1974 : int err;
1975 0 : int i, bars = 0;
1976 :
1977 : /*
1978 : * Power state could be unknown at this point, either due to a fresh
1979 : * boot or a device removal call. So get the current power state
1980 : * so that things like MSI message writing will behave as expected
1981 : * (e.g. if the device really is in D0 at enable time).
1982 : */
1983 0 : pci_update_current_state(dev, dev->current_state);
1984 :
1985 0 : if (atomic_inc_return(&dev->enable_cnt) > 1)
1986 : return 0; /* already enabled */
1987 :
1988 0 : bridge = pci_upstream_bridge(dev);
1989 0 : if (bridge)
1990 0 : pci_enable_bridge(bridge);
1991 :
1992 : /* only skip sriov related */
1993 0 : for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1994 0 : if (dev->resource[i].flags & flags)
1995 0 : bars |= (1 << i);
1996 0 : for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1997 0 : if (dev->resource[i].flags & flags)
1998 0 : bars |= (1 << i);
1999 :
2000 0 : err = do_pci_enable_device(dev, bars);
2001 0 : if (err < 0)
2002 0 : atomic_dec(&dev->enable_cnt);
2003 : return err;
2004 : }
2005 :
2006 : /**
2007 : * pci_enable_device_io - Initialize a device for use with IO space
2008 : * @dev: PCI device to be initialized
2009 : *
2010 : * Initialize device before it's used by a driver. Ask low-level code
2011 : * to enable I/O resources. Wake up the device if it was suspended.
2012 : * Beware, this function can fail.
2013 : */
2014 0 : int pci_enable_device_io(struct pci_dev *dev)
2015 : {
2016 0 : return pci_enable_device_flags(dev, IORESOURCE_IO);
2017 : }
2018 : EXPORT_SYMBOL(pci_enable_device_io);
2019 :
2020 : /**
2021 : * pci_enable_device_mem - Initialize a device for use with Memory space
2022 : * @dev: PCI device to be initialized
2023 : *
2024 : * Initialize device before it's used by a driver. Ask low-level code
2025 : * to enable Memory resources. Wake up the device if it was suspended.
2026 : * Beware, this function can fail.
2027 : */
2028 0 : int pci_enable_device_mem(struct pci_dev *dev)
2029 : {
2030 0 : return pci_enable_device_flags(dev, IORESOURCE_MEM);
2031 : }
2032 : EXPORT_SYMBOL(pci_enable_device_mem);
2033 :
2034 : /**
2035 : * pci_enable_device - Initialize device before it's used by a driver.
2036 : * @dev: PCI device to be initialized
2037 : *
2038 : * Initialize device before it's used by a driver. Ask low-level code
2039 : * to enable I/O and memory. Wake up the device if it was suspended.
2040 : * Beware, this function can fail.
2041 : *
2042 : * Note we don't actually enable the device many times if we call
2043 : * this function repeatedly (we just increment the count).
2044 : */
2045 0 : int pci_enable_device(struct pci_dev *dev)
2046 : {
2047 0 : return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
2048 : }
2049 : EXPORT_SYMBOL(pci_enable_device);
2050 :
2051 : /*
2052 : * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2053 : * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2054 : * there's no need to track it separately. pci_devres is initialized
2055 : * when a device is enabled using managed PCI device enable interface.
2056 : */
2057 : struct pci_devres {
2058 : unsigned int enabled:1;
2059 : unsigned int pinned:1;
2060 : unsigned int orig_intx:1;
2061 : unsigned int restore_intx:1;
2062 : unsigned int mwi:1;
2063 : u32 region_mask;
2064 : };
2065 :
2066 0 : static void pcim_release(struct device *gendev, void *res)
2067 : {
2068 0 : struct pci_dev *dev = to_pci_dev(gendev);
2069 0 : struct pci_devres *this = res;
2070 : int i;
2071 :
2072 0 : for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2073 0 : if (this->region_mask & (1 << i))
2074 0 : pci_release_region(dev, i);
2075 :
2076 0 : if (this->mwi)
2077 0 : pci_clear_mwi(dev);
2078 :
2079 0 : if (this->restore_intx)
2080 0 : pci_intx(dev, this->orig_intx);
2081 :
2082 0 : if (this->enabled && !this->pinned)
2083 0 : pci_disable_device(dev);
2084 0 : }
2085 :
2086 0 : static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2087 : {
2088 : struct pci_devres *dr, *new_dr;
2089 :
2090 0 : dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2091 0 : if (dr)
2092 : return dr;
2093 :
2094 0 : new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2095 0 : if (!new_dr)
2096 : return NULL;
2097 0 : return devres_get(&pdev->dev, new_dr, NULL, NULL);
2098 : }
2099 :
2100 : static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2101 : {
2102 0 : if (pci_is_managed(pdev))
2103 0 : return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2104 : return NULL;
2105 : }
2106 :
2107 : /**
2108 : * pcim_enable_device - Managed pci_enable_device()
2109 : * @pdev: PCI device to be initialized
2110 : *
2111 : * Managed pci_enable_device().
2112 : */
2113 0 : int pcim_enable_device(struct pci_dev *pdev)
2114 : {
2115 : struct pci_devres *dr;
2116 : int rc;
2117 :
2118 0 : dr = get_pci_dr(pdev);
2119 0 : if (unlikely(!dr))
2120 : return -ENOMEM;
2121 0 : if (dr->enabled)
2122 : return 0;
2123 :
2124 0 : rc = pci_enable_device(pdev);
2125 0 : if (!rc) {
2126 0 : pdev->is_managed = 1;
2127 0 : dr->enabled = 1;
2128 : }
2129 : return rc;
2130 : }
2131 : EXPORT_SYMBOL(pcim_enable_device);
2132 :
2133 : /**
2134 : * pcim_pin_device - Pin managed PCI device
2135 : * @pdev: PCI device to pin
2136 : *
2137 : * Pin managed PCI device @pdev. Pinned device won't be disabled on
2138 : * driver detach. @pdev must have been enabled with
2139 : * pcim_enable_device().
2140 : */
2141 0 : void pcim_pin_device(struct pci_dev *pdev)
2142 : {
2143 : struct pci_devres *dr;
2144 :
2145 0 : dr = find_pci_dr(pdev);
2146 0 : WARN_ON(!dr || !dr->enabled);
2147 0 : if (dr)
2148 0 : dr->pinned = 1;
2149 0 : }
2150 : EXPORT_SYMBOL(pcim_pin_device);
2151 :
2152 : /*
2153 : * pcibios_device_add - provide arch specific hooks when adding device dev
2154 : * @dev: the PCI device being added
2155 : *
2156 : * Permits the platform to provide architecture specific functionality when
2157 : * devices are added. This is the default implementation. Architecture
2158 : * implementations can override this.
2159 : */
2160 0 : int __weak pcibios_device_add(struct pci_dev *dev)
2161 : {
2162 0 : return 0;
2163 : }
2164 :
2165 : /**
2166 : * pcibios_release_device - provide arch specific hooks when releasing
2167 : * device dev
2168 : * @dev: the PCI device being released
2169 : *
2170 : * Permits the platform to provide architecture specific functionality when
2171 : * devices are released. This is the default implementation. Architecture
2172 : * implementations can override this.
2173 : */
2174 0 : void __weak pcibios_release_device(struct pci_dev *dev) {}
2175 :
2176 : /**
2177 : * pcibios_disable_device - disable arch specific PCI resources for device dev
2178 : * @dev: the PCI device to disable
2179 : *
2180 : * Disables architecture specific PCI resources for the device. This
2181 : * is the default implementation. Architecture implementations can
2182 : * override this.
2183 : */
2184 0 : void __weak pcibios_disable_device(struct pci_dev *dev) {}
2185 :
2186 : /**
2187 : * pcibios_penalize_isa_irq - penalize an ISA IRQ
2188 : * @irq: ISA IRQ to penalize
2189 : * @active: IRQ active or not
2190 : *
2191 : * Permits the platform to provide architecture-specific functionality when
2192 : * penalizing ISA IRQs. This is the default implementation. Architecture
2193 : * implementations can override this.
2194 : */
2195 0 : void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2196 :
2197 0 : static void do_pci_disable_device(struct pci_dev *dev)
2198 : {
2199 : u16 pci_command;
2200 :
2201 0 : pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2202 0 : if (pci_command & PCI_COMMAND_MASTER) {
2203 0 : pci_command &= ~PCI_COMMAND_MASTER;
2204 0 : pci_write_config_word(dev, PCI_COMMAND, pci_command);
2205 : }
2206 :
2207 0 : pcibios_disable_device(dev);
2208 0 : }
2209 :
2210 : /**
2211 : * pci_disable_enabled_device - Disable device without updating enable_cnt
2212 : * @dev: PCI device to disable
2213 : *
2214 : * NOTE: This function is a backend of PCI power management routines and is
2215 : * not supposed to be called drivers.
2216 : */
2217 0 : void pci_disable_enabled_device(struct pci_dev *dev)
2218 : {
2219 0 : if (pci_is_enabled(dev))
2220 0 : do_pci_disable_device(dev);
2221 0 : }
2222 :
2223 : /**
2224 : * pci_disable_device - Disable PCI device after use
2225 : * @dev: PCI device to be disabled
2226 : *
2227 : * Signal to the system that the PCI device is not in use by the system
2228 : * anymore. This only involves disabling PCI bus-mastering, if active.
2229 : *
2230 : * Note we don't actually disable the device until all callers of
2231 : * pci_enable_device() have called pci_disable_device().
2232 : */
2233 0 : void pci_disable_device(struct pci_dev *dev)
2234 : {
2235 : struct pci_devres *dr;
2236 :
2237 0 : dr = find_pci_dr(dev);
2238 0 : if (dr)
2239 0 : dr->enabled = 0;
2240 :
2241 0 : dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2242 : "disabling already-disabled device");
2243 :
2244 0 : if (atomic_dec_return(&dev->enable_cnt) != 0)
2245 : return;
2246 :
2247 0 : do_pci_disable_device(dev);
2248 :
2249 0 : dev->is_busmaster = 0;
2250 : }
2251 : EXPORT_SYMBOL(pci_disable_device);
2252 :
2253 : /**
2254 : * pcibios_set_pcie_reset_state - set reset state for device dev
2255 : * @dev: the PCIe device reset
2256 : * @state: Reset state to enter into
2257 : *
2258 : * Set the PCIe reset state for the device. This is the default
2259 : * implementation. Architecture implementations can override this.
2260 : */
2261 0 : int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2262 : enum pcie_reset_state state)
2263 : {
2264 0 : return -EINVAL;
2265 : }
2266 :
2267 : /**
2268 : * pci_set_pcie_reset_state - set reset state for device dev
2269 : * @dev: the PCIe device reset
2270 : * @state: Reset state to enter into
2271 : *
2272 : * Sets the PCI reset state for the device.
2273 : */
2274 0 : int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2275 : {
2276 0 : return pcibios_set_pcie_reset_state(dev, state);
2277 : }
2278 : EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2279 :
2280 : #ifdef CONFIG_PCIEAER
2281 : void pcie_clear_device_status(struct pci_dev *dev)
2282 : {
2283 : u16 sta;
2284 :
2285 : pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2286 : pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2287 : }
2288 : #endif
2289 :
2290 : /**
2291 : * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2292 : * @dev: PCIe root port or event collector.
2293 : */
2294 0 : void pcie_clear_root_pme_status(struct pci_dev *dev)
2295 : {
2296 0 : pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2297 0 : }
2298 :
2299 : /**
2300 : * pci_check_pme_status - Check if given device has generated PME.
2301 : * @dev: Device to check.
2302 : *
2303 : * Check the PME status of the device and if set, clear it and clear PME enable
2304 : * (if set). Return 'true' if PME status and PME enable were both set or
2305 : * 'false' otherwise.
2306 : */
2307 0 : bool pci_check_pme_status(struct pci_dev *dev)
2308 : {
2309 : int pmcsr_pos;
2310 : u16 pmcsr;
2311 0 : bool ret = false;
2312 :
2313 0 : if (!dev->pm_cap)
2314 : return false;
2315 :
2316 0 : pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2317 0 : pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2318 0 : if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2319 : return false;
2320 :
2321 : /* Clear PME status. */
2322 0 : pmcsr |= PCI_PM_CTRL_PME_STATUS;
2323 0 : if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2324 : /* Disable PME to avoid interrupt flood. */
2325 0 : pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2326 0 : ret = true;
2327 : }
2328 :
2329 0 : pci_write_config_word(dev, pmcsr_pos, pmcsr);
2330 :
2331 0 : return ret;
2332 : }
2333 :
2334 : /**
2335 : * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2336 : * @dev: Device to handle.
2337 : * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2338 : *
2339 : * Check if @dev has generated PME and queue a resume request for it in that
2340 : * case.
2341 : */
2342 0 : static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2343 : {
2344 0 : if (pme_poll_reset && dev->pme_poll)
2345 0 : dev->pme_poll = false;
2346 :
2347 0 : if (pci_check_pme_status(dev)) {
2348 0 : pci_wakeup_event(dev);
2349 0 : pm_request_resume(&dev->dev);
2350 : }
2351 0 : return 0;
2352 : }
2353 :
2354 : /**
2355 : * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2356 : * @bus: Top bus of the subtree to walk.
2357 : */
2358 0 : void pci_pme_wakeup_bus(struct pci_bus *bus)
2359 : {
2360 0 : if (bus)
2361 0 : pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2362 0 : }
2363 :
2364 :
2365 : /**
2366 : * pci_pme_capable - check the capability of PCI device to generate PME#
2367 : * @dev: PCI device to handle.
2368 : * @state: PCI state from which device will issue PME#.
2369 : */
2370 0 : bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2371 : {
2372 0 : if (!dev->pm_cap)
2373 : return false;
2374 :
2375 0 : return !!(dev->pme_support & (1 << state));
2376 : }
2377 : EXPORT_SYMBOL(pci_pme_capable);
2378 :
2379 0 : static void pci_pme_list_scan(struct work_struct *work)
2380 : {
2381 : struct pci_pme_device *pme_dev, *n;
2382 :
2383 0 : mutex_lock(&pci_pme_list_mutex);
2384 0 : list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2385 0 : if (pme_dev->dev->pme_poll) {
2386 : struct pci_dev *bridge;
2387 :
2388 0 : bridge = pme_dev->dev->bus->self;
2389 : /*
2390 : * If bridge is in low power state, the
2391 : * configuration space of subordinate devices
2392 : * may be not accessible
2393 : */
2394 0 : if (bridge && bridge->current_state != PCI_D0)
2395 0 : continue;
2396 : /*
2397 : * If the device is in D3cold it should not be
2398 : * polled either.
2399 : */
2400 0 : if (pme_dev->dev->current_state == PCI_D3cold)
2401 0 : continue;
2402 :
2403 0 : pci_pme_wakeup(pme_dev->dev, NULL);
2404 : } else {
2405 0 : list_del(&pme_dev->list);
2406 0 : kfree(pme_dev);
2407 : }
2408 : }
2409 0 : if (!list_empty(&pci_pme_list))
2410 0 : queue_delayed_work(system_freezable_wq, &pci_pme_work,
2411 : msecs_to_jiffies(PME_TIMEOUT));
2412 0 : mutex_unlock(&pci_pme_list_mutex);
2413 0 : }
2414 :
2415 0 : static void __pci_pme_active(struct pci_dev *dev, bool enable)
2416 : {
2417 : u16 pmcsr;
2418 :
2419 0 : if (!dev->pme_support)
2420 0 : return;
2421 :
2422 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2423 : /* Clear PME_Status by writing 1 to it and enable PME# */
2424 0 : pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2425 0 : if (!enable)
2426 0 : pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2427 :
2428 0 : pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2429 : }
2430 :
2431 : /**
2432 : * pci_pme_restore - Restore PME configuration after config space restore.
2433 : * @dev: PCI device to update.
2434 : */
2435 0 : void pci_pme_restore(struct pci_dev *dev)
2436 : {
2437 : u16 pmcsr;
2438 :
2439 0 : if (!dev->pme_support)
2440 0 : return;
2441 :
2442 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2443 0 : if (dev->wakeup_prepared) {
2444 0 : pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2445 0 : pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2446 : } else {
2447 0 : pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2448 0 : pmcsr |= PCI_PM_CTRL_PME_STATUS;
2449 : }
2450 0 : pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2451 : }
2452 :
2453 : /**
2454 : * pci_pme_active - enable or disable PCI device's PME# function
2455 : * @dev: PCI device to handle.
2456 : * @enable: 'true' to enable PME# generation; 'false' to disable it.
2457 : *
2458 : * The caller must verify that the device is capable of generating PME# before
2459 : * calling this function with @enable equal to 'true'.
2460 : */
2461 0 : void pci_pme_active(struct pci_dev *dev, bool enable)
2462 : {
2463 0 : __pci_pme_active(dev, enable);
2464 :
2465 : /*
2466 : * PCI (as opposed to PCIe) PME requires that the device have
2467 : * its PME# line hooked up correctly. Not all hardware vendors
2468 : * do this, so the PME never gets delivered and the device
2469 : * remains asleep. The easiest way around this is to
2470 : * periodically walk the list of suspended devices and check
2471 : * whether any have their PME flag set. The assumption is that
2472 : * we'll wake up often enough anyway that this won't be a huge
2473 : * hit, and the power savings from the devices will still be a
2474 : * win.
2475 : *
2476 : * Although PCIe uses in-band PME message instead of PME# line
2477 : * to report PME, PME does not work for some PCIe devices in
2478 : * reality. For example, there are devices that set their PME
2479 : * status bits, but don't really bother to send a PME message;
2480 : * there are PCI Express Root Ports that don't bother to
2481 : * trigger interrupts when they receive PME messages from the
2482 : * devices below. So PME poll is used for PCIe devices too.
2483 : */
2484 :
2485 0 : if (dev->pme_poll) {
2486 : struct pci_pme_device *pme_dev;
2487 0 : if (enable) {
2488 0 : pme_dev = kmalloc(sizeof(struct pci_pme_device),
2489 : GFP_KERNEL);
2490 0 : if (!pme_dev) {
2491 0 : pci_warn(dev, "can't enable PME#\n");
2492 0 : return;
2493 : }
2494 0 : pme_dev->dev = dev;
2495 0 : mutex_lock(&pci_pme_list_mutex);
2496 0 : list_add(&pme_dev->list, &pci_pme_list);
2497 0 : if (list_is_singular(&pci_pme_list))
2498 0 : queue_delayed_work(system_freezable_wq,
2499 : &pci_pme_work,
2500 : msecs_to_jiffies(PME_TIMEOUT));
2501 0 : mutex_unlock(&pci_pme_list_mutex);
2502 : } else {
2503 0 : mutex_lock(&pci_pme_list_mutex);
2504 0 : list_for_each_entry(pme_dev, &pci_pme_list, list) {
2505 0 : if (pme_dev->dev == dev) {
2506 0 : list_del(&pme_dev->list);
2507 0 : kfree(pme_dev);
2508 0 : break;
2509 : }
2510 : }
2511 0 : mutex_unlock(&pci_pme_list_mutex);
2512 : }
2513 : }
2514 :
2515 : pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2516 : }
2517 : EXPORT_SYMBOL(pci_pme_active);
2518 :
2519 : /**
2520 : * __pci_enable_wake - enable PCI device as wakeup event source
2521 : * @dev: PCI device affected
2522 : * @state: PCI state from which device will issue wakeup events
2523 : * @enable: True to enable event generation; false to disable
2524 : *
2525 : * This enables the device as a wakeup event source, or disables it.
2526 : * When such events involves platform-specific hooks, those hooks are
2527 : * called automatically by this routine.
2528 : *
2529 : * Devices with legacy power management (no standard PCI PM capabilities)
2530 : * always require such platform hooks.
2531 : *
2532 : * RETURN VALUE:
2533 : * 0 is returned on success
2534 : * -EINVAL is returned if device is not supposed to wake up the system
2535 : * Error code depending on the platform is returned if both the platform and
2536 : * the native mechanism fail to enable the generation of wake-up events
2537 : */
2538 0 : static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2539 : {
2540 0 : int ret = 0;
2541 :
2542 : /*
2543 : * Bridges that are not power-manageable directly only signal
2544 : * wakeup on behalf of subordinate devices which is set up
2545 : * elsewhere, so skip them. However, bridges that are
2546 : * power-manageable may signal wakeup for themselves (for example,
2547 : * on a hotplug event) and they need to be covered here.
2548 : */
2549 0 : if (!pci_power_manageable(dev))
2550 : return 0;
2551 :
2552 : /* Don't do the same thing twice in a row for one device. */
2553 0 : if (!!enable == !!dev->wakeup_prepared)
2554 : return 0;
2555 :
2556 : /*
2557 : * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2558 : * Anderson we should be doing PME# wake enable followed by ACPI wake
2559 : * enable. To disable wake-up we call the platform first, for symmetry.
2560 : */
2561 :
2562 0 : if (enable) {
2563 : int error;
2564 :
2565 : /*
2566 : * Enable PME signaling if the device can signal PME from
2567 : * D3cold regardless of whether or not it can signal PME from
2568 : * the current target state, because that will allow it to
2569 : * signal PME when the hierarchy above it goes into D3cold and
2570 : * the device itself ends up in D3cold as a result of that.
2571 : */
2572 0 : if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2573 0 : pci_pme_active(dev, true);
2574 : else
2575 : ret = 1;
2576 0 : error = platform_pci_set_wakeup(dev, true);
2577 0 : if (ret)
2578 0 : ret = error;
2579 0 : if (!ret)
2580 0 : dev->wakeup_prepared = true;
2581 : } else {
2582 0 : platform_pci_set_wakeup(dev, false);
2583 0 : pci_pme_active(dev, false);
2584 0 : dev->wakeup_prepared = false;
2585 : }
2586 :
2587 : return ret;
2588 : }
2589 :
2590 : /**
2591 : * pci_enable_wake - change wakeup settings for a PCI device
2592 : * @pci_dev: Target device
2593 : * @state: PCI state from which device will issue wakeup events
2594 : * @enable: Whether or not to enable event generation
2595 : *
2596 : * If @enable is set, check device_may_wakeup() for the device before calling
2597 : * __pci_enable_wake() for it.
2598 : */
2599 0 : int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2600 : {
2601 0 : if (enable && !device_may_wakeup(&pci_dev->dev))
2602 : return -EINVAL;
2603 :
2604 0 : return __pci_enable_wake(pci_dev, state, enable);
2605 : }
2606 : EXPORT_SYMBOL(pci_enable_wake);
2607 :
2608 : /**
2609 : * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2610 : * @dev: PCI device to prepare
2611 : * @enable: True to enable wake-up event generation; false to disable
2612 : *
2613 : * Many drivers want the device to wake up the system from D3_hot or D3_cold
2614 : * and this function allows them to set that up cleanly - pci_enable_wake()
2615 : * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2616 : * ordering constraints.
2617 : *
2618 : * This function only returns error code if the device is not allowed to wake
2619 : * up the system from sleep or it is not capable of generating PME# from both
2620 : * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2621 : */
2622 0 : int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2623 : {
2624 0 : return pci_pme_capable(dev, PCI_D3cold) ?
2625 0 : pci_enable_wake(dev, PCI_D3cold, enable) :
2626 0 : pci_enable_wake(dev, PCI_D3hot, enable);
2627 : }
2628 : EXPORT_SYMBOL(pci_wake_from_d3);
2629 :
2630 : /**
2631 : * pci_target_state - find an appropriate low power state for a given PCI dev
2632 : * @dev: PCI device
2633 : * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2634 : *
2635 : * Use underlying platform code to find a supported low power state for @dev.
2636 : * If the platform can't manage @dev, return the deepest state from which it
2637 : * can generate wake events, based on any available PME info.
2638 : */
2639 0 : static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2640 : {
2641 0 : if (platform_pci_power_manageable(dev)) {
2642 : /*
2643 : * Call the platform to find the target state for the device.
2644 : */
2645 : pci_power_t state = platform_pci_choose_state(dev);
2646 :
2647 : switch (state) {
2648 : case PCI_POWER_ERROR:
2649 : case PCI_UNKNOWN:
2650 : return PCI_D3hot;
2651 :
2652 : case PCI_D1:
2653 : case PCI_D2:
2654 : if (pci_no_d1d2(dev))
2655 : return PCI_D3hot;
2656 : }
2657 :
2658 : return state;
2659 : }
2660 :
2661 : /*
2662 : * If the device is in D3cold even though it's not power-manageable by
2663 : * the platform, it may have been powered down by non-standard means.
2664 : * Best to let it slumber.
2665 : */
2666 0 : if (dev->current_state == PCI_D3cold)
2667 : return PCI_D3cold;
2668 0 : else if (!dev->pm_cap)
2669 : return PCI_D0;
2670 :
2671 0 : if (wakeup && dev->pme_support) {
2672 : pci_power_t state = PCI_D3hot;
2673 :
2674 : /*
2675 : * Find the deepest state from which the device can generate
2676 : * PME#.
2677 : */
2678 0 : while (state && !(dev->pme_support & (1 << state)))
2679 0 : state--;
2680 :
2681 0 : if (state)
2682 : return state;
2683 0 : else if (dev->pme_support & 1)
2684 : return PCI_D0;
2685 : }
2686 :
2687 0 : return PCI_D3hot;
2688 : }
2689 :
2690 : /**
2691 : * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2692 : * into a sleep state
2693 : * @dev: Device to handle.
2694 : *
2695 : * Choose the power state appropriate for the device depending on whether
2696 : * it can wake up the system and/or is power manageable by the platform
2697 : * (PCI_D3hot is the default) and put the device into that state.
2698 : */
2699 0 : int pci_prepare_to_sleep(struct pci_dev *dev)
2700 : {
2701 0 : bool wakeup = device_may_wakeup(&dev->dev);
2702 0 : pci_power_t target_state = pci_target_state(dev, wakeup);
2703 : int error;
2704 :
2705 0 : if (target_state == PCI_POWER_ERROR)
2706 : return -EIO;
2707 :
2708 0 : pci_enable_wake(dev, target_state, wakeup);
2709 :
2710 0 : error = pci_set_power_state(dev, target_state);
2711 :
2712 0 : if (error)
2713 0 : pci_enable_wake(dev, target_state, false);
2714 :
2715 : return error;
2716 : }
2717 : EXPORT_SYMBOL(pci_prepare_to_sleep);
2718 :
2719 : /**
2720 : * pci_back_from_sleep - turn PCI device on during system-wide transition
2721 : * into working state
2722 : * @dev: Device to handle.
2723 : *
2724 : * Disable device's system wake-up capability and put it into D0.
2725 : */
2726 0 : int pci_back_from_sleep(struct pci_dev *dev)
2727 : {
2728 0 : int ret = pci_set_power_state(dev, PCI_D0);
2729 :
2730 0 : if (ret)
2731 : return ret;
2732 :
2733 0 : pci_enable_wake(dev, PCI_D0, false);
2734 0 : return 0;
2735 : }
2736 : EXPORT_SYMBOL(pci_back_from_sleep);
2737 :
2738 : /**
2739 : * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2740 : * @dev: PCI device being suspended.
2741 : *
2742 : * Prepare @dev to generate wake-up events at run time and put it into a low
2743 : * power state.
2744 : */
2745 0 : int pci_finish_runtime_suspend(struct pci_dev *dev)
2746 : {
2747 : pci_power_t target_state;
2748 : int error;
2749 :
2750 0 : target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2751 0 : if (target_state == PCI_POWER_ERROR)
2752 : return -EIO;
2753 :
2754 0 : __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2755 :
2756 0 : error = pci_set_power_state(dev, target_state);
2757 :
2758 0 : if (error)
2759 0 : pci_enable_wake(dev, target_state, false);
2760 :
2761 : return error;
2762 : }
2763 :
2764 : /**
2765 : * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2766 : * @dev: Device to check.
2767 : *
2768 : * Return true if the device itself is capable of generating wake-up events
2769 : * (through the platform or using the native PCIe PME) or if the device supports
2770 : * PME and one of its upstream bridges can generate wake-up events.
2771 : */
2772 0 : bool pci_dev_run_wake(struct pci_dev *dev)
2773 : {
2774 0 : struct pci_bus *bus = dev->bus;
2775 :
2776 0 : if (!dev->pme_support)
2777 : return false;
2778 :
2779 : /* PME-capable in principle, but not from the target power state */
2780 0 : if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2781 : return false;
2782 :
2783 0 : if (device_can_wakeup(&dev->dev))
2784 : return true;
2785 :
2786 0 : while (bus->parent) {
2787 0 : struct pci_dev *bridge = bus->self;
2788 :
2789 0 : if (device_can_wakeup(&bridge->dev))
2790 : return true;
2791 :
2792 : bus = bus->parent;
2793 : }
2794 :
2795 : /* We have reached the root bus. */
2796 0 : if (bus->bridge)
2797 0 : return device_can_wakeup(bus->bridge);
2798 :
2799 : return false;
2800 : }
2801 : EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2802 :
2803 : /**
2804 : * pci_dev_need_resume - Check if it is necessary to resume the device.
2805 : * @pci_dev: Device to check.
2806 : *
2807 : * Return 'true' if the device is not runtime-suspended or it has to be
2808 : * reconfigured due to wakeup settings difference between system and runtime
2809 : * suspend, or the current power state of it is not suitable for the upcoming
2810 : * (system-wide) transition.
2811 : */
2812 0 : bool pci_dev_need_resume(struct pci_dev *pci_dev)
2813 : {
2814 0 : struct device *dev = &pci_dev->dev;
2815 : pci_power_t target_state;
2816 :
2817 0 : if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2818 : return true;
2819 :
2820 0 : target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2821 :
2822 : /*
2823 : * If the earlier platform check has not triggered, D3cold is just power
2824 : * removal on top of D3hot, so no need to resume the device in that
2825 : * case.
2826 : */
2827 0 : return target_state != pci_dev->current_state &&
2828 0 : target_state != PCI_D3cold &&
2829 : pci_dev->current_state != PCI_D3hot;
2830 : }
2831 :
2832 : /**
2833 : * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2834 : * @pci_dev: Device to check.
2835 : *
2836 : * If the device is suspended and it is not configured for system wakeup,
2837 : * disable PME for it to prevent it from waking up the system unnecessarily.
2838 : *
2839 : * Note that if the device's power state is D3cold and the platform check in
2840 : * pci_dev_need_resume() has not triggered, the device's configuration need not
2841 : * be changed.
2842 : */
2843 0 : void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2844 : {
2845 0 : struct device *dev = &pci_dev->dev;
2846 :
2847 0 : spin_lock_irq(&dev->power.lock);
2848 :
2849 0 : if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2850 0 : pci_dev->current_state < PCI_D3cold)
2851 0 : __pci_pme_active(pci_dev, false);
2852 :
2853 0 : spin_unlock_irq(&dev->power.lock);
2854 0 : }
2855 :
2856 : /**
2857 : * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2858 : * @pci_dev: Device to handle.
2859 : *
2860 : * If the device is runtime suspended and wakeup-capable, enable PME for it as
2861 : * it might have been disabled during the prepare phase of system suspend if
2862 : * the device was not configured for system wakeup.
2863 : */
2864 0 : void pci_dev_complete_resume(struct pci_dev *pci_dev)
2865 : {
2866 0 : struct device *dev = &pci_dev->dev;
2867 :
2868 0 : if (!pci_dev_run_wake(pci_dev))
2869 : return;
2870 :
2871 0 : spin_lock_irq(&dev->power.lock);
2872 :
2873 0 : if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2874 0 : __pci_pme_active(pci_dev, true);
2875 :
2876 0 : spin_unlock_irq(&dev->power.lock);
2877 : }
2878 :
2879 : /**
2880 : * pci_choose_state - Choose the power state of a PCI device.
2881 : * @dev: Target PCI device.
2882 : * @state: Target state for the whole system.
2883 : *
2884 : * Returns PCI power state suitable for @dev and @state.
2885 : */
2886 0 : pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
2887 : {
2888 0 : if (state.event == PM_EVENT_ON)
2889 : return PCI_D0;
2890 :
2891 0 : return pci_target_state(dev, false);
2892 : }
2893 : EXPORT_SYMBOL(pci_choose_state);
2894 :
2895 0 : void pci_config_pm_runtime_get(struct pci_dev *pdev)
2896 : {
2897 0 : struct device *dev = &pdev->dev;
2898 0 : struct device *parent = dev->parent;
2899 :
2900 0 : if (parent)
2901 : pm_runtime_get_sync(parent);
2902 0 : pm_runtime_get_noresume(dev);
2903 : /*
2904 : * pdev->current_state is set to PCI_D3cold during suspending,
2905 : * so wait until suspending completes
2906 : */
2907 0 : pm_runtime_barrier(dev);
2908 : /*
2909 : * Only need to resume devices in D3cold, because config
2910 : * registers are still accessible for devices suspended but
2911 : * not in D3cold.
2912 : */
2913 0 : if (pdev->current_state == PCI_D3cold)
2914 : pm_runtime_resume(dev);
2915 0 : }
2916 :
2917 0 : void pci_config_pm_runtime_put(struct pci_dev *pdev)
2918 : {
2919 0 : struct device *dev = &pdev->dev;
2920 0 : struct device *parent = dev->parent;
2921 :
2922 0 : pm_runtime_put(dev);
2923 0 : if (parent)
2924 : pm_runtime_put_sync(parent);
2925 0 : }
2926 :
2927 : static const struct dmi_system_id bridge_d3_blacklist[] = {
2928 : #ifdef CONFIG_X86
2929 : {
2930 : /*
2931 : * Gigabyte X299 root port is not marked as hotplug capable
2932 : * which allows Linux to power manage it. However, this
2933 : * confuses the BIOS SMI handler so don't power manage root
2934 : * ports on that system.
2935 : */
2936 : .ident = "X299 DESIGNARE EX-CF",
2937 : .matches = {
2938 : DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2939 : DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2940 : },
2941 : },
2942 : {
2943 : /*
2944 : * Downstream device is not accessible after putting a root port
2945 : * into D3cold and back into D0 on Elo i2.
2946 : */
2947 : .ident = "Elo i2",
2948 : .matches = {
2949 : DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"),
2950 : DMI_MATCH(DMI_PRODUCT_NAME, "Elo i2"),
2951 : DMI_MATCH(DMI_PRODUCT_VERSION, "RevB"),
2952 : },
2953 : },
2954 : #endif
2955 : { }
2956 : };
2957 :
2958 : /**
2959 : * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2960 : * @bridge: Bridge to check
2961 : *
2962 : * This function checks if it is possible to move the bridge to D3.
2963 : * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2964 : */
2965 0 : bool pci_bridge_d3_possible(struct pci_dev *bridge)
2966 : {
2967 0 : if (!pci_is_pcie(bridge))
2968 : return false;
2969 :
2970 0 : switch (pci_pcie_type(bridge)) {
2971 : case PCI_EXP_TYPE_ROOT_PORT:
2972 : case PCI_EXP_TYPE_UPSTREAM:
2973 : case PCI_EXP_TYPE_DOWNSTREAM:
2974 0 : if (pci_bridge_d3_disable)
2975 : return false;
2976 :
2977 : /*
2978 : * Hotplug ports handled by firmware in System Management Mode
2979 : * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2980 : */
2981 0 : if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2982 : return false;
2983 :
2984 0 : if (pci_bridge_d3_force)
2985 : return true;
2986 :
2987 : /* Even the oldest 2010 Thunderbolt controller supports D3. */
2988 0 : if (bridge->is_thunderbolt)
2989 : return true;
2990 :
2991 : /* Platform might know better if the bridge supports D3 */
2992 0 : if (platform_pci_bridge_d3(bridge))
2993 : return true;
2994 :
2995 : /*
2996 : * Hotplug ports handled natively by the OS were not validated
2997 : * by vendors for runtime D3 at least until 2018 because there
2998 : * was no OS support.
2999 : */
3000 : if (bridge->is_hotplug_bridge)
3001 : return false;
3002 :
3003 : if (dmi_check_system(bridge_d3_blacklist))
3004 : return false;
3005 :
3006 : /*
3007 : * It should be safe to put PCIe ports from 2015 or newer
3008 : * to D3.
3009 : */
3010 : if (dmi_get_bios_year() >= 2015)
3011 : return true;
3012 : break;
3013 : }
3014 :
3015 : return false;
3016 : }
3017 :
3018 0 : static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
3019 : {
3020 0 : bool *d3cold_ok = data;
3021 :
3022 0 : if (/* The device needs to be allowed to go D3cold ... */
3023 0 : dev->no_d3cold || !dev->d3cold_allowed ||
3024 :
3025 : /* ... and if it is wakeup capable to do so from D3cold. */
3026 0 : (device_may_wakeup(&dev->dev) &&
3027 0 : !pci_pme_capable(dev, PCI_D3cold)) ||
3028 :
3029 : /* If it is a bridge it must be allowed to go to D3. */
3030 0 : !pci_power_manageable(dev))
3031 :
3032 0 : *d3cold_ok = false;
3033 :
3034 0 : return !*d3cold_ok;
3035 : }
3036 :
3037 : /*
3038 : * pci_bridge_d3_update - Update bridge D3 capabilities
3039 : * @dev: PCI device which is changed
3040 : *
3041 : * Update upstream bridge PM capabilities accordingly depending on if the
3042 : * device PM configuration was changed or the device is being removed. The
3043 : * change is also propagated upstream.
3044 : */
3045 0 : void pci_bridge_d3_update(struct pci_dev *dev)
3046 : {
3047 0 : bool remove = !device_is_registered(&dev->dev);
3048 : struct pci_dev *bridge;
3049 0 : bool d3cold_ok = true;
3050 :
3051 0 : bridge = pci_upstream_bridge(dev);
3052 0 : if (!bridge || !pci_bridge_d3_possible(bridge))
3053 0 : return;
3054 :
3055 : /*
3056 : * If D3 is currently allowed for the bridge, removing one of its
3057 : * children won't change that.
3058 : */
3059 0 : if (remove && bridge->bridge_d3)
3060 : return;
3061 :
3062 : /*
3063 : * If D3 is currently allowed for the bridge and a child is added or
3064 : * changed, disallowance of D3 can only be caused by that child, so
3065 : * we only need to check that single device, not any of its siblings.
3066 : *
3067 : * If D3 is currently not allowed for the bridge, checking the device
3068 : * first may allow us to skip checking its siblings.
3069 : */
3070 0 : if (!remove)
3071 0 : pci_dev_check_d3cold(dev, &d3cold_ok);
3072 :
3073 : /*
3074 : * If D3 is currently not allowed for the bridge, this may be caused
3075 : * either by the device being changed/removed or any of its siblings,
3076 : * so we need to go through all children to find out if one of them
3077 : * continues to block D3.
3078 : */
3079 0 : if (d3cold_ok && !bridge->bridge_d3)
3080 0 : pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3081 : &d3cold_ok);
3082 :
3083 0 : if (bridge->bridge_d3 != d3cold_ok) {
3084 0 : bridge->bridge_d3 = d3cold_ok;
3085 : /* Propagate change to upstream bridges */
3086 0 : pci_bridge_d3_update(bridge);
3087 : }
3088 : }
3089 :
3090 : /**
3091 : * pci_d3cold_enable - Enable D3cold for device
3092 : * @dev: PCI device to handle
3093 : *
3094 : * This function can be used in drivers to enable D3cold from the device
3095 : * they handle. It also updates upstream PCI bridge PM capabilities
3096 : * accordingly.
3097 : */
3098 0 : void pci_d3cold_enable(struct pci_dev *dev)
3099 : {
3100 0 : if (dev->no_d3cold) {
3101 0 : dev->no_d3cold = false;
3102 0 : pci_bridge_d3_update(dev);
3103 : }
3104 0 : }
3105 : EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3106 :
3107 : /**
3108 : * pci_d3cold_disable - Disable D3cold for device
3109 : * @dev: PCI device to handle
3110 : *
3111 : * This function can be used in drivers to disable D3cold from the device
3112 : * they handle. It also updates upstream PCI bridge PM capabilities
3113 : * accordingly.
3114 : */
3115 0 : void pci_d3cold_disable(struct pci_dev *dev)
3116 : {
3117 0 : if (!dev->no_d3cold) {
3118 0 : dev->no_d3cold = true;
3119 0 : pci_bridge_d3_update(dev);
3120 : }
3121 0 : }
3122 : EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3123 :
3124 : /**
3125 : * pci_pm_init - Initialize PM functions of given PCI device
3126 : * @dev: PCI device to handle.
3127 : */
3128 0 : void pci_pm_init(struct pci_dev *dev)
3129 : {
3130 : int pm;
3131 : u16 status;
3132 : u16 pmc;
3133 :
3134 0 : pm_runtime_forbid(&dev->dev);
3135 0 : pm_runtime_set_active(&dev->dev);
3136 0 : pm_runtime_enable(&dev->dev);
3137 0 : device_enable_async_suspend(&dev->dev);
3138 0 : dev->wakeup_prepared = false;
3139 :
3140 0 : dev->pm_cap = 0;
3141 0 : dev->pme_support = 0;
3142 :
3143 : /* find PCI PM capability in list */
3144 0 : pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3145 0 : if (!pm)
3146 0 : return;
3147 : /* Check device's ability to generate PME# */
3148 0 : pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3149 :
3150 0 : if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3151 0 : pci_err(dev, "unsupported PM cap regs version (%u)\n",
3152 : pmc & PCI_PM_CAP_VER_MASK);
3153 0 : return;
3154 : }
3155 :
3156 0 : dev->pm_cap = pm;
3157 0 : dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3158 0 : dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3159 0 : dev->bridge_d3 = pci_bridge_d3_possible(dev);
3160 0 : dev->d3cold_allowed = true;
3161 :
3162 0 : dev->d1_support = false;
3163 0 : dev->d2_support = false;
3164 0 : if (!pci_no_d1d2(dev)) {
3165 0 : if (pmc & PCI_PM_CAP_D1)
3166 0 : dev->d1_support = true;
3167 0 : if (pmc & PCI_PM_CAP_D2)
3168 0 : dev->d2_support = true;
3169 :
3170 0 : if (dev->d1_support || dev->d2_support)
3171 0 : pci_info(dev, "supports%s%s\n",
3172 : dev->d1_support ? " D1" : "",
3173 : dev->d2_support ? " D2" : "");
3174 : }
3175 :
3176 0 : pmc &= PCI_PM_CAP_PME_MASK;
3177 0 : if (pmc) {
3178 0 : pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3179 : (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3180 : (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3181 : (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3182 : (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3183 : (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3184 0 : dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3185 0 : dev->pme_poll = true;
3186 : /*
3187 : * Make device's PM flags reflect the wake-up capability, but
3188 : * let the user space enable it to wake up the system as needed.
3189 : */
3190 0 : device_set_wakeup_capable(&dev->dev, true);
3191 : /* Disable the PME# generation functionality */
3192 0 : pci_pme_active(dev, false);
3193 : }
3194 :
3195 0 : pci_read_config_word(dev, PCI_STATUS, &status);
3196 0 : if (status & PCI_STATUS_IMM_READY)
3197 0 : dev->imm_ready = 1;
3198 : }
3199 :
3200 : static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3201 : {
3202 0 : unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3203 :
3204 : switch (prop) {
3205 : case PCI_EA_P_MEM:
3206 : case PCI_EA_P_VF_MEM:
3207 : flags |= IORESOURCE_MEM;
3208 : break;
3209 : case PCI_EA_P_MEM_PREFETCH:
3210 : case PCI_EA_P_VF_MEM_PREFETCH:
3211 : flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3212 : break;
3213 : case PCI_EA_P_IO:
3214 : flags |= IORESOURCE_IO;
3215 : break;
3216 : default:
3217 : return 0;
3218 : }
3219 :
3220 : return flags;
3221 : }
3222 :
3223 : static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3224 : u8 prop)
3225 : {
3226 0 : if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3227 0 : return &dev->resource[bei];
3228 : #ifdef CONFIG_PCI_IOV
3229 : else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3230 : (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3231 : return &dev->resource[PCI_IOV_RESOURCES +
3232 : bei - PCI_EA_BEI_VF_BAR0];
3233 : #endif
3234 0 : else if (bei == PCI_EA_BEI_ROM)
3235 0 : return &dev->resource[PCI_ROM_RESOURCE];
3236 : else
3237 : return NULL;
3238 : }
3239 :
3240 : /* Read an Enhanced Allocation (EA) entry */
3241 0 : static int pci_ea_read(struct pci_dev *dev, int offset)
3242 : {
3243 : struct resource *res;
3244 0 : int ent_size, ent_offset = offset;
3245 : resource_size_t start, end;
3246 : unsigned long flags;
3247 : u32 dw0, bei, base, max_offset;
3248 : u8 prop;
3249 0 : bool support_64 = (sizeof(resource_size_t) >= 8);
3250 :
3251 0 : pci_read_config_dword(dev, ent_offset, &dw0);
3252 0 : ent_offset += 4;
3253 :
3254 : /* Entry size field indicates DWORDs after 1st */
3255 0 : ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3256 :
3257 0 : if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3258 : goto out;
3259 :
3260 0 : bei = (dw0 & PCI_EA_BEI) >> 4;
3261 0 : prop = (dw0 & PCI_EA_PP) >> 8;
3262 :
3263 : /*
3264 : * If the Property is in the reserved range, try the Secondary
3265 : * Property instead.
3266 : */
3267 0 : if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3268 0 : prop = (dw0 & PCI_EA_SP) >> 16;
3269 0 : if (prop > PCI_EA_P_BRIDGE_IO)
3270 : goto out;
3271 :
3272 0 : res = pci_ea_get_resource(dev, bei, prop);
3273 0 : if (!res) {
3274 0 : pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3275 0 : goto out;
3276 : }
3277 :
3278 0 : flags = pci_ea_flags(dev, prop);
3279 0 : if (!flags) {
3280 0 : pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3281 0 : goto out;
3282 : }
3283 :
3284 : /* Read Base */
3285 0 : pci_read_config_dword(dev, ent_offset, &base);
3286 0 : start = (base & PCI_EA_FIELD_MASK);
3287 0 : ent_offset += 4;
3288 :
3289 : /* Read MaxOffset */
3290 0 : pci_read_config_dword(dev, ent_offset, &max_offset);
3291 0 : ent_offset += 4;
3292 :
3293 : /* Read Base MSBs (if 64-bit entry) */
3294 0 : if (base & PCI_EA_IS_64) {
3295 : u32 base_upper;
3296 :
3297 0 : pci_read_config_dword(dev, ent_offset, &base_upper);
3298 0 : ent_offset += 4;
3299 :
3300 0 : flags |= IORESOURCE_MEM_64;
3301 :
3302 : /* entry starts above 32-bit boundary, can't use */
3303 : if (!support_64 && base_upper)
3304 : goto out;
3305 :
3306 : if (support_64)
3307 0 : start |= ((u64)base_upper << 32);
3308 : }
3309 :
3310 0 : end = start + (max_offset | 0x03);
3311 :
3312 : /* Read MaxOffset MSBs (if 64-bit entry) */
3313 0 : if (max_offset & PCI_EA_IS_64) {
3314 : u32 max_offset_upper;
3315 :
3316 0 : pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3317 0 : ent_offset += 4;
3318 :
3319 0 : flags |= IORESOURCE_MEM_64;
3320 :
3321 : /* entry too big, can't use */
3322 : if (!support_64 && max_offset_upper)
3323 : goto out;
3324 :
3325 : if (support_64)
3326 0 : end += ((u64)max_offset_upper << 32);
3327 : }
3328 :
3329 0 : if (end < start) {
3330 0 : pci_err(dev, "EA Entry crosses address boundary\n");
3331 0 : goto out;
3332 : }
3333 :
3334 0 : if (ent_size != ent_offset - offset) {
3335 0 : pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3336 : ent_size, ent_offset - offset);
3337 0 : goto out;
3338 : }
3339 :
3340 0 : res->name = pci_name(dev);
3341 0 : res->start = start;
3342 0 : res->end = end;
3343 0 : res->flags = flags;
3344 :
3345 0 : if (bei <= PCI_EA_BEI_BAR5)
3346 0 : pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3347 : bei, res, prop);
3348 0 : else if (bei == PCI_EA_BEI_ROM)
3349 0 : pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3350 : res, prop);
3351 0 : else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3352 0 : pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3353 : bei - PCI_EA_BEI_VF_BAR0, res, prop);
3354 : else
3355 0 : pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3356 : bei, res, prop);
3357 :
3358 : out:
3359 0 : return offset + ent_size;
3360 : }
3361 :
3362 : /* Enhanced Allocation Initialization */
3363 0 : void pci_ea_init(struct pci_dev *dev)
3364 : {
3365 : int ea;
3366 : u8 num_ent;
3367 : int offset;
3368 : int i;
3369 :
3370 : /* find PCI EA capability in list */
3371 0 : ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3372 0 : if (!ea)
3373 0 : return;
3374 :
3375 : /* determine the number of entries */
3376 0 : pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3377 : &num_ent);
3378 0 : num_ent &= PCI_EA_NUM_ENT_MASK;
3379 :
3380 0 : offset = ea + PCI_EA_FIRST_ENT;
3381 :
3382 : /* Skip DWORD 2 for type 1 functions */
3383 0 : if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3384 0 : offset += 4;
3385 :
3386 : /* parse each EA entry */
3387 0 : for (i = 0; i < num_ent; ++i)
3388 0 : offset = pci_ea_read(dev, offset);
3389 : }
3390 :
3391 : static void pci_add_saved_cap(struct pci_dev *pci_dev,
3392 : struct pci_cap_saved_state *new_cap)
3393 : {
3394 0 : hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3395 : }
3396 :
3397 : /**
3398 : * _pci_add_cap_save_buffer - allocate buffer for saving given
3399 : * capability registers
3400 : * @dev: the PCI device
3401 : * @cap: the capability to allocate the buffer for
3402 : * @extended: Standard or Extended capability ID
3403 : * @size: requested size of the buffer
3404 : */
3405 0 : static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3406 : bool extended, unsigned int size)
3407 : {
3408 : int pos;
3409 : struct pci_cap_saved_state *save_state;
3410 :
3411 0 : if (extended)
3412 0 : pos = pci_find_ext_capability(dev, cap);
3413 : else
3414 0 : pos = pci_find_capability(dev, cap);
3415 :
3416 0 : if (!pos)
3417 : return 0;
3418 :
3419 0 : save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3420 0 : if (!save_state)
3421 : return -ENOMEM;
3422 :
3423 0 : save_state->cap.cap_nr = cap;
3424 0 : save_state->cap.cap_extended = extended;
3425 0 : save_state->cap.size = size;
3426 0 : pci_add_saved_cap(dev, save_state);
3427 :
3428 0 : return 0;
3429 : }
3430 :
3431 0 : int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3432 : {
3433 0 : return _pci_add_cap_save_buffer(dev, cap, false, size);
3434 : }
3435 :
3436 0 : int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3437 : {
3438 0 : return _pci_add_cap_save_buffer(dev, cap, true, size);
3439 : }
3440 :
3441 : /**
3442 : * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3443 : * @dev: the PCI device
3444 : */
3445 0 : void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3446 : {
3447 : int error;
3448 :
3449 0 : error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3450 : PCI_EXP_SAVE_REGS * sizeof(u16));
3451 0 : if (error)
3452 0 : pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3453 :
3454 0 : error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3455 0 : if (error)
3456 0 : pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3457 :
3458 0 : error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3459 : 2 * sizeof(u16));
3460 0 : if (error)
3461 0 : pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3462 :
3463 0 : pci_allocate_vc_save_buffers(dev);
3464 0 : }
3465 :
3466 0 : void pci_free_cap_save_buffers(struct pci_dev *dev)
3467 : {
3468 : struct pci_cap_saved_state *tmp;
3469 : struct hlist_node *n;
3470 :
3471 0 : hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3472 0 : kfree(tmp);
3473 0 : }
3474 :
3475 : /**
3476 : * pci_configure_ari - enable or disable ARI forwarding
3477 : * @dev: the PCI device
3478 : *
3479 : * If @dev and its upstream bridge both support ARI, enable ARI in the
3480 : * bridge. Otherwise, disable ARI in the bridge.
3481 : */
3482 0 : void pci_configure_ari(struct pci_dev *dev)
3483 : {
3484 : u32 cap;
3485 : struct pci_dev *bridge;
3486 :
3487 0 : if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3488 0 : return;
3489 :
3490 0 : bridge = dev->bus->self;
3491 0 : if (!bridge)
3492 : return;
3493 :
3494 0 : pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3495 0 : if (!(cap & PCI_EXP_DEVCAP2_ARI))
3496 : return;
3497 :
3498 0 : if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3499 0 : pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3500 : PCI_EXP_DEVCTL2_ARI);
3501 0 : bridge->ari_enabled = 1;
3502 : } else {
3503 0 : pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3504 : PCI_EXP_DEVCTL2_ARI);
3505 0 : bridge->ari_enabled = 0;
3506 : }
3507 : }
3508 :
3509 0 : static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3510 : {
3511 : int pos;
3512 : u16 cap, ctrl;
3513 :
3514 0 : pos = pdev->acs_cap;
3515 0 : if (!pos)
3516 : return false;
3517 :
3518 : /*
3519 : * Except for egress control, capabilities are either required
3520 : * or only required if controllable. Features missing from the
3521 : * capability field can therefore be assumed as hard-wired enabled.
3522 : */
3523 0 : pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3524 0 : acs_flags &= (cap | PCI_ACS_EC);
3525 :
3526 0 : pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3527 0 : return (ctrl & acs_flags) == acs_flags;
3528 : }
3529 :
3530 : /**
3531 : * pci_acs_enabled - test ACS against required flags for a given device
3532 : * @pdev: device to test
3533 : * @acs_flags: required PCI ACS flags
3534 : *
3535 : * Return true if the device supports the provided flags. Automatically
3536 : * filters out flags that are not implemented on multifunction devices.
3537 : *
3538 : * Note that this interface checks the effective ACS capabilities of the
3539 : * device rather than the actual capabilities. For instance, most single
3540 : * function endpoints are not required to support ACS because they have no
3541 : * opportunity for peer-to-peer access. We therefore return 'true'
3542 : * regardless of whether the device exposes an ACS capability. This makes
3543 : * it much easier for callers of this function to ignore the actual type
3544 : * or topology of the device when testing ACS support.
3545 : */
3546 0 : bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3547 : {
3548 : int ret;
3549 :
3550 0 : ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3551 0 : if (ret >= 0)
3552 0 : return ret > 0;
3553 :
3554 : /*
3555 : * Conventional PCI and PCI-X devices never support ACS, either
3556 : * effectively or actually. The shared bus topology implies that
3557 : * any device on the bus can receive or snoop DMA.
3558 : */
3559 0 : if (!pci_is_pcie(pdev))
3560 : return false;
3561 :
3562 0 : switch (pci_pcie_type(pdev)) {
3563 : /*
3564 : * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3565 : * but since their primary interface is PCI/X, we conservatively
3566 : * handle them as we would a non-PCIe device.
3567 : */
3568 : case PCI_EXP_TYPE_PCIE_BRIDGE:
3569 : /*
3570 : * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3571 : * applicable... must never implement an ACS Extended Capability...".
3572 : * This seems arbitrary, but we take a conservative interpretation
3573 : * of this statement.
3574 : */
3575 : case PCI_EXP_TYPE_PCI_BRIDGE:
3576 : case PCI_EXP_TYPE_RC_EC:
3577 : return false;
3578 : /*
3579 : * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3580 : * implement ACS in order to indicate their peer-to-peer capabilities,
3581 : * regardless of whether they are single- or multi-function devices.
3582 : */
3583 : case PCI_EXP_TYPE_DOWNSTREAM:
3584 : case PCI_EXP_TYPE_ROOT_PORT:
3585 0 : return pci_acs_flags_enabled(pdev, acs_flags);
3586 : /*
3587 : * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3588 : * implemented by the remaining PCIe types to indicate peer-to-peer
3589 : * capabilities, but only when they are part of a multifunction
3590 : * device. The footnote for section 6.12 indicates the specific
3591 : * PCIe types included here.
3592 : */
3593 : case PCI_EXP_TYPE_ENDPOINT:
3594 : case PCI_EXP_TYPE_UPSTREAM:
3595 : case PCI_EXP_TYPE_LEG_END:
3596 : case PCI_EXP_TYPE_RC_END:
3597 0 : if (!pdev->multifunction)
3598 : break;
3599 :
3600 0 : return pci_acs_flags_enabled(pdev, acs_flags);
3601 : }
3602 :
3603 : /*
3604 : * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3605 : * to single function devices with the exception of downstream ports.
3606 : */
3607 0 : return true;
3608 : }
3609 :
3610 : /**
3611 : * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3612 : * @start: starting downstream device
3613 : * @end: ending upstream device or NULL to search to the root bus
3614 : * @acs_flags: required flags
3615 : *
3616 : * Walk up a device tree from start to end testing PCI ACS support. If
3617 : * any step along the way does not support the required flags, return false.
3618 : */
3619 0 : bool pci_acs_path_enabled(struct pci_dev *start,
3620 : struct pci_dev *end, u16 acs_flags)
3621 : {
3622 0 : struct pci_dev *pdev, *parent = start;
3623 :
3624 : do {
3625 0 : pdev = parent;
3626 :
3627 0 : if (!pci_acs_enabled(pdev, acs_flags))
3628 : return false;
3629 :
3630 0 : if (pci_is_root_bus(pdev->bus))
3631 0 : return (end == NULL);
3632 :
3633 0 : parent = pdev->bus->self;
3634 0 : } while (pdev != end);
3635 :
3636 : return true;
3637 : }
3638 :
3639 : /**
3640 : * pci_acs_init - Initialize ACS if hardware supports it
3641 : * @dev: the PCI device
3642 : */
3643 0 : void pci_acs_init(struct pci_dev *dev)
3644 : {
3645 0 : dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3646 :
3647 : /*
3648 : * Attempt to enable ACS regardless of capability because some Root
3649 : * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3650 : * the standard ACS capability but still support ACS via those
3651 : * quirks.
3652 : */
3653 0 : pci_enable_acs(dev);
3654 0 : }
3655 :
3656 : /**
3657 : * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3658 : * @pdev: PCI device
3659 : * @bar: BAR to find
3660 : *
3661 : * Helper to find the position of the ctrl register for a BAR.
3662 : * Returns -ENOTSUPP if resizable BARs are not supported at all.
3663 : * Returns -ENOENT if no ctrl register for the BAR could be found.
3664 : */
3665 0 : static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3666 : {
3667 : unsigned int pos, nbars, i;
3668 : u32 ctrl;
3669 :
3670 0 : pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3671 0 : if (!pos)
3672 : return -ENOTSUPP;
3673 :
3674 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3675 0 : nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3676 : PCI_REBAR_CTRL_NBAR_SHIFT;
3677 :
3678 0 : for (i = 0; i < nbars; i++, pos += 8) {
3679 : int bar_idx;
3680 :
3681 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3682 0 : bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3683 0 : if (bar_idx == bar)
3684 0 : return pos;
3685 : }
3686 :
3687 : return -ENOENT;
3688 : }
3689 :
3690 : /**
3691 : * pci_rebar_get_possible_sizes - get possible sizes for BAR
3692 : * @pdev: PCI device
3693 : * @bar: BAR to query
3694 : *
3695 : * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3696 : * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3697 : */
3698 0 : u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3699 : {
3700 : int pos;
3701 : u32 cap;
3702 :
3703 0 : pos = pci_rebar_find_pos(pdev, bar);
3704 0 : if (pos < 0)
3705 : return 0;
3706 :
3707 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3708 0 : cap &= PCI_REBAR_CAP_SIZES;
3709 :
3710 : /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3711 0 : if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3712 0 : bar == 0 && cap == 0x7000)
3713 0 : cap = 0x3f000;
3714 :
3715 0 : return cap >> 4;
3716 : }
3717 : EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3718 :
3719 : /**
3720 : * pci_rebar_get_current_size - get the current size of a BAR
3721 : * @pdev: PCI device
3722 : * @bar: BAR to set size to
3723 : *
3724 : * Read the size of a BAR from the resizable BAR config.
3725 : * Returns size if found or negative error code.
3726 : */
3727 0 : int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3728 : {
3729 : int pos;
3730 : u32 ctrl;
3731 :
3732 0 : pos = pci_rebar_find_pos(pdev, bar);
3733 0 : if (pos < 0)
3734 : return pos;
3735 :
3736 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3737 0 : return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3738 : }
3739 :
3740 : /**
3741 : * pci_rebar_set_size - set a new size for a BAR
3742 : * @pdev: PCI device
3743 : * @bar: BAR to set size to
3744 : * @size: new size as defined in the spec (0=1MB, 19=512GB)
3745 : *
3746 : * Set the new size of a BAR as defined in the spec.
3747 : * Returns zero if resizing was successful, error code otherwise.
3748 : */
3749 0 : int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3750 : {
3751 : int pos;
3752 : u32 ctrl;
3753 :
3754 0 : pos = pci_rebar_find_pos(pdev, bar);
3755 0 : if (pos < 0)
3756 : return pos;
3757 :
3758 0 : pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3759 0 : ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3760 0 : ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3761 0 : pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3762 0 : return 0;
3763 : }
3764 :
3765 : /**
3766 : * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3767 : * @dev: the PCI device
3768 : * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3769 : * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3770 : * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3771 : * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3772 : *
3773 : * Return 0 if all upstream bridges support AtomicOp routing, egress
3774 : * blocking is disabled on all upstream ports, and the root port supports
3775 : * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3776 : * AtomicOp completion), or negative otherwise.
3777 : */
3778 0 : int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3779 : {
3780 0 : struct pci_bus *bus = dev->bus;
3781 : struct pci_dev *bridge;
3782 : u32 cap, ctl2;
3783 :
3784 : /*
3785 : * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3786 : * in Device Control 2 is reserved in VFs and the PF value applies
3787 : * to all associated VFs.
3788 : */
3789 0 : if (dev->is_virtfn)
3790 : return -EINVAL;
3791 :
3792 0 : if (!pci_is_pcie(dev))
3793 : return -EINVAL;
3794 :
3795 : /*
3796 : * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3797 : * AtomicOp requesters. For now, we only support endpoints as
3798 : * requesters and root ports as completers. No endpoints as
3799 : * completers, and no peer-to-peer.
3800 : */
3801 :
3802 0 : switch (pci_pcie_type(dev)) {
3803 : case PCI_EXP_TYPE_ENDPOINT:
3804 : case PCI_EXP_TYPE_LEG_END:
3805 : case PCI_EXP_TYPE_RC_END:
3806 : break;
3807 : default:
3808 : return -EINVAL;
3809 : }
3810 :
3811 0 : while (bus->parent) {
3812 0 : bridge = bus->self;
3813 :
3814 0 : pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3815 :
3816 0 : switch (pci_pcie_type(bridge)) {
3817 : /* Ensure switch ports support AtomicOp routing */
3818 : case PCI_EXP_TYPE_UPSTREAM:
3819 : case PCI_EXP_TYPE_DOWNSTREAM:
3820 0 : if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3821 : return -EINVAL;
3822 : break;
3823 :
3824 : /* Ensure root port supports all the sizes we care about */
3825 : case PCI_EXP_TYPE_ROOT_PORT:
3826 0 : if ((cap & cap_mask) != cap_mask)
3827 : return -EINVAL;
3828 : break;
3829 : }
3830 :
3831 : /* Ensure upstream ports don't block AtomicOps on egress */
3832 0 : if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3833 0 : pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3834 : &ctl2);
3835 0 : if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3836 : return -EINVAL;
3837 : }
3838 :
3839 0 : bus = bus->parent;
3840 : }
3841 :
3842 0 : pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3843 : PCI_EXP_DEVCTL2_ATOMIC_REQ);
3844 0 : return 0;
3845 : }
3846 : EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3847 :
3848 : /**
3849 : * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3850 : * @dev: the PCI device
3851 : * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3852 : *
3853 : * Perform INTx swizzling for a device behind one level of bridge. This is
3854 : * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3855 : * behind bridges on add-in cards. For devices with ARI enabled, the slot
3856 : * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3857 : * the PCI Express Base Specification, Revision 2.1)
3858 : */
3859 0 : u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3860 : {
3861 : int slot;
3862 :
3863 0 : if (pci_ari_enabled(dev->bus))
3864 : slot = 0;
3865 : else
3866 0 : slot = PCI_SLOT(dev->devfn);
3867 :
3868 0 : return (((pin - 1) + slot) % 4) + 1;
3869 : }
3870 :
3871 0 : int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3872 : {
3873 : u8 pin;
3874 :
3875 0 : pin = dev->pin;
3876 0 : if (!pin)
3877 : return -1;
3878 :
3879 0 : while (!pci_is_root_bus(dev->bus)) {
3880 0 : pin = pci_swizzle_interrupt_pin(dev, pin);
3881 0 : dev = dev->bus->self;
3882 : }
3883 0 : *bridge = dev;
3884 0 : return pin;
3885 : }
3886 :
3887 : /**
3888 : * pci_common_swizzle - swizzle INTx all the way to root bridge
3889 : * @dev: the PCI device
3890 : * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3891 : *
3892 : * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3893 : * bridges all the way up to a PCI root bus.
3894 : */
3895 0 : u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3896 : {
3897 0 : u8 pin = *pinp;
3898 :
3899 0 : while (!pci_is_root_bus(dev->bus)) {
3900 0 : pin = pci_swizzle_interrupt_pin(dev, pin);
3901 0 : dev = dev->bus->self;
3902 : }
3903 0 : *pinp = pin;
3904 0 : return PCI_SLOT(dev->devfn);
3905 : }
3906 : EXPORT_SYMBOL_GPL(pci_common_swizzle);
3907 :
3908 : /**
3909 : * pci_release_region - Release a PCI bar
3910 : * @pdev: PCI device whose resources were previously reserved by
3911 : * pci_request_region()
3912 : * @bar: BAR to release
3913 : *
3914 : * Releases the PCI I/O and memory resources previously reserved by a
3915 : * successful call to pci_request_region(). Call this function only
3916 : * after all use of the PCI regions has ceased.
3917 : */
3918 0 : void pci_release_region(struct pci_dev *pdev, int bar)
3919 : {
3920 : struct pci_devres *dr;
3921 :
3922 0 : if (pci_resource_len(pdev, bar) == 0)
3923 : return;
3924 0 : if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3925 0 : release_region(pci_resource_start(pdev, bar),
3926 : pci_resource_len(pdev, bar));
3927 0 : else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3928 0 : release_mem_region(pci_resource_start(pdev, bar),
3929 : pci_resource_len(pdev, bar));
3930 :
3931 0 : dr = find_pci_dr(pdev);
3932 0 : if (dr)
3933 0 : dr->region_mask &= ~(1 << bar);
3934 : }
3935 : EXPORT_SYMBOL(pci_release_region);
3936 :
3937 : /**
3938 : * __pci_request_region - Reserved PCI I/O and memory resource
3939 : * @pdev: PCI device whose resources are to be reserved
3940 : * @bar: BAR to be reserved
3941 : * @res_name: Name to be associated with resource.
3942 : * @exclusive: whether the region access is exclusive or not
3943 : *
3944 : * Mark the PCI region associated with PCI device @pdev BAR @bar as
3945 : * being reserved by owner @res_name. Do not access any
3946 : * address inside the PCI regions unless this call returns
3947 : * successfully.
3948 : *
3949 : * If @exclusive is set, then the region is marked so that userspace
3950 : * is explicitly not allowed to map the resource via /dev/mem or
3951 : * sysfs MMIO access.
3952 : *
3953 : * Returns 0 on success, or %EBUSY on error. A warning
3954 : * message is also printed on failure.
3955 : */
3956 0 : static int __pci_request_region(struct pci_dev *pdev, int bar,
3957 : const char *res_name, int exclusive)
3958 : {
3959 : struct pci_devres *dr;
3960 :
3961 0 : if (pci_resource_len(pdev, bar) == 0)
3962 : return 0;
3963 :
3964 0 : if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3965 0 : if (!request_region(pci_resource_start(pdev, bar),
3966 : pci_resource_len(pdev, bar), res_name))
3967 : goto err_out;
3968 0 : } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3969 0 : if (!__request_mem_region(pci_resource_start(pdev, bar),
3970 : pci_resource_len(pdev, bar), res_name,
3971 : exclusive))
3972 : goto err_out;
3973 : }
3974 :
3975 0 : dr = find_pci_dr(pdev);
3976 0 : if (dr)
3977 0 : dr->region_mask |= 1 << bar;
3978 :
3979 : return 0;
3980 :
3981 : err_out:
3982 0 : pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3983 : &pdev->resource[bar]);
3984 0 : return -EBUSY;
3985 : }
3986 :
3987 : /**
3988 : * pci_request_region - Reserve PCI I/O and memory resource
3989 : * @pdev: PCI device whose resources are to be reserved
3990 : * @bar: BAR to be reserved
3991 : * @res_name: Name to be associated with resource
3992 : *
3993 : * Mark the PCI region associated with PCI device @pdev BAR @bar as
3994 : * being reserved by owner @res_name. Do not access any
3995 : * address inside the PCI regions unless this call returns
3996 : * successfully.
3997 : *
3998 : * Returns 0 on success, or %EBUSY on error. A warning
3999 : * message is also printed on failure.
4000 : */
4001 0 : int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
4002 : {
4003 0 : return __pci_request_region(pdev, bar, res_name, 0);
4004 : }
4005 : EXPORT_SYMBOL(pci_request_region);
4006 :
4007 : /**
4008 : * pci_release_selected_regions - Release selected PCI I/O and memory resources
4009 : * @pdev: PCI device whose resources were previously reserved
4010 : * @bars: Bitmask of BARs to be released
4011 : *
4012 : * Release selected PCI I/O and memory resources previously reserved.
4013 : * Call this function only after all use of the PCI regions has ceased.
4014 : */
4015 0 : void pci_release_selected_regions(struct pci_dev *pdev, int bars)
4016 : {
4017 : int i;
4018 :
4019 0 : for (i = 0; i < PCI_STD_NUM_BARS; i++)
4020 0 : if (bars & (1 << i))
4021 0 : pci_release_region(pdev, i);
4022 0 : }
4023 : EXPORT_SYMBOL(pci_release_selected_regions);
4024 :
4025 0 : static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
4026 : const char *res_name, int excl)
4027 : {
4028 : int i;
4029 :
4030 0 : for (i = 0; i < PCI_STD_NUM_BARS; i++)
4031 0 : if (bars & (1 << i))
4032 0 : if (__pci_request_region(pdev, i, res_name, excl))
4033 : goto err_out;
4034 : return 0;
4035 :
4036 : err_out:
4037 0 : while (--i >= 0)
4038 0 : if (bars & (1 << i))
4039 0 : pci_release_region(pdev, i);
4040 :
4041 : return -EBUSY;
4042 : }
4043 :
4044 :
4045 : /**
4046 : * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4047 : * @pdev: PCI device whose resources are to be reserved
4048 : * @bars: Bitmask of BARs to be requested
4049 : * @res_name: Name to be associated with resource
4050 : */
4051 0 : int pci_request_selected_regions(struct pci_dev *pdev, int bars,
4052 : const char *res_name)
4053 : {
4054 0 : return __pci_request_selected_regions(pdev, bars, res_name, 0);
4055 : }
4056 : EXPORT_SYMBOL(pci_request_selected_regions);
4057 :
4058 0 : int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
4059 : const char *res_name)
4060 : {
4061 0 : return __pci_request_selected_regions(pdev, bars, res_name,
4062 : IORESOURCE_EXCLUSIVE);
4063 : }
4064 : EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4065 :
4066 : /**
4067 : * pci_release_regions - Release reserved PCI I/O and memory resources
4068 : * @pdev: PCI device whose resources were previously reserved by
4069 : * pci_request_regions()
4070 : *
4071 : * Releases all PCI I/O and memory resources previously reserved by a
4072 : * successful call to pci_request_regions(). Call this function only
4073 : * after all use of the PCI regions has ceased.
4074 : */
4075 :
4076 0 : void pci_release_regions(struct pci_dev *pdev)
4077 : {
4078 0 : pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
4079 0 : }
4080 : EXPORT_SYMBOL(pci_release_regions);
4081 :
4082 : /**
4083 : * pci_request_regions - Reserve PCI I/O and memory resources
4084 : * @pdev: PCI device whose resources are to be reserved
4085 : * @res_name: Name to be associated with resource.
4086 : *
4087 : * Mark all PCI regions associated with PCI device @pdev as
4088 : * being reserved by owner @res_name. Do not access any
4089 : * address inside the PCI regions unless this call returns
4090 : * successfully.
4091 : *
4092 : * Returns 0 on success, or %EBUSY on error. A warning
4093 : * message is also printed on failure.
4094 : */
4095 0 : int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4096 : {
4097 0 : return pci_request_selected_regions(pdev,
4098 : ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4099 : }
4100 : EXPORT_SYMBOL(pci_request_regions);
4101 :
4102 : /**
4103 : * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4104 : * @pdev: PCI device whose resources are to be reserved
4105 : * @res_name: Name to be associated with resource.
4106 : *
4107 : * Mark all PCI regions associated with PCI device @pdev as being reserved
4108 : * by owner @res_name. Do not access any address inside the PCI regions
4109 : * unless this call returns successfully.
4110 : *
4111 : * pci_request_regions_exclusive() will mark the region so that /dev/mem
4112 : * and the sysfs MMIO access will not be allowed.
4113 : *
4114 : * Returns 0 on success, or %EBUSY on error. A warning message is also
4115 : * printed on failure.
4116 : */
4117 0 : int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4118 : {
4119 0 : return pci_request_selected_regions_exclusive(pdev,
4120 : ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4121 : }
4122 : EXPORT_SYMBOL(pci_request_regions_exclusive);
4123 :
4124 : /*
4125 : * Record the PCI IO range (expressed as CPU physical address + size).
4126 : * Return a negative value if an error has occurred, zero otherwise
4127 : */
4128 0 : int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4129 : resource_size_t size)
4130 : {
4131 0 : int ret = 0;
4132 : #ifdef PCI_IOBASE
4133 : struct logic_pio_hwaddr *range;
4134 :
4135 0 : if (!size || addr + size < addr)
4136 : return -EINVAL;
4137 :
4138 0 : range = kzalloc(sizeof(*range), GFP_ATOMIC);
4139 0 : if (!range)
4140 : return -ENOMEM;
4141 :
4142 0 : range->fwnode = fwnode;
4143 0 : range->size = size;
4144 0 : range->hw_start = addr;
4145 0 : range->flags = LOGIC_PIO_CPU_MMIO;
4146 :
4147 0 : ret = logic_pio_register_range(range);
4148 0 : if (ret)
4149 0 : kfree(range);
4150 :
4151 : /* Ignore duplicates due to deferred probing */
4152 0 : if (ret == -EEXIST)
4153 0 : ret = 0;
4154 : #endif
4155 :
4156 : return ret;
4157 : }
4158 :
4159 0 : phys_addr_t pci_pio_to_address(unsigned long pio)
4160 : {
4161 0 : phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
4162 :
4163 : #ifdef PCI_IOBASE
4164 0 : if (pio >= MMIO_UPPER_LIMIT)
4165 : return address;
4166 :
4167 0 : address = logic_pio_to_hwaddr(pio);
4168 : #endif
4169 :
4170 0 : return address;
4171 : }
4172 : EXPORT_SYMBOL_GPL(pci_pio_to_address);
4173 :
4174 0 : unsigned long __weak pci_address_to_pio(phys_addr_t address)
4175 : {
4176 : #ifdef PCI_IOBASE
4177 0 : return logic_pio_trans_cpuaddr(address);
4178 : #else
4179 : if (address > IO_SPACE_LIMIT)
4180 : return (unsigned long)-1;
4181 :
4182 : return (unsigned long) address;
4183 : #endif
4184 : }
4185 :
4186 : /**
4187 : * pci_remap_iospace - Remap the memory mapped I/O space
4188 : * @res: Resource describing the I/O space
4189 : * @phys_addr: physical address of range to be mapped
4190 : *
4191 : * Remap the memory mapped I/O space described by the @res and the CPU
4192 : * physical address @phys_addr into virtual address space. Only
4193 : * architectures that have memory mapped IO functions defined (and the
4194 : * PCI_IOBASE value defined) should call this function.
4195 : */
4196 : #ifndef pci_remap_iospace
4197 0 : int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4198 : {
4199 : #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4200 0 : unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4201 :
4202 0 : if (!(res->flags & IORESOURCE_IO))
4203 : return -EINVAL;
4204 :
4205 0 : if (res->end > IO_SPACE_LIMIT)
4206 : return -EINVAL;
4207 :
4208 0 : return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4209 0 : pgprot_device(PAGE_KERNEL));
4210 : #else
4211 : /*
4212 : * This architecture does not have memory mapped I/O space,
4213 : * so this function should never be called
4214 : */
4215 : WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4216 : return -ENODEV;
4217 : #endif
4218 : }
4219 : EXPORT_SYMBOL(pci_remap_iospace);
4220 : #endif
4221 :
4222 : /**
4223 : * pci_unmap_iospace - Unmap the memory mapped I/O space
4224 : * @res: resource to be unmapped
4225 : *
4226 : * Unmap the CPU virtual address @res from virtual address space. Only
4227 : * architectures that have memory mapped IO functions defined (and the
4228 : * PCI_IOBASE value defined) should call this function.
4229 : */
4230 0 : void pci_unmap_iospace(struct resource *res)
4231 : {
4232 : #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4233 0 : unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4234 :
4235 0 : vunmap_range(vaddr, vaddr + resource_size(res));
4236 : #endif
4237 0 : }
4238 : EXPORT_SYMBOL(pci_unmap_iospace);
4239 :
4240 0 : static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4241 : {
4242 0 : struct resource **res = ptr;
4243 :
4244 0 : pci_unmap_iospace(*res);
4245 0 : }
4246 :
4247 : /**
4248 : * devm_pci_remap_iospace - Managed pci_remap_iospace()
4249 : * @dev: Generic device to remap IO address for
4250 : * @res: Resource describing the I/O space
4251 : * @phys_addr: physical address of range to be mapped
4252 : *
4253 : * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4254 : * detach.
4255 : */
4256 0 : int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4257 : phys_addr_t phys_addr)
4258 : {
4259 : const struct resource **ptr;
4260 : int error;
4261 :
4262 0 : ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4263 0 : if (!ptr)
4264 : return -ENOMEM;
4265 :
4266 0 : error = pci_remap_iospace(res, phys_addr);
4267 0 : if (error) {
4268 0 : devres_free(ptr);
4269 : } else {
4270 0 : *ptr = res;
4271 0 : devres_add(dev, ptr);
4272 : }
4273 :
4274 : return error;
4275 : }
4276 : EXPORT_SYMBOL(devm_pci_remap_iospace);
4277 :
4278 : /**
4279 : * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4280 : * @dev: Generic device to remap IO address for
4281 : * @offset: Resource address to map
4282 : * @size: Size of map
4283 : *
4284 : * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4285 : * detach.
4286 : */
4287 0 : void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4288 : resource_size_t offset,
4289 : resource_size_t size)
4290 : {
4291 : void __iomem **ptr, *addr;
4292 :
4293 0 : ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4294 0 : if (!ptr)
4295 : return NULL;
4296 :
4297 0 : addr = pci_remap_cfgspace(offset, size);
4298 0 : if (addr) {
4299 0 : *ptr = addr;
4300 0 : devres_add(dev, ptr);
4301 : } else
4302 0 : devres_free(ptr);
4303 :
4304 : return addr;
4305 : }
4306 : EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4307 :
4308 : /**
4309 : * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4310 : * @dev: generic device to handle the resource for
4311 : * @res: configuration space resource to be handled
4312 : *
4313 : * Checks that a resource is a valid memory region, requests the memory
4314 : * region and ioremaps with pci_remap_cfgspace() API that ensures the
4315 : * proper PCI configuration space memory attributes are guaranteed.
4316 : *
4317 : * All operations are managed and will be undone on driver detach.
4318 : *
4319 : * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4320 : * on failure. Usage example::
4321 : *
4322 : * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4323 : * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4324 : * if (IS_ERR(base))
4325 : * return PTR_ERR(base);
4326 : */
4327 0 : void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4328 : struct resource *res)
4329 : {
4330 : resource_size_t size;
4331 : const char *name;
4332 : void __iomem *dest_ptr;
4333 :
4334 0 : BUG_ON(!dev);
4335 :
4336 0 : if (!res || resource_type(res) != IORESOURCE_MEM) {
4337 0 : dev_err(dev, "invalid resource\n");
4338 0 : return IOMEM_ERR_PTR(-EINVAL);
4339 : }
4340 :
4341 0 : size = resource_size(res);
4342 :
4343 0 : if (res->name)
4344 0 : name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4345 : res->name);
4346 : else
4347 0 : name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4348 0 : if (!name)
4349 : return IOMEM_ERR_PTR(-ENOMEM);
4350 :
4351 0 : if (!devm_request_mem_region(dev, res->start, size, name)) {
4352 0 : dev_err(dev, "can't request region for resource %pR\n", res);
4353 0 : return IOMEM_ERR_PTR(-EBUSY);
4354 : }
4355 :
4356 0 : dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4357 0 : if (!dest_ptr) {
4358 0 : dev_err(dev, "ioremap failed for resource %pR\n", res);
4359 0 : devm_release_mem_region(dev, res->start, size);
4360 0 : dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4361 : }
4362 :
4363 : return dest_ptr;
4364 : }
4365 : EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4366 :
4367 0 : static void __pci_set_master(struct pci_dev *dev, bool enable)
4368 : {
4369 : u16 old_cmd, cmd;
4370 :
4371 0 : pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4372 0 : if (enable)
4373 0 : cmd = old_cmd | PCI_COMMAND_MASTER;
4374 : else
4375 0 : cmd = old_cmd & ~PCI_COMMAND_MASTER;
4376 0 : if (cmd != old_cmd) {
4377 : pci_dbg(dev, "%s bus mastering\n",
4378 : enable ? "enabling" : "disabling");
4379 0 : pci_write_config_word(dev, PCI_COMMAND, cmd);
4380 : }
4381 0 : dev->is_busmaster = enable;
4382 0 : }
4383 :
4384 : /**
4385 : * pcibios_setup - process "pci=" kernel boot arguments
4386 : * @str: string used to pass in "pci=" kernel boot arguments
4387 : *
4388 : * Process kernel boot arguments. This is the default implementation.
4389 : * Architecture specific implementations can override this as necessary.
4390 : */
4391 0 : char * __weak __init pcibios_setup(char *str)
4392 : {
4393 0 : return str;
4394 : }
4395 :
4396 : /**
4397 : * pcibios_set_master - enable PCI bus-mastering for device dev
4398 : * @dev: the PCI device to enable
4399 : *
4400 : * Enables PCI bus-mastering for the device. This is the default
4401 : * implementation. Architecture specific implementations can override
4402 : * this if necessary.
4403 : */
4404 0 : void __weak pcibios_set_master(struct pci_dev *dev)
4405 : {
4406 : u8 lat;
4407 :
4408 : /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4409 0 : if (pci_is_pcie(dev))
4410 0 : return;
4411 :
4412 0 : pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4413 0 : if (lat < 16)
4414 0 : lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4415 0 : else if (lat > pcibios_max_latency)
4416 0 : lat = pcibios_max_latency;
4417 : else
4418 : return;
4419 :
4420 0 : pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4421 : }
4422 :
4423 : /**
4424 : * pci_set_master - enables bus-mastering for device dev
4425 : * @dev: the PCI device to enable
4426 : *
4427 : * Enables bus-mastering on the device and calls pcibios_set_master()
4428 : * to do the needed arch specific settings.
4429 : */
4430 0 : void pci_set_master(struct pci_dev *dev)
4431 : {
4432 0 : __pci_set_master(dev, true);
4433 0 : pcibios_set_master(dev);
4434 0 : }
4435 : EXPORT_SYMBOL(pci_set_master);
4436 :
4437 : /**
4438 : * pci_clear_master - disables bus-mastering for device dev
4439 : * @dev: the PCI device to disable
4440 : */
4441 0 : void pci_clear_master(struct pci_dev *dev)
4442 : {
4443 0 : __pci_set_master(dev, false);
4444 0 : }
4445 : EXPORT_SYMBOL(pci_clear_master);
4446 :
4447 : /**
4448 : * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4449 : * @dev: the PCI device for which MWI is to be enabled
4450 : *
4451 : * Helper function for pci_set_mwi.
4452 : * Originally copied from drivers/net/acenic.c.
4453 : * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4454 : *
4455 : * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4456 : */
4457 0 : int pci_set_cacheline_size(struct pci_dev *dev)
4458 : {
4459 : u8 cacheline_size;
4460 :
4461 0 : if (!pci_cache_line_size)
4462 : return -EINVAL;
4463 :
4464 : /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4465 : equal to or multiple of the right value. */
4466 0 : pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4467 0 : if (cacheline_size >= pci_cache_line_size &&
4468 0 : (cacheline_size % pci_cache_line_size) == 0)
4469 : return 0;
4470 :
4471 : /* Write the correct value. */
4472 0 : pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4473 : /* Read it back. */
4474 0 : pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4475 0 : if (cacheline_size == pci_cache_line_size)
4476 : return 0;
4477 :
4478 : pci_dbg(dev, "cache line size of %d is not supported\n",
4479 : pci_cache_line_size << 2);
4480 :
4481 0 : return -EINVAL;
4482 : }
4483 : EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4484 :
4485 : /**
4486 : * pci_set_mwi - enables memory-write-invalidate PCI transaction
4487 : * @dev: the PCI device for which MWI is enabled
4488 : *
4489 : * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4490 : *
4491 : * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4492 : */
4493 0 : int pci_set_mwi(struct pci_dev *dev)
4494 : {
4495 : #ifdef PCI_DISABLE_MWI
4496 : return 0;
4497 : #else
4498 : int rc;
4499 : u16 cmd;
4500 :
4501 0 : rc = pci_set_cacheline_size(dev);
4502 0 : if (rc)
4503 : return rc;
4504 :
4505 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
4506 0 : if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4507 : pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4508 0 : cmd |= PCI_COMMAND_INVALIDATE;
4509 0 : pci_write_config_word(dev, PCI_COMMAND, cmd);
4510 : }
4511 : return 0;
4512 : #endif
4513 : }
4514 : EXPORT_SYMBOL(pci_set_mwi);
4515 :
4516 : /**
4517 : * pcim_set_mwi - a device-managed pci_set_mwi()
4518 : * @dev: the PCI device for which MWI is enabled
4519 : *
4520 : * Managed pci_set_mwi().
4521 : *
4522 : * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4523 : */
4524 0 : int pcim_set_mwi(struct pci_dev *dev)
4525 : {
4526 : struct pci_devres *dr;
4527 :
4528 0 : dr = find_pci_dr(dev);
4529 0 : if (!dr)
4530 : return -ENOMEM;
4531 :
4532 0 : dr->mwi = 1;
4533 0 : return pci_set_mwi(dev);
4534 : }
4535 : EXPORT_SYMBOL(pcim_set_mwi);
4536 :
4537 : /**
4538 : * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4539 : * @dev: the PCI device for which MWI is enabled
4540 : *
4541 : * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4542 : * Callers are not required to check the return value.
4543 : *
4544 : * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4545 : */
4546 0 : int pci_try_set_mwi(struct pci_dev *dev)
4547 : {
4548 : #ifdef PCI_DISABLE_MWI
4549 : return 0;
4550 : #else
4551 0 : return pci_set_mwi(dev);
4552 : #endif
4553 : }
4554 : EXPORT_SYMBOL(pci_try_set_mwi);
4555 :
4556 : /**
4557 : * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4558 : * @dev: the PCI device to disable
4559 : *
4560 : * Disables PCI Memory-Write-Invalidate transaction on the device
4561 : */
4562 0 : void pci_clear_mwi(struct pci_dev *dev)
4563 : {
4564 : #ifndef PCI_DISABLE_MWI
4565 : u16 cmd;
4566 :
4567 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
4568 0 : if (cmd & PCI_COMMAND_INVALIDATE) {
4569 0 : cmd &= ~PCI_COMMAND_INVALIDATE;
4570 0 : pci_write_config_word(dev, PCI_COMMAND, cmd);
4571 : }
4572 : #endif
4573 0 : }
4574 : EXPORT_SYMBOL(pci_clear_mwi);
4575 :
4576 : /**
4577 : * pci_disable_parity - disable parity checking for device
4578 : * @dev: the PCI device to operate on
4579 : *
4580 : * Disable parity checking for device @dev
4581 : */
4582 0 : void pci_disable_parity(struct pci_dev *dev)
4583 : {
4584 : u16 cmd;
4585 :
4586 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
4587 0 : if (cmd & PCI_COMMAND_PARITY) {
4588 0 : cmd &= ~PCI_COMMAND_PARITY;
4589 0 : pci_write_config_word(dev, PCI_COMMAND, cmd);
4590 : }
4591 0 : }
4592 :
4593 : /**
4594 : * pci_intx - enables/disables PCI INTx for device dev
4595 : * @pdev: the PCI device to operate on
4596 : * @enable: boolean: whether to enable or disable PCI INTx
4597 : *
4598 : * Enables/disables PCI INTx for device @pdev
4599 : */
4600 0 : void pci_intx(struct pci_dev *pdev, int enable)
4601 : {
4602 : u16 pci_command, new;
4603 :
4604 0 : pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4605 :
4606 0 : if (enable)
4607 0 : new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4608 : else
4609 0 : new = pci_command | PCI_COMMAND_INTX_DISABLE;
4610 :
4611 0 : if (new != pci_command) {
4612 : struct pci_devres *dr;
4613 :
4614 0 : pci_write_config_word(pdev, PCI_COMMAND, new);
4615 :
4616 0 : dr = find_pci_dr(pdev);
4617 0 : if (dr && !dr->restore_intx) {
4618 0 : dr->restore_intx = 1;
4619 0 : dr->orig_intx = !enable;
4620 : }
4621 : }
4622 0 : }
4623 : EXPORT_SYMBOL_GPL(pci_intx);
4624 :
4625 0 : static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4626 : {
4627 0 : struct pci_bus *bus = dev->bus;
4628 0 : bool mask_updated = true;
4629 : u32 cmd_status_dword;
4630 : u16 origcmd, newcmd;
4631 : unsigned long flags;
4632 : bool irq_pending;
4633 :
4634 : /*
4635 : * We do a single dword read to retrieve both command and status.
4636 : * Document assumptions that make this possible.
4637 : */
4638 : BUILD_BUG_ON(PCI_COMMAND % 4);
4639 : BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4640 :
4641 0 : raw_spin_lock_irqsave(&pci_lock, flags);
4642 :
4643 0 : bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4644 :
4645 0 : irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4646 :
4647 : /*
4648 : * Check interrupt status register to see whether our device
4649 : * triggered the interrupt (when masking) or the next IRQ is
4650 : * already pending (when unmasking).
4651 : */
4652 0 : if (mask != irq_pending) {
4653 : mask_updated = false;
4654 : goto done;
4655 : }
4656 :
4657 0 : origcmd = cmd_status_dword;
4658 0 : newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4659 0 : if (mask)
4660 0 : newcmd |= PCI_COMMAND_INTX_DISABLE;
4661 0 : if (newcmd != origcmd)
4662 0 : bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4663 :
4664 : done:
4665 0 : raw_spin_unlock_irqrestore(&pci_lock, flags);
4666 :
4667 0 : return mask_updated;
4668 : }
4669 :
4670 : /**
4671 : * pci_check_and_mask_intx - mask INTx on pending interrupt
4672 : * @dev: the PCI device to operate on
4673 : *
4674 : * Check if the device dev has its INTx line asserted, mask it and return
4675 : * true in that case. False is returned if no interrupt was pending.
4676 : */
4677 0 : bool pci_check_and_mask_intx(struct pci_dev *dev)
4678 : {
4679 0 : return pci_check_and_set_intx_mask(dev, true);
4680 : }
4681 : EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4682 :
4683 : /**
4684 : * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4685 : * @dev: the PCI device to operate on
4686 : *
4687 : * Check if the device dev has its INTx line asserted, unmask it if not and
4688 : * return true. False is returned and the mask remains active if there was
4689 : * still an interrupt pending.
4690 : */
4691 0 : bool pci_check_and_unmask_intx(struct pci_dev *dev)
4692 : {
4693 0 : return pci_check_and_set_intx_mask(dev, false);
4694 : }
4695 : EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4696 :
4697 : /**
4698 : * pci_wait_for_pending_transaction - wait for pending transaction
4699 : * @dev: the PCI device to operate on
4700 : *
4701 : * Return 0 if transaction is pending 1 otherwise.
4702 : */
4703 0 : int pci_wait_for_pending_transaction(struct pci_dev *dev)
4704 : {
4705 0 : if (!pci_is_pcie(dev))
4706 : return 1;
4707 :
4708 0 : return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4709 : PCI_EXP_DEVSTA_TRPND);
4710 : }
4711 : EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4712 :
4713 : /**
4714 : * pcie_flr - initiate a PCIe function level reset
4715 : * @dev: device to reset
4716 : *
4717 : * Initiate a function level reset unconditionally on @dev without
4718 : * checking any flags and DEVCAP
4719 : */
4720 0 : int pcie_flr(struct pci_dev *dev)
4721 : {
4722 0 : if (!pci_wait_for_pending_transaction(dev))
4723 0 : pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4724 :
4725 0 : pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4726 :
4727 0 : if (dev->imm_ready)
4728 : return 0;
4729 :
4730 : /*
4731 : * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4732 : * 100ms, but may silently discard requests while the FLR is in
4733 : * progress. Wait 100ms before trying to access the device.
4734 : */
4735 0 : msleep(100);
4736 :
4737 0 : return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4738 : }
4739 : EXPORT_SYMBOL_GPL(pcie_flr);
4740 :
4741 : /**
4742 : * pcie_reset_flr - initiate a PCIe function level reset
4743 : * @dev: device to reset
4744 : * @probe: if true, return 0 if device can be reset this way
4745 : *
4746 : * Initiate a function level reset on @dev.
4747 : */
4748 0 : int pcie_reset_flr(struct pci_dev *dev, bool probe)
4749 : {
4750 0 : if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4751 : return -ENOTTY;
4752 :
4753 0 : if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))
4754 : return -ENOTTY;
4755 :
4756 0 : if (probe)
4757 : return 0;
4758 :
4759 0 : return pcie_flr(dev);
4760 : }
4761 : EXPORT_SYMBOL_GPL(pcie_reset_flr);
4762 :
4763 0 : static int pci_af_flr(struct pci_dev *dev, bool probe)
4764 : {
4765 : int pos;
4766 : u8 cap;
4767 :
4768 0 : pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4769 0 : if (!pos)
4770 : return -ENOTTY;
4771 :
4772 0 : if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4773 : return -ENOTTY;
4774 :
4775 0 : pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4776 0 : if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4777 : return -ENOTTY;
4778 :
4779 0 : if (probe)
4780 : return 0;
4781 :
4782 : /*
4783 : * Wait for Transaction Pending bit to clear. A word-aligned test
4784 : * is used, so we use the control offset rather than status and shift
4785 : * the test bit to match.
4786 : */
4787 0 : if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4788 : PCI_AF_STATUS_TP << 8))
4789 0 : pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4790 :
4791 0 : pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4792 :
4793 0 : if (dev->imm_ready)
4794 : return 0;
4795 :
4796 : /*
4797 : * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4798 : * updated 27 July 2006; a device must complete an FLR within
4799 : * 100ms, but may silently discard requests while the FLR is in
4800 : * progress. Wait 100ms before trying to access the device.
4801 : */
4802 0 : msleep(100);
4803 :
4804 0 : return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4805 : }
4806 :
4807 : /**
4808 : * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4809 : * @dev: Device to reset.
4810 : * @probe: if true, return 0 if the device can be reset this way.
4811 : *
4812 : * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4813 : * unset, it will be reinitialized internally when going from PCI_D3hot to
4814 : * PCI_D0. If that's the case and the device is not in a low-power state
4815 : * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4816 : *
4817 : * NOTE: This causes the caller to sleep for twice the device power transition
4818 : * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4819 : * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4820 : * Moreover, only devices in D0 can be reset by this function.
4821 : */
4822 0 : static int pci_pm_reset(struct pci_dev *dev, bool probe)
4823 : {
4824 : u16 csr;
4825 :
4826 0 : if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4827 : return -ENOTTY;
4828 :
4829 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4830 0 : if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4831 : return -ENOTTY;
4832 :
4833 0 : if (probe)
4834 : return 0;
4835 :
4836 0 : if (dev->current_state != PCI_D0)
4837 : return -EINVAL;
4838 :
4839 0 : csr &= ~PCI_PM_CTRL_STATE_MASK;
4840 0 : csr |= PCI_D3hot;
4841 0 : pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4842 0 : pci_dev_d3_sleep(dev);
4843 :
4844 0 : csr &= ~PCI_PM_CTRL_STATE_MASK;
4845 : csr |= PCI_D0;
4846 0 : pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4847 0 : pci_dev_d3_sleep(dev);
4848 :
4849 0 : return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4850 : }
4851 :
4852 : /**
4853 : * pcie_wait_for_link_delay - Wait until link is active or inactive
4854 : * @pdev: Bridge device
4855 : * @active: waiting for active or inactive?
4856 : * @delay: Delay to wait after link has become active (in ms)
4857 : *
4858 : * Use this to wait till link becomes active or inactive.
4859 : */
4860 0 : static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4861 : int delay)
4862 : {
4863 0 : int timeout = 1000;
4864 : bool ret;
4865 : u16 lnk_status;
4866 :
4867 : /*
4868 : * Some controllers might not implement link active reporting. In this
4869 : * case, we wait for 1000 ms + any delay requested by the caller.
4870 : */
4871 0 : if (!pdev->link_active_reporting) {
4872 0 : msleep(timeout + delay);
4873 0 : return true;
4874 : }
4875 :
4876 : /*
4877 : * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4878 : * after which we should expect an link active if the reset was
4879 : * successful. If so, software must wait a minimum 100ms before sending
4880 : * configuration requests to devices downstream this port.
4881 : *
4882 : * If the link fails to activate, either the device was physically
4883 : * removed or the link is permanently failed.
4884 : */
4885 0 : if (active)
4886 0 : msleep(20);
4887 : for (;;) {
4888 0 : pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4889 0 : ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4890 0 : if (ret == active)
4891 : break;
4892 0 : if (timeout <= 0)
4893 : break;
4894 0 : msleep(10);
4895 0 : timeout -= 10;
4896 : }
4897 0 : if (active && ret)
4898 0 : msleep(delay);
4899 :
4900 0 : return ret == active;
4901 : }
4902 :
4903 : /**
4904 : * pcie_wait_for_link - Wait until link is active or inactive
4905 : * @pdev: Bridge device
4906 : * @active: waiting for active or inactive?
4907 : *
4908 : * Use this to wait till link becomes active or inactive.
4909 : */
4910 0 : bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4911 : {
4912 0 : return pcie_wait_for_link_delay(pdev, active, 100);
4913 : }
4914 :
4915 : /*
4916 : * Find maximum D3cold delay required by all the devices on the bus. The
4917 : * spec says 100 ms, but firmware can lower it and we allow drivers to
4918 : * increase it as well.
4919 : *
4920 : * Called with @pci_bus_sem locked for reading.
4921 : */
4922 : static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4923 : {
4924 : const struct pci_dev *pdev;
4925 0 : int min_delay = 100;
4926 0 : int max_delay = 0;
4927 :
4928 0 : list_for_each_entry(pdev, &bus->devices, bus_list) {
4929 0 : if (pdev->d3cold_delay < min_delay)
4930 0 : min_delay = pdev->d3cold_delay;
4931 0 : if (pdev->d3cold_delay > max_delay)
4932 0 : max_delay = pdev->d3cold_delay;
4933 : }
4934 :
4935 0 : return max(min_delay, max_delay);
4936 : }
4937 :
4938 : /**
4939 : * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4940 : * @dev: PCI bridge
4941 : * @reset_type: reset type in human-readable form
4942 : * @timeout: maximum time to wait for devices on secondary bus (milliseconds)
4943 : *
4944 : * Handle necessary delays before access to the devices on the secondary
4945 : * side of the bridge are permitted after D3cold to D0 transition
4946 : * or Conventional Reset.
4947 : *
4948 : * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4949 : * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4950 : * 4.3.2.
4951 : *
4952 : * Return 0 on success or -ENOTTY if the first device on the secondary bus
4953 : * failed to become accessible.
4954 : */
4955 0 : int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
4956 : int timeout)
4957 : {
4958 : struct pci_dev *child;
4959 : int delay;
4960 :
4961 0 : if (pci_dev_is_disconnected(dev))
4962 : return 0;
4963 :
4964 0 : if (!pci_is_bridge(dev))
4965 : return 0;
4966 :
4967 0 : down_read(&pci_bus_sem);
4968 :
4969 : /*
4970 : * We only deal with devices that are present currently on the bus.
4971 : * For any hot-added devices the access delay is handled in pciehp
4972 : * board_added(). In case of ACPI hotplug the firmware is expected
4973 : * to configure the devices before OS is notified.
4974 : */
4975 0 : if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4976 0 : up_read(&pci_bus_sem);
4977 0 : return 0;
4978 : }
4979 :
4980 : /* Take d3cold_delay requirements into account */
4981 0 : delay = pci_bus_max_d3cold_delay(dev->subordinate);
4982 0 : if (!delay) {
4983 0 : up_read(&pci_bus_sem);
4984 0 : return 0;
4985 : }
4986 :
4987 0 : child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4988 : bus_list);
4989 0 : up_read(&pci_bus_sem);
4990 :
4991 : /*
4992 : * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4993 : * accessing the device after reset (that is 1000 ms + 100 ms).
4994 : */
4995 0 : if (!pci_is_pcie(dev)) {
4996 : pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4997 0 : msleep(1000 + delay);
4998 0 : return 0;
4999 : }
5000 :
5001 : /*
5002 : * For PCIe downstream and root ports that do not support speeds
5003 : * greater than 5 GT/s need to wait minimum 100 ms. For higher
5004 : * speeds (gen3) we need to wait first for the data link layer to
5005 : * become active.
5006 : *
5007 : * However, 100 ms is the minimum and the PCIe spec says the
5008 : * software must allow at least 1s before it can determine that the
5009 : * device that did not respond is a broken device. There is
5010 : * evidence that 100 ms is not always enough, for example certain
5011 : * Titan Ridge xHCI controller does not always respond to
5012 : * configuration requests if we only wait for 100 ms (see
5013 : * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
5014 : *
5015 : * Therefore we wait for 100 ms and check for the device presence
5016 : * until the timeout expires.
5017 : */
5018 0 : if (!pcie_downstream_port(dev))
5019 : return 0;
5020 :
5021 0 : if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
5022 : pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
5023 0 : msleep(delay);
5024 : } else {
5025 : pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
5026 : delay);
5027 0 : if (!pcie_wait_for_link_delay(dev, true, delay)) {
5028 : /* Did not train, no need to wait any further */
5029 0 : pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
5030 0 : return -ENOTTY;
5031 : }
5032 : }
5033 :
5034 0 : return pci_dev_wait(child, reset_type, timeout - delay);
5035 : }
5036 :
5037 0 : void pci_reset_secondary_bus(struct pci_dev *dev)
5038 : {
5039 : u16 ctrl;
5040 :
5041 0 : pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
5042 0 : ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
5043 0 : pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5044 :
5045 : /*
5046 : * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
5047 : * this to 2ms to ensure that we meet the minimum requirement.
5048 : */
5049 0 : msleep(2);
5050 :
5051 0 : ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
5052 0 : pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5053 0 : }
5054 :
5055 0 : void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
5056 : {
5057 0 : pci_reset_secondary_bus(dev);
5058 0 : }
5059 :
5060 : /**
5061 : * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5062 : * @dev: Bridge device
5063 : *
5064 : * Use the bridge control register to assert reset on the secondary bus.
5065 : * Devices on the secondary bus are left in power-on state.
5066 : */
5067 0 : int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
5068 : {
5069 0 : pcibios_reset_secondary_bus(dev);
5070 :
5071 0 : return pci_bridge_wait_for_secondary_bus(dev, "bus reset",
5072 : PCIE_RESET_READY_POLL_MS);
5073 : }
5074 : EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
5075 :
5076 0 : static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)
5077 : {
5078 : struct pci_dev *pdev;
5079 :
5080 0 : if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5081 0 : !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5082 : return -ENOTTY;
5083 :
5084 0 : list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5085 0 : if (pdev != dev)
5086 : return -ENOTTY;
5087 :
5088 0 : if (probe)
5089 : return 0;
5090 :
5091 0 : return pci_bridge_secondary_bus_reset(dev->bus->self);
5092 : }
5093 :
5094 : static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe)
5095 : {
5096 0 : int rc = -ENOTTY;
5097 :
5098 0 : if (!hotplug || !try_module_get(hotplug->owner))
5099 : return rc;
5100 :
5101 0 : if (hotplug->ops->reset_slot)
5102 0 : rc = hotplug->ops->reset_slot(hotplug, probe);
5103 :
5104 : module_put(hotplug->owner);
5105 :
5106 : return rc;
5107 : }
5108 :
5109 0 : static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
5110 : {
5111 0 : if (dev->multifunction || dev->subordinate || !dev->slot ||
5112 0 : dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5113 : return -ENOTTY;
5114 :
5115 0 : return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5116 : }
5117 :
5118 0 : static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
5119 : {
5120 : int rc;
5121 :
5122 0 : rc = pci_dev_reset_slot_function(dev, probe);
5123 0 : if (rc != -ENOTTY)
5124 : return rc;
5125 0 : return pci_parent_bus_reset(dev, probe);
5126 : }
5127 :
5128 0 : void pci_dev_lock(struct pci_dev *dev)
5129 : {
5130 : /* block PM suspend, driver probe, etc. */
5131 0 : device_lock(&dev->dev);
5132 0 : pci_cfg_access_lock(dev);
5133 0 : }
5134 : EXPORT_SYMBOL_GPL(pci_dev_lock);
5135 :
5136 : /* Return 1 on successful lock, 0 on contention */
5137 0 : int pci_dev_trylock(struct pci_dev *dev)
5138 : {
5139 0 : if (device_trylock(&dev->dev)) {
5140 0 : if (pci_cfg_access_trylock(dev))
5141 : return 1;
5142 0 : device_unlock(&dev->dev);
5143 : }
5144 :
5145 : return 0;
5146 : }
5147 : EXPORT_SYMBOL_GPL(pci_dev_trylock);
5148 :
5149 0 : void pci_dev_unlock(struct pci_dev *dev)
5150 : {
5151 0 : pci_cfg_access_unlock(dev);
5152 0 : device_unlock(&dev->dev);
5153 0 : }
5154 : EXPORT_SYMBOL_GPL(pci_dev_unlock);
5155 :
5156 0 : static void pci_dev_save_and_disable(struct pci_dev *dev)
5157 : {
5158 0 : const struct pci_error_handlers *err_handler =
5159 0 : dev->driver ? dev->driver->err_handler : NULL;
5160 :
5161 : /*
5162 : * dev->driver->err_handler->reset_prepare() is protected against
5163 : * races with ->remove() by the device lock, which must be held by
5164 : * the caller.
5165 : */
5166 0 : if (err_handler && err_handler->reset_prepare)
5167 0 : err_handler->reset_prepare(dev);
5168 :
5169 : /*
5170 : * Wake-up device prior to save. PM registers default to D0 after
5171 : * reset and a simple register restore doesn't reliably return
5172 : * to a non-D0 state anyway.
5173 : */
5174 0 : pci_set_power_state(dev, PCI_D0);
5175 :
5176 0 : pci_save_state(dev);
5177 : /*
5178 : * Disable the device by clearing the Command register, except for
5179 : * INTx-disable which is set. This not only disables MMIO and I/O port
5180 : * BARs, but also prevents the device from being Bus Master, preventing
5181 : * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5182 : * compliant devices, INTx-disable prevents legacy interrupts.
5183 : */
5184 0 : pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5185 0 : }
5186 :
5187 0 : static void pci_dev_restore(struct pci_dev *dev)
5188 : {
5189 0 : const struct pci_error_handlers *err_handler =
5190 0 : dev->driver ? dev->driver->err_handler : NULL;
5191 :
5192 0 : pci_restore_state(dev);
5193 :
5194 : /*
5195 : * dev->driver->err_handler->reset_done() is protected against
5196 : * races with ->remove() by the device lock, which must be held by
5197 : * the caller.
5198 : */
5199 0 : if (err_handler && err_handler->reset_done)
5200 0 : err_handler->reset_done(dev);
5201 0 : }
5202 :
5203 : /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5204 : static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
5205 : { },
5206 : { pci_dev_specific_reset, .name = "device_specific" },
5207 : { pci_dev_acpi_reset, .name = "acpi" },
5208 : { pcie_reset_flr, .name = "flr" },
5209 : { pci_af_flr, .name = "af_flr" },
5210 : { pci_pm_reset, .name = "pm" },
5211 : { pci_reset_bus_function, .name = "bus" },
5212 : };
5213 :
5214 0 : static ssize_t reset_method_show(struct device *dev,
5215 : struct device_attribute *attr, char *buf)
5216 : {
5217 0 : struct pci_dev *pdev = to_pci_dev(dev);
5218 0 : ssize_t len = 0;
5219 : int i, m;
5220 :
5221 0 : for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5222 0 : m = pdev->reset_methods[i];
5223 0 : if (!m)
5224 : break;
5225 :
5226 0 : len += sysfs_emit_at(buf, len, "%s%s", len ? " " : "",
5227 : pci_reset_fn_methods[m].name);
5228 : }
5229 :
5230 0 : if (len)
5231 0 : len += sysfs_emit_at(buf, len, "\n");
5232 :
5233 0 : return len;
5234 : }
5235 :
5236 : static int reset_method_lookup(const char *name)
5237 : {
5238 : int m;
5239 :
5240 0 : for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5241 0 : if (sysfs_streq(name, pci_reset_fn_methods[m].name))
5242 : return m;
5243 : }
5244 :
5245 : return 0; /* not found */
5246 : }
5247 :
5248 0 : static ssize_t reset_method_store(struct device *dev,
5249 : struct device_attribute *attr,
5250 : const char *buf, size_t count)
5251 : {
5252 0 : struct pci_dev *pdev = to_pci_dev(dev);
5253 : char *options, *name;
5254 : int m, n;
5255 0 : u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 };
5256 :
5257 0 : if (sysfs_streq(buf, "")) {
5258 0 : pdev->reset_methods[0] = 0;
5259 0 : pci_warn(pdev, "All device reset methods disabled by user");
5260 0 : return count;
5261 : }
5262 :
5263 0 : if (sysfs_streq(buf, "default")) {
5264 0 : pci_init_reset_methods(pdev);
5265 0 : return count;
5266 : }
5267 :
5268 0 : options = kstrndup(buf, count, GFP_KERNEL);
5269 0 : if (!options)
5270 : return -ENOMEM;
5271 :
5272 : n = 0;
5273 0 : while ((name = strsep(&options, " ")) != NULL) {
5274 0 : if (sysfs_streq(name, ""))
5275 0 : continue;
5276 :
5277 0 : name = strim(name);
5278 :
5279 0 : m = reset_method_lookup(name);
5280 0 : if (!m) {
5281 0 : pci_err(pdev, "Invalid reset method '%s'", name);
5282 0 : goto error;
5283 : }
5284 :
5285 0 : if (pci_reset_fn_methods[m].reset_fn(pdev, PCI_RESET_PROBE)) {
5286 0 : pci_err(pdev, "Unsupported reset method '%s'", name);
5287 0 : goto error;
5288 : }
5289 :
5290 0 : if (n == PCI_NUM_RESET_METHODS - 1) {
5291 0 : pci_err(pdev, "Too many reset methods\n");
5292 0 : goto error;
5293 : }
5294 :
5295 0 : reset_methods[n++] = m;
5296 : }
5297 :
5298 0 : reset_methods[n] = 0;
5299 :
5300 : /* Warn if dev-specific supported but not highest priority */
5301 0 : if (pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) == 0 &&
5302 0 : reset_methods[0] != 1)
5303 0 : pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user");
5304 0 : memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods));
5305 0 : kfree(options);
5306 0 : return count;
5307 :
5308 : error:
5309 : /* Leave previous methods unchanged */
5310 0 : kfree(options);
5311 0 : return -EINVAL;
5312 : }
5313 : static DEVICE_ATTR_RW(reset_method);
5314 :
5315 : static struct attribute *pci_dev_reset_method_attrs[] = {
5316 : &dev_attr_reset_method.attr,
5317 : NULL,
5318 : };
5319 :
5320 0 : static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj,
5321 : struct attribute *a, int n)
5322 : {
5323 0 : struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
5324 :
5325 0 : if (!pci_reset_supported(pdev))
5326 : return 0;
5327 :
5328 0 : return a->mode;
5329 : }
5330 :
5331 : const struct attribute_group pci_dev_reset_method_attr_group = {
5332 : .attrs = pci_dev_reset_method_attrs,
5333 : .is_visible = pci_dev_reset_method_attr_is_visible,
5334 : };
5335 :
5336 : /**
5337 : * __pci_reset_function_locked - reset a PCI device function while holding
5338 : * the @dev mutex lock.
5339 : * @dev: PCI device to reset
5340 : *
5341 : * Some devices allow an individual function to be reset without affecting
5342 : * other functions in the same device. The PCI device must be responsive
5343 : * to PCI config space in order to use this function.
5344 : *
5345 : * The device function is presumed to be unused and the caller is holding
5346 : * the device mutex lock when this function is called.
5347 : *
5348 : * Resetting the device will make the contents of PCI configuration space
5349 : * random, so any caller of this must be prepared to reinitialise the
5350 : * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5351 : * etc.
5352 : *
5353 : * Returns 0 if the device function was successfully reset or negative if the
5354 : * device doesn't support resetting a single function.
5355 : */
5356 0 : int __pci_reset_function_locked(struct pci_dev *dev)
5357 : {
5358 : int i, m, rc;
5359 :
5360 : might_sleep();
5361 :
5362 : /*
5363 : * A reset method returns -ENOTTY if it doesn't support this device and
5364 : * we should try the next method.
5365 : *
5366 : * If it returns 0 (success), we're finished. If it returns any other
5367 : * error, we're also finished: this indicates that further reset
5368 : * mechanisms might be broken on the device.
5369 : */
5370 0 : for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5371 0 : m = dev->reset_methods[i];
5372 0 : if (!m)
5373 : return -ENOTTY;
5374 :
5375 0 : rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5376 0 : if (!rc)
5377 : return 0;
5378 0 : if (rc != -ENOTTY)
5379 : return rc;
5380 : }
5381 :
5382 : return -ENOTTY;
5383 : }
5384 : EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5385 :
5386 : /**
5387 : * pci_init_reset_methods - check whether device can be safely reset
5388 : * and store supported reset mechanisms.
5389 : * @dev: PCI device to check for reset mechanisms
5390 : *
5391 : * Some devices allow an individual function to be reset without affecting
5392 : * other functions in the same device. The PCI device must be in D0-D3hot
5393 : * state.
5394 : *
5395 : * Stores reset mechanisms supported by device in reset_methods byte array
5396 : * which is a member of struct pci_dev.
5397 : */
5398 0 : void pci_init_reset_methods(struct pci_dev *dev)
5399 : {
5400 : int m, i, rc;
5401 :
5402 : BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS);
5403 :
5404 : might_sleep();
5405 :
5406 0 : i = 0;
5407 0 : for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5408 0 : rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);
5409 0 : if (!rc)
5410 0 : dev->reset_methods[i++] = m;
5411 0 : else if (rc != -ENOTTY)
5412 : break;
5413 : }
5414 :
5415 0 : dev->reset_methods[i] = 0;
5416 0 : }
5417 :
5418 : /**
5419 : * pci_reset_function - quiesce and reset a PCI device function
5420 : * @dev: PCI device to reset
5421 : *
5422 : * Some devices allow an individual function to be reset without affecting
5423 : * other functions in the same device. The PCI device must be responsive
5424 : * to PCI config space in order to use this function.
5425 : *
5426 : * This function does not just reset the PCI portion of a device, but
5427 : * clears all the state associated with the device. This function differs
5428 : * from __pci_reset_function_locked() in that it saves and restores device state
5429 : * over the reset and takes the PCI device lock.
5430 : *
5431 : * Returns 0 if the device function was successfully reset or negative if the
5432 : * device doesn't support resetting a single function.
5433 : */
5434 0 : int pci_reset_function(struct pci_dev *dev)
5435 : {
5436 : int rc;
5437 :
5438 0 : if (!pci_reset_supported(dev))
5439 : return -ENOTTY;
5440 :
5441 0 : pci_dev_lock(dev);
5442 0 : pci_dev_save_and_disable(dev);
5443 :
5444 0 : rc = __pci_reset_function_locked(dev);
5445 :
5446 0 : pci_dev_restore(dev);
5447 0 : pci_dev_unlock(dev);
5448 :
5449 0 : return rc;
5450 : }
5451 : EXPORT_SYMBOL_GPL(pci_reset_function);
5452 :
5453 : /**
5454 : * pci_reset_function_locked - quiesce and reset a PCI device function
5455 : * @dev: PCI device to reset
5456 : *
5457 : * Some devices allow an individual function to be reset without affecting
5458 : * other functions in the same device. The PCI device must be responsive
5459 : * to PCI config space in order to use this function.
5460 : *
5461 : * This function does not just reset the PCI portion of a device, but
5462 : * clears all the state associated with the device. This function differs
5463 : * from __pci_reset_function_locked() in that it saves and restores device state
5464 : * over the reset. It also differs from pci_reset_function() in that it
5465 : * requires the PCI device lock to be held.
5466 : *
5467 : * Returns 0 if the device function was successfully reset or negative if the
5468 : * device doesn't support resetting a single function.
5469 : */
5470 0 : int pci_reset_function_locked(struct pci_dev *dev)
5471 : {
5472 : int rc;
5473 :
5474 0 : if (!pci_reset_supported(dev))
5475 : return -ENOTTY;
5476 :
5477 0 : pci_dev_save_and_disable(dev);
5478 :
5479 0 : rc = __pci_reset_function_locked(dev);
5480 :
5481 0 : pci_dev_restore(dev);
5482 :
5483 0 : return rc;
5484 : }
5485 : EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5486 :
5487 : /**
5488 : * pci_try_reset_function - quiesce and reset a PCI device function
5489 : * @dev: PCI device to reset
5490 : *
5491 : * Same as above, except return -EAGAIN if unable to lock device.
5492 : */
5493 0 : int pci_try_reset_function(struct pci_dev *dev)
5494 : {
5495 : int rc;
5496 :
5497 0 : if (!pci_reset_supported(dev))
5498 : return -ENOTTY;
5499 :
5500 0 : if (!pci_dev_trylock(dev))
5501 : return -EAGAIN;
5502 :
5503 0 : pci_dev_save_and_disable(dev);
5504 0 : rc = __pci_reset_function_locked(dev);
5505 0 : pci_dev_restore(dev);
5506 0 : pci_dev_unlock(dev);
5507 :
5508 0 : return rc;
5509 : }
5510 : EXPORT_SYMBOL_GPL(pci_try_reset_function);
5511 :
5512 : /* Do any devices on or below this bus prevent a bus reset? */
5513 0 : static bool pci_bus_resetable(struct pci_bus *bus)
5514 : {
5515 : struct pci_dev *dev;
5516 :
5517 :
5518 0 : if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5519 : return false;
5520 :
5521 0 : list_for_each_entry(dev, &bus->devices, bus_list) {
5522 0 : if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5523 0 : (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5524 : return false;
5525 : }
5526 :
5527 : return true;
5528 : }
5529 :
5530 : /* Lock devices from the top of the tree down */
5531 0 : static void pci_bus_lock(struct pci_bus *bus)
5532 : {
5533 : struct pci_dev *dev;
5534 :
5535 0 : list_for_each_entry(dev, &bus->devices, bus_list) {
5536 0 : pci_dev_lock(dev);
5537 0 : if (dev->subordinate)
5538 0 : pci_bus_lock(dev->subordinate);
5539 : }
5540 0 : }
5541 :
5542 : /* Unlock devices from the bottom of the tree up */
5543 0 : static void pci_bus_unlock(struct pci_bus *bus)
5544 : {
5545 : struct pci_dev *dev;
5546 :
5547 0 : list_for_each_entry(dev, &bus->devices, bus_list) {
5548 0 : if (dev->subordinate)
5549 0 : pci_bus_unlock(dev->subordinate);
5550 0 : pci_dev_unlock(dev);
5551 : }
5552 0 : }
5553 :
5554 : /* Return 1 on successful lock, 0 on contention */
5555 0 : static int pci_bus_trylock(struct pci_bus *bus)
5556 : {
5557 : struct pci_dev *dev;
5558 :
5559 0 : list_for_each_entry(dev, &bus->devices, bus_list) {
5560 0 : if (!pci_dev_trylock(dev))
5561 : goto unlock;
5562 0 : if (dev->subordinate) {
5563 0 : if (!pci_bus_trylock(dev->subordinate)) {
5564 : pci_dev_unlock(dev);
5565 : goto unlock;
5566 : }
5567 : }
5568 : }
5569 : return 1;
5570 :
5571 : unlock:
5572 0 : list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5573 0 : if (dev->subordinate)
5574 0 : pci_bus_unlock(dev->subordinate);
5575 0 : pci_dev_unlock(dev);
5576 : }
5577 : return 0;
5578 : }
5579 :
5580 : /* Do any devices on or below this slot prevent a bus reset? */
5581 0 : static bool pci_slot_resetable(struct pci_slot *slot)
5582 : {
5583 : struct pci_dev *dev;
5584 :
5585 0 : if (slot->bus->self &&
5586 0 : (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5587 : return false;
5588 :
5589 0 : list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5590 0 : if (!dev->slot || dev->slot != slot)
5591 0 : continue;
5592 0 : if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5593 0 : (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5594 : return false;
5595 : }
5596 :
5597 : return true;
5598 : }
5599 :
5600 : /* Lock devices from the top of the tree down */
5601 0 : static void pci_slot_lock(struct pci_slot *slot)
5602 : {
5603 : struct pci_dev *dev;
5604 :
5605 0 : list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5606 0 : if (!dev->slot || dev->slot != slot)
5607 0 : continue;
5608 0 : pci_dev_lock(dev);
5609 0 : if (dev->subordinate)
5610 0 : pci_bus_lock(dev->subordinate);
5611 : }
5612 0 : }
5613 :
5614 : /* Unlock devices from the bottom of the tree up */
5615 0 : static void pci_slot_unlock(struct pci_slot *slot)
5616 : {
5617 : struct pci_dev *dev;
5618 :
5619 0 : list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5620 0 : if (!dev->slot || dev->slot != slot)
5621 0 : continue;
5622 0 : if (dev->subordinate)
5623 0 : pci_bus_unlock(dev->subordinate);
5624 : pci_dev_unlock(dev);
5625 : }
5626 0 : }
5627 :
5628 : /* Return 1 on successful lock, 0 on contention */
5629 0 : static int pci_slot_trylock(struct pci_slot *slot)
5630 : {
5631 : struct pci_dev *dev;
5632 :
5633 0 : list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5634 0 : if (!dev->slot || dev->slot != slot)
5635 0 : continue;
5636 0 : if (!pci_dev_trylock(dev))
5637 : goto unlock;
5638 0 : if (dev->subordinate) {
5639 0 : if (!pci_bus_trylock(dev->subordinate)) {
5640 : pci_dev_unlock(dev);
5641 : goto unlock;
5642 : }
5643 : }
5644 : }
5645 : return 1;
5646 :
5647 : unlock:
5648 0 : list_for_each_entry_continue_reverse(dev,
5649 : &slot->bus->devices, bus_list) {
5650 0 : if (!dev->slot || dev->slot != slot)
5651 0 : continue;
5652 0 : if (dev->subordinate)
5653 0 : pci_bus_unlock(dev->subordinate);
5654 : pci_dev_unlock(dev);
5655 : }
5656 : return 0;
5657 : }
5658 :
5659 : /*
5660 : * Save and disable devices from the top of the tree down while holding
5661 : * the @dev mutex lock for the entire tree.
5662 : */
5663 0 : static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5664 : {
5665 : struct pci_dev *dev;
5666 :
5667 0 : list_for_each_entry(dev, &bus->devices, bus_list) {
5668 0 : pci_dev_save_and_disable(dev);
5669 0 : if (dev->subordinate)
5670 0 : pci_bus_save_and_disable_locked(dev->subordinate);
5671 : }
5672 0 : }
5673 :
5674 : /*
5675 : * Restore devices from top of the tree down while holding @dev mutex lock
5676 : * for the entire tree. Parent bridges need to be restored before we can
5677 : * get to subordinate devices.
5678 : */
5679 0 : static void pci_bus_restore_locked(struct pci_bus *bus)
5680 : {
5681 : struct pci_dev *dev;
5682 :
5683 0 : list_for_each_entry(dev, &bus->devices, bus_list) {
5684 0 : pci_dev_restore(dev);
5685 0 : if (dev->subordinate)
5686 0 : pci_bus_restore_locked(dev->subordinate);
5687 : }
5688 0 : }
5689 :
5690 : /*
5691 : * Save and disable devices from the top of the tree down while holding
5692 : * the @dev mutex lock for the entire tree.
5693 : */
5694 0 : static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5695 : {
5696 : struct pci_dev *dev;
5697 :
5698 0 : list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5699 0 : if (!dev->slot || dev->slot != slot)
5700 0 : continue;
5701 0 : pci_dev_save_and_disable(dev);
5702 0 : if (dev->subordinate)
5703 0 : pci_bus_save_and_disable_locked(dev->subordinate);
5704 : }
5705 0 : }
5706 :
5707 : /*
5708 : * Restore devices from top of the tree down while holding @dev mutex lock
5709 : * for the entire tree. Parent bridges need to be restored before we can
5710 : * get to subordinate devices.
5711 : */
5712 0 : static void pci_slot_restore_locked(struct pci_slot *slot)
5713 : {
5714 : struct pci_dev *dev;
5715 :
5716 0 : list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5717 0 : if (!dev->slot || dev->slot != slot)
5718 0 : continue;
5719 0 : pci_dev_restore(dev);
5720 0 : if (dev->subordinate)
5721 0 : pci_bus_restore_locked(dev->subordinate);
5722 : }
5723 0 : }
5724 :
5725 0 : static int pci_slot_reset(struct pci_slot *slot, bool probe)
5726 : {
5727 : int rc;
5728 :
5729 0 : if (!slot || !pci_slot_resetable(slot))
5730 : return -ENOTTY;
5731 :
5732 0 : if (!probe)
5733 0 : pci_slot_lock(slot);
5734 :
5735 : might_sleep();
5736 :
5737 0 : rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5738 :
5739 0 : if (!probe)
5740 0 : pci_slot_unlock(slot);
5741 :
5742 : return rc;
5743 : }
5744 :
5745 : /**
5746 : * pci_probe_reset_slot - probe whether a PCI slot can be reset
5747 : * @slot: PCI slot to probe
5748 : *
5749 : * Return 0 if slot can be reset, negative if a slot reset is not supported.
5750 : */
5751 0 : int pci_probe_reset_slot(struct pci_slot *slot)
5752 : {
5753 0 : return pci_slot_reset(slot, PCI_RESET_PROBE);
5754 : }
5755 : EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5756 :
5757 : /**
5758 : * __pci_reset_slot - Try to reset a PCI slot
5759 : * @slot: PCI slot to reset
5760 : *
5761 : * A PCI bus may host multiple slots, each slot may support a reset mechanism
5762 : * independent of other slots. For instance, some slots may support slot power
5763 : * control. In the case of a 1:1 bus to slot architecture, this function may
5764 : * wrap the bus reset to avoid spurious slot related events such as hotplug.
5765 : * Generally a slot reset should be attempted before a bus reset. All of the
5766 : * function of the slot and any subordinate buses behind the slot are reset
5767 : * through this function. PCI config space of all devices in the slot and
5768 : * behind the slot is saved before and restored after reset.
5769 : *
5770 : * Same as above except return -EAGAIN if the slot cannot be locked
5771 : */
5772 0 : static int __pci_reset_slot(struct pci_slot *slot)
5773 : {
5774 : int rc;
5775 :
5776 0 : rc = pci_slot_reset(slot, PCI_RESET_PROBE);
5777 0 : if (rc)
5778 : return rc;
5779 :
5780 0 : if (pci_slot_trylock(slot)) {
5781 0 : pci_slot_save_and_disable_locked(slot);
5782 : might_sleep();
5783 0 : rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET);
5784 0 : pci_slot_restore_locked(slot);
5785 0 : pci_slot_unlock(slot);
5786 : } else
5787 : rc = -EAGAIN;
5788 :
5789 : return rc;
5790 : }
5791 :
5792 0 : static int pci_bus_reset(struct pci_bus *bus, bool probe)
5793 : {
5794 : int ret;
5795 :
5796 0 : if (!bus->self || !pci_bus_resetable(bus))
5797 : return -ENOTTY;
5798 :
5799 0 : if (probe)
5800 : return 0;
5801 :
5802 0 : pci_bus_lock(bus);
5803 :
5804 : might_sleep();
5805 :
5806 0 : ret = pci_bridge_secondary_bus_reset(bus->self);
5807 :
5808 0 : pci_bus_unlock(bus);
5809 :
5810 0 : return ret;
5811 : }
5812 :
5813 : /**
5814 : * pci_bus_error_reset - reset the bridge's subordinate bus
5815 : * @bridge: The parent device that connects to the bus to reset
5816 : *
5817 : * This function will first try to reset the slots on this bus if the method is
5818 : * available. If slot reset fails or is not available, this will fall back to a
5819 : * secondary bus reset.
5820 : */
5821 0 : int pci_bus_error_reset(struct pci_dev *bridge)
5822 : {
5823 0 : struct pci_bus *bus = bridge->subordinate;
5824 : struct pci_slot *slot;
5825 :
5826 0 : if (!bus)
5827 : return -ENOTTY;
5828 :
5829 0 : mutex_lock(&pci_slot_mutex);
5830 0 : if (list_empty(&bus->slots))
5831 : goto bus_reset;
5832 :
5833 0 : list_for_each_entry(slot, &bus->slots, list)
5834 0 : if (pci_probe_reset_slot(slot))
5835 : goto bus_reset;
5836 :
5837 0 : list_for_each_entry(slot, &bus->slots, list)
5838 0 : if (pci_slot_reset(slot, PCI_RESET_DO_RESET))
5839 : goto bus_reset;
5840 :
5841 0 : mutex_unlock(&pci_slot_mutex);
5842 0 : return 0;
5843 : bus_reset:
5844 0 : mutex_unlock(&pci_slot_mutex);
5845 0 : return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);
5846 : }
5847 :
5848 : /**
5849 : * pci_probe_reset_bus - probe whether a PCI bus can be reset
5850 : * @bus: PCI bus to probe
5851 : *
5852 : * Return 0 if bus can be reset, negative if a bus reset is not supported.
5853 : */
5854 0 : int pci_probe_reset_bus(struct pci_bus *bus)
5855 : {
5856 0 : return pci_bus_reset(bus, PCI_RESET_PROBE);
5857 : }
5858 : EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5859 :
5860 : /**
5861 : * __pci_reset_bus - Try to reset a PCI bus
5862 : * @bus: top level PCI bus to reset
5863 : *
5864 : * Same as above except return -EAGAIN if the bus cannot be locked
5865 : */
5866 0 : static int __pci_reset_bus(struct pci_bus *bus)
5867 : {
5868 : int rc;
5869 :
5870 0 : rc = pci_bus_reset(bus, PCI_RESET_PROBE);
5871 0 : if (rc)
5872 : return rc;
5873 :
5874 0 : if (pci_bus_trylock(bus)) {
5875 0 : pci_bus_save_and_disable_locked(bus);
5876 : might_sleep();
5877 0 : rc = pci_bridge_secondary_bus_reset(bus->self);
5878 0 : pci_bus_restore_locked(bus);
5879 0 : pci_bus_unlock(bus);
5880 : } else
5881 : rc = -EAGAIN;
5882 :
5883 : return rc;
5884 : }
5885 :
5886 : /**
5887 : * pci_reset_bus - Try to reset a PCI bus
5888 : * @pdev: top level PCI device to reset via slot/bus
5889 : *
5890 : * Same as above except return -EAGAIN if the bus cannot be locked
5891 : */
5892 0 : int pci_reset_bus(struct pci_dev *pdev)
5893 : {
5894 0 : return (!pci_probe_reset_slot(pdev->slot)) ?
5895 0 : __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5896 : }
5897 : EXPORT_SYMBOL_GPL(pci_reset_bus);
5898 :
5899 : /**
5900 : * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5901 : * @dev: PCI device to query
5902 : *
5903 : * Returns mmrbc: maximum designed memory read count in bytes or
5904 : * appropriate error value.
5905 : */
5906 0 : int pcix_get_max_mmrbc(struct pci_dev *dev)
5907 : {
5908 : int cap;
5909 : u32 stat;
5910 :
5911 0 : cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5912 0 : if (!cap)
5913 : return -EINVAL;
5914 :
5915 0 : if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5916 : return -EINVAL;
5917 :
5918 0 : return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5919 : }
5920 : EXPORT_SYMBOL(pcix_get_max_mmrbc);
5921 :
5922 : /**
5923 : * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5924 : * @dev: PCI device to query
5925 : *
5926 : * Returns mmrbc: maximum memory read count in bytes or appropriate error
5927 : * value.
5928 : */
5929 0 : int pcix_get_mmrbc(struct pci_dev *dev)
5930 : {
5931 : int cap;
5932 : u16 cmd;
5933 :
5934 0 : cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5935 0 : if (!cap)
5936 : return -EINVAL;
5937 :
5938 0 : if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5939 : return -EINVAL;
5940 :
5941 0 : return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5942 : }
5943 : EXPORT_SYMBOL(pcix_get_mmrbc);
5944 :
5945 : /**
5946 : * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5947 : * @dev: PCI device to query
5948 : * @mmrbc: maximum memory read count in bytes
5949 : * valid values are 512, 1024, 2048, 4096
5950 : *
5951 : * If possible sets maximum memory read byte count, some bridges have errata
5952 : * that prevent this.
5953 : */
5954 0 : int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5955 : {
5956 : int cap;
5957 : u32 stat, v, o;
5958 : u16 cmd;
5959 :
5960 0 : if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5961 : return -EINVAL;
5962 :
5963 0 : v = ffs(mmrbc) - 10;
5964 :
5965 0 : cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5966 0 : if (!cap)
5967 : return -EINVAL;
5968 :
5969 0 : if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5970 : return -EINVAL;
5971 :
5972 0 : if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5973 : return -E2BIG;
5974 :
5975 0 : if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5976 : return -EINVAL;
5977 :
5978 0 : o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5979 0 : if (o != v) {
5980 0 : if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5981 : return -EIO;
5982 :
5983 0 : cmd &= ~PCI_X_CMD_MAX_READ;
5984 0 : cmd |= v << 2;
5985 0 : if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5986 : return -EIO;
5987 : }
5988 : return 0;
5989 : }
5990 : EXPORT_SYMBOL(pcix_set_mmrbc);
5991 :
5992 : /**
5993 : * pcie_get_readrq - get PCI Express read request size
5994 : * @dev: PCI device to query
5995 : *
5996 : * Returns maximum memory read request in bytes or appropriate error value.
5997 : */
5998 0 : int pcie_get_readrq(struct pci_dev *dev)
5999 : {
6000 : u16 ctl;
6001 :
6002 0 : pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6003 :
6004 0 : return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6005 : }
6006 : EXPORT_SYMBOL(pcie_get_readrq);
6007 :
6008 : /**
6009 : * pcie_set_readrq - set PCI Express maximum memory read request
6010 : * @dev: PCI device to query
6011 : * @rq: maximum memory read count in bytes
6012 : * valid values are 128, 256, 512, 1024, 2048, 4096
6013 : *
6014 : * If possible sets maximum memory read request in bytes
6015 : */
6016 0 : int pcie_set_readrq(struct pci_dev *dev, int rq)
6017 : {
6018 : u16 v;
6019 : int ret;
6020 0 : struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
6021 :
6022 0 : if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
6023 : return -EINVAL;
6024 :
6025 : /*
6026 : * If using the "performance" PCIe config, we clamp the read rq
6027 : * size to the max packet size to keep the host bridge from
6028 : * generating requests larger than we can cope with.
6029 : */
6030 0 : if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
6031 0 : int mps = pcie_get_mps(dev);
6032 :
6033 0 : if (mps < rq)
6034 0 : rq = mps;
6035 : }
6036 :
6037 0 : v = (ffs(rq) - 8) << 12;
6038 :
6039 0 : if (bridge->no_inc_mrrs) {
6040 0 : int max_mrrs = pcie_get_readrq(dev);
6041 :
6042 0 : if (rq > max_mrrs) {
6043 0 : pci_info(dev, "can't set Max_Read_Request_Size to %d; max is %d\n", rq, max_mrrs);
6044 0 : return -EINVAL;
6045 : }
6046 : }
6047 :
6048 0 : ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6049 : PCI_EXP_DEVCTL_READRQ, v);
6050 :
6051 : return pcibios_err_to_errno(ret);
6052 : }
6053 : EXPORT_SYMBOL(pcie_set_readrq);
6054 :
6055 : /**
6056 : * pcie_get_mps - get PCI Express maximum payload size
6057 : * @dev: PCI device to query
6058 : *
6059 : * Returns maximum payload size in bytes
6060 : */
6061 0 : int pcie_get_mps(struct pci_dev *dev)
6062 : {
6063 : u16 ctl;
6064 :
6065 0 : pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6066 :
6067 0 : return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6068 : }
6069 : EXPORT_SYMBOL(pcie_get_mps);
6070 :
6071 : /**
6072 : * pcie_set_mps - set PCI Express maximum payload size
6073 : * @dev: PCI device to query
6074 : * @mps: maximum payload size in bytes
6075 : * valid values are 128, 256, 512, 1024, 2048, 4096
6076 : *
6077 : * If possible sets maximum payload size
6078 : */
6079 0 : int pcie_set_mps(struct pci_dev *dev, int mps)
6080 : {
6081 : u16 v;
6082 : int ret;
6083 :
6084 0 : if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
6085 : return -EINVAL;
6086 :
6087 0 : v = ffs(mps) - 8;
6088 0 : if (v > dev->pcie_mpss)
6089 : return -EINVAL;
6090 0 : v <<= 5;
6091 :
6092 0 : ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6093 : PCI_EXP_DEVCTL_PAYLOAD, v);
6094 :
6095 : return pcibios_err_to_errno(ret);
6096 : }
6097 : EXPORT_SYMBOL(pcie_set_mps);
6098 :
6099 : /**
6100 : * pcie_bandwidth_available - determine minimum link settings of a PCIe
6101 : * device and its bandwidth limitation
6102 : * @dev: PCI device to query
6103 : * @limiting_dev: storage for device causing the bandwidth limitation
6104 : * @speed: storage for speed of limiting device
6105 : * @width: storage for width of limiting device
6106 : *
6107 : * Walk up the PCI device chain and find the point where the minimum
6108 : * bandwidth is available. Return the bandwidth available there and (if
6109 : * limiting_dev, speed, and width pointers are supplied) information about
6110 : * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6111 : * raw bandwidth.
6112 : */
6113 0 : u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
6114 : enum pci_bus_speed *speed,
6115 : enum pcie_link_width *width)
6116 : {
6117 : u16 lnksta;
6118 : enum pci_bus_speed next_speed;
6119 : enum pcie_link_width next_width;
6120 : u32 bw, next_bw;
6121 :
6122 0 : if (speed)
6123 0 : *speed = PCI_SPEED_UNKNOWN;
6124 0 : if (width)
6125 0 : *width = PCIE_LNK_WIDTH_UNKNOWN;
6126 :
6127 : bw = 0;
6128 :
6129 0 : while (dev) {
6130 0 : pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
6131 :
6132 0 : next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
6133 0 : next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
6134 : PCI_EXP_LNKSTA_NLW_SHIFT;
6135 :
6136 0 : next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
6137 :
6138 : /* Check if current device limits the total bandwidth */
6139 0 : if (!bw || next_bw <= bw) {
6140 0 : bw = next_bw;
6141 :
6142 0 : if (limiting_dev)
6143 0 : *limiting_dev = dev;
6144 0 : if (speed)
6145 0 : *speed = next_speed;
6146 0 : if (width)
6147 0 : *width = next_width;
6148 : }
6149 :
6150 0 : dev = pci_upstream_bridge(dev);
6151 : }
6152 :
6153 0 : return bw;
6154 : }
6155 : EXPORT_SYMBOL(pcie_bandwidth_available);
6156 :
6157 : /**
6158 : * pcie_get_speed_cap - query for the PCI device's link speed capability
6159 : * @dev: PCI device to query
6160 : *
6161 : * Query the PCI device speed capability. Return the maximum link speed
6162 : * supported by the device.
6163 : */
6164 0 : enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6165 : {
6166 : u32 lnkcap2, lnkcap;
6167 :
6168 : /*
6169 : * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6170 : * implementation note there recommends using the Supported Link
6171 : * Speeds Vector in Link Capabilities 2 when supported.
6172 : *
6173 : * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6174 : * should use the Supported Link Speeds field in Link Capabilities,
6175 : * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6176 : */
6177 0 : pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6178 :
6179 : /* PCIe r3.0-compliant */
6180 0 : if (lnkcap2)
6181 0 : return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
6182 :
6183 0 : pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6184 0 : if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6185 : return PCIE_SPEED_5_0GT;
6186 0 : else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6187 : return PCIE_SPEED_2_5GT;
6188 :
6189 0 : return PCI_SPEED_UNKNOWN;
6190 : }
6191 : EXPORT_SYMBOL(pcie_get_speed_cap);
6192 :
6193 : /**
6194 : * pcie_get_width_cap - query for the PCI device's link width capability
6195 : * @dev: PCI device to query
6196 : *
6197 : * Query the PCI device width capability. Return the maximum link width
6198 : * supported by the device.
6199 : */
6200 0 : enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
6201 : {
6202 : u32 lnkcap;
6203 :
6204 0 : pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6205 0 : if (lnkcap)
6206 0 : return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
6207 :
6208 : return PCIE_LNK_WIDTH_UNKNOWN;
6209 : }
6210 : EXPORT_SYMBOL(pcie_get_width_cap);
6211 :
6212 : /**
6213 : * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6214 : * @dev: PCI device
6215 : * @speed: storage for link speed
6216 : * @width: storage for link width
6217 : *
6218 : * Calculate a PCI device's link bandwidth by querying for its link speed
6219 : * and width, multiplying them, and applying encoding overhead. The result
6220 : * is in Mb/s, i.e., megabits/second of raw bandwidth.
6221 : */
6222 0 : u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6223 : enum pcie_link_width *width)
6224 : {
6225 0 : *speed = pcie_get_speed_cap(dev);
6226 0 : *width = pcie_get_width_cap(dev);
6227 :
6228 0 : if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6229 : return 0;
6230 :
6231 0 : return *width * PCIE_SPEED2MBS_ENC(*speed);
6232 : }
6233 :
6234 : /**
6235 : * __pcie_print_link_status - Report the PCI device's link speed and width
6236 : * @dev: PCI device to query
6237 : * @verbose: Print info even when enough bandwidth is available
6238 : *
6239 : * If the available bandwidth at the device is less than the device is
6240 : * capable of, report the device's maximum possible bandwidth and the
6241 : * upstream link that limits its performance. If @verbose, always print
6242 : * the available bandwidth, even if the device isn't constrained.
6243 : */
6244 0 : void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6245 : {
6246 : enum pcie_link_width width, width_cap;
6247 : enum pci_bus_speed speed, speed_cap;
6248 0 : struct pci_dev *limiting_dev = NULL;
6249 : u32 bw_avail, bw_cap;
6250 :
6251 0 : bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6252 0 : bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6253 :
6254 0 : if (bw_avail >= bw_cap && verbose)
6255 0 : pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6256 : bw_cap / 1000, bw_cap % 1000,
6257 : pci_speed_string(speed_cap), width_cap);
6258 0 : else if (bw_avail < bw_cap)
6259 0 : pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6260 : bw_avail / 1000, bw_avail % 1000,
6261 : pci_speed_string(speed), width,
6262 : limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6263 : bw_cap / 1000, bw_cap % 1000,
6264 : pci_speed_string(speed_cap), width_cap);
6265 0 : }
6266 :
6267 : /**
6268 : * pcie_print_link_status - Report the PCI device's link speed and width
6269 : * @dev: PCI device to query
6270 : *
6271 : * Report the available bandwidth at the device.
6272 : */
6273 0 : void pcie_print_link_status(struct pci_dev *dev)
6274 : {
6275 0 : __pcie_print_link_status(dev, true);
6276 0 : }
6277 : EXPORT_SYMBOL(pcie_print_link_status);
6278 :
6279 : /**
6280 : * pci_select_bars - Make BAR mask from the type of resource
6281 : * @dev: the PCI device for which BAR mask is made
6282 : * @flags: resource type mask to be selected
6283 : *
6284 : * This helper routine makes bar mask from the type of resource.
6285 : */
6286 0 : int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6287 : {
6288 0 : int i, bars = 0;
6289 0 : for (i = 0; i < PCI_NUM_RESOURCES; i++)
6290 0 : if (pci_resource_flags(dev, i) & flags)
6291 0 : bars |= (1 << i);
6292 0 : return bars;
6293 : }
6294 : EXPORT_SYMBOL(pci_select_bars);
6295 :
6296 : /* Some architectures require additional programming to enable VGA */
6297 : static arch_set_vga_state_t arch_set_vga_state;
6298 :
6299 0 : void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6300 : {
6301 0 : arch_set_vga_state = func; /* NULL disables */
6302 0 : }
6303 :
6304 : static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6305 : unsigned int command_bits, u32 flags)
6306 : {
6307 0 : if (arch_set_vga_state)
6308 0 : return arch_set_vga_state(dev, decode, command_bits,
6309 : flags);
6310 : return 0;
6311 : }
6312 :
6313 : /**
6314 : * pci_set_vga_state - set VGA decode state on device and parents if requested
6315 : * @dev: the PCI device
6316 : * @decode: true = enable decoding, false = disable decoding
6317 : * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6318 : * @flags: traverse ancestors and change bridges
6319 : * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6320 : */
6321 0 : int pci_set_vga_state(struct pci_dev *dev, bool decode,
6322 : unsigned int command_bits, u32 flags)
6323 : {
6324 : struct pci_bus *bus;
6325 : struct pci_dev *bridge;
6326 : u16 cmd;
6327 : int rc;
6328 :
6329 0 : WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6330 :
6331 : /* ARCH specific VGA enables */
6332 0 : rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6333 0 : if (rc)
6334 : return rc;
6335 :
6336 0 : if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6337 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
6338 0 : if (decode)
6339 0 : cmd |= command_bits;
6340 : else
6341 0 : cmd &= ~command_bits;
6342 0 : pci_write_config_word(dev, PCI_COMMAND, cmd);
6343 : }
6344 :
6345 0 : if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6346 : return 0;
6347 :
6348 0 : bus = dev->bus;
6349 0 : while (bus) {
6350 0 : bridge = bus->self;
6351 0 : if (bridge) {
6352 0 : pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6353 : &cmd);
6354 0 : if (decode)
6355 0 : cmd |= PCI_BRIDGE_CTL_VGA;
6356 : else
6357 0 : cmd &= ~PCI_BRIDGE_CTL_VGA;
6358 0 : pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6359 : cmd);
6360 : }
6361 0 : bus = bus->parent;
6362 : }
6363 : return 0;
6364 : }
6365 :
6366 : #ifdef CONFIG_ACPI
6367 : bool pci_pr3_present(struct pci_dev *pdev)
6368 : {
6369 : struct acpi_device *adev;
6370 :
6371 : if (acpi_disabled)
6372 : return false;
6373 :
6374 : adev = ACPI_COMPANION(&pdev->dev);
6375 : if (!adev)
6376 : return false;
6377 :
6378 : return adev->power.flags.power_resources &&
6379 : acpi_has_method(adev->handle, "_PR3");
6380 : }
6381 : EXPORT_SYMBOL_GPL(pci_pr3_present);
6382 : #endif
6383 :
6384 : /**
6385 : * pci_add_dma_alias - Add a DMA devfn alias for a device
6386 : * @dev: the PCI device for which alias is added
6387 : * @devfn_from: alias slot and function
6388 : * @nr_devfns: number of subsequent devfns to alias
6389 : *
6390 : * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6391 : * which is used to program permissible bus-devfn source addresses for DMA
6392 : * requests in an IOMMU. These aliases factor into IOMMU group creation
6393 : * and are useful for devices generating DMA requests beyond or different
6394 : * from their logical bus-devfn. Examples include device quirks where the
6395 : * device simply uses the wrong devfn, as well as non-transparent bridges
6396 : * where the alias may be a proxy for devices in another domain.
6397 : *
6398 : * IOMMU group creation is performed during device discovery or addition,
6399 : * prior to any potential DMA mapping and therefore prior to driver probing
6400 : * (especially for userspace assigned devices where IOMMU group definition
6401 : * cannot be left as a userspace activity). DMA aliases should therefore
6402 : * be configured via quirks, such as the PCI fixup header quirk.
6403 : */
6404 0 : void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from,
6405 : unsigned int nr_devfns)
6406 : {
6407 : int devfn_to;
6408 :
6409 0 : nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from);
6410 0 : devfn_to = devfn_from + nr_devfns - 1;
6411 :
6412 0 : if (!dev->dma_alias_mask)
6413 0 : dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6414 0 : if (!dev->dma_alias_mask) {
6415 0 : pci_warn(dev, "Unable to allocate DMA alias mask\n");
6416 0 : return;
6417 : }
6418 :
6419 0 : bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6420 :
6421 0 : if (nr_devfns == 1)
6422 0 : pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6423 : PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6424 0 : else if (nr_devfns > 1)
6425 0 : pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6426 : PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6427 : PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6428 : }
6429 :
6430 0 : bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6431 : {
6432 0 : return (dev1->dma_alias_mask &&
6433 0 : test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6434 0 : (dev2->dma_alias_mask &&
6435 0 : test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6436 0 : pci_real_dma_dev(dev1) == dev2 ||
6437 0 : pci_real_dma_dev(dev2) == dev1;
6438 : }
6439 :
6440 0 : bool pci_device_is_present(struct pci_dev *pdev)
6441 : {
6442 : u32 v;
6443 :
6444 : /* Check PF if pdev is a VF, since VF Vendor/Device IDs are 0xffff */
6445 0 : pdev = pci_physfn(pdev);
6446 0 : if (pci_dev_is_disconnected(pdev))
6447 : return false;
6448 0 : return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6449 : }
6450 : EXPORT_SYMBOL_GPL(pci_device_is_present);
6451 :
6452 0 : void pci_ignore_hotplug(struct pci_dev *dev)
6453 : {
6454 0 : struct pci_dev *bridge = dev->bus->self;
6455 :
6456 0 : dev->ignore_hotplug = 1;
6457 : /* Propagate the "ignore hotplug" setting to the parent bridge. */
6458 0 : if (bridge)
6459 0 : bridge->ignore_hotplug = 1;
6460 0 : }
6461 : EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6462 :
6463 : /**
6464 : * pci_real_dma_dev - Get PCI DMA device for PCI device
6465 : * @dev: the PCI device that may have a PCI DMA alias
6466 : *
6467 : * Permits the platform to provide architecture-specific functionality to
6468 : * devices needing to alias DMA to another PCI device on another PCI bus. If
6469 : * the PCI device is on the same bus, it is recommended to use
6470 : * pci_add_dma_alias(). This is the default implementation. Architecture
6471 : * implementations can override this.
6472 : */
6473 0 : struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6474 : {
6475 0 : return dev;
6476 : }
6477 :
6478 0 : resource_size_t __weak pcibios_default_alignment(void)
6479 : {
6480 0 : return 0;
6481 : }
6482 :
6483 : /*
6484 : * Arches that don't want to expose struct resource to userland as-is in
6485 : * sysfs and /proc can implement their own pci_resource_to_user().
6486 : */
6487 0 : void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6488 : const struct resource *rsrc,
6489 : resource_size_t *start, resource_size_t *end)
6490 : {
6491 0 : *start = rsrc->start;
6492 0 : *end = rsrc->end;
6493 0 : }
6494 :
6495 : static char *resource_alignment_param;
6496 : static DEFINE_SPINLOCK(resource_alignment_lock);
6497 :
6498 : /**
6499 : * pci_specified_resource_alignment - get resource alignment specified by user.
6500 : * @dev: the PCI device to get
6501 : * @resize: whether or not to change resources' size when reassigning alignment
6502 : *
6503 : * RETURNS: Resource alignment if it is specified.
6504 : * Zero if it is not specified.
6505 : */
6506 0 : static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6507 : bool *resize)
6508 : {
6509 : int align_order, count;
6510 0 : resource_size_t align = pcibios_default_alignment();
6511 : const char *p;
6512 : int ret;
6513 :
6514 0 : spin_lock(&resource_alignment_lock);
6515 0 : p = resource_alignment_param;
6516 0 : if (!p || !*p)
6517 : goto out;
6518 0 : if (pci_has_flag(PCI_PROBE_ONLY)) {
6519 0 : align = 0;
6520 0 : pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6521 : goto out;
6522 : }
6523 :
6524 0 : while (*p) {
6525 0 : count = 0;
6526 0 : if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6527 0 : p[count] == '@') {
6528 0 : p += count + 1;
6529 0 : if (align_order > 63) {
6530 0 : pr_err("PCI: Invalid requested alignment (order %d)\n",
6531 : align_order);
6532 0 : align_order = PAGE_SHIFT;
6533 : }
6534 : } else {
6535 0 : align_order = PAGE_SHIFT;
6536 : }
6537 :
6538 0 : ret = pci_dev_str_match(dev, p, &p);
6539 0 : if (ret == 1) {
6540 0 : *resize = true;
6541 0 : align = 1ULL << align_order;
6542 0 : break;
6543 0 : } else if (ret < 0) {
6544 0 : pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6545 : p);
6546 0 : break;
6547 : }
6548 :
6549 0 : if (*p != ';' && *p != ',') {
6550 : /* End of param or invalid format */
6551 : break;
6552 : }
6553 0 : p++;
6554 : }
6555 : out:
6556 0 : spin_unlock(&resource_alignment_lock);
6557 0 : return align;
6558 : }
6559 :
6560 0 : static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6561 : resource_size_t align, bool resize)
6562 : {
6563 0 : struct resource *r = &dev->resource[bar];
6564 : resource_size_t size;
6565 :
6566 0 : if (!(r->flags & IORESOURCE_MEM))
6567 : return;
6568 :
6569 0 : if (r->flags & IORESOURCE_PCI_FIXED) {
6570 0 : pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6571 : bar, r, (unsigned long long)align);
6572 0 : return;
6573 : }
6574 :
6575 0 : size = resource_size(r);
6576 0 : if (size >= align)
6577 : return;
6578 :
6579 : /*
6580 : * Increase the alignment of the resource. There are two ways we
6581 : * can do this:
6582 : *
6583 : * 1) Increase the size of the resource. BARs are aligned on their
6584 : * size, so when we reallocate space for this resource, we'll
6585 : * allocate it with the larger alignment. This also prevents
6586 : * assignment of any other BARs inside the alignment region, so
6587 : * if we're requesting page alignment, this means no other BARs
6588 : * will share the page.
6589 : *
6590 : * The disadvantage is that this makes the resource larger than
6591 : * the hardware BAR, which may break drivers that compute things
6592 : * based on the resource size, e.g., to find registers at a
6593 : * fixed offset before the end of the BAR.
6594 : *
6595 : * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6596 : * set r->start to the desired alignment. By itself this
6597 : * doesn't prevent other BARs being put inside the alignment
6598 : * region, but if we realign *every* resource of every device in
6599 : * the system, none of them will share an alignment region.
6600 : *
6601 : * When the user has requested alignment for only some devices via
6602 : * the "pci=resource_alignment" argument, "resize" is true and we
6603 : * use the first method. Otherwise we assume we're aligning all
6604 : * devices and we use the second.
6605 : */
6606 :
6607 0 : pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6608 : bar, r, (unsigned long long)align);
6609 :
6610 0 : if (resize) {
6611 0 : r->start = 0;
6612 0 : r->end = align - 1;
6613 : } else {
6614 0 : r->flags &= ~IORESOURCE_SIZEALIGN;
6615 0 : r->flags |= IORESOURCE_STARTALIGN;
6616 0 : r->start = align;
6617 0 : r->end = r->start + size - 1;
6618 : }
6619 0 : r->flags |= IORESOURCE_UNSET;
6620 : }
6621 :
6622 : /*
6623 : * This function disables memory decoding and releases memory resources
6624 : * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6625 : * It also rounds up size to specified alignment.
6626 : * Later on, the kernel will assign page-aligned memory resource back
6627 : * to the device.
6628 : */
6629 0 : void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6630 : {
6631 : int i;
6632 : struct resource *r;
6633 : resource_size_t align;
6634 : u16 command;
6635 0 : bool resize = false;
6636 :
6637 : /*
6638 : * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6639 : * 3.4.1.11. Their resources are allocated from the space
6640 : * described by the VF BARx register in the PF's SR-IOV capability.
6641 : * We can't influence their alignment here.
6642 : */
6643 0 : if (dev->is_virtfn)
6644 0 : return;
6645 :
6646 : /* check if specified PCI is target device to reassign */
6647 0 : align = pci_specified_resource_alignment(dev, &resize);
6648 0 : if (!align)
6649 : return;
6650 :
6651 0 : if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6652 0 : (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6653 0 : pci_warn(dev, "Can't reassign resources to host bridge\n");
6654 0 : return;
6655 : }
6656 :
6657 0 : pci_read_config_word(dev, PCI_COMMAND, &command);
6658 0 : command &= ~PCI_COMMAND_MEMORY;
6659 0 : pci_write_config_word(dev, PCI_COMMAND, command);
6660 :
6661 0 : for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6662 0 : pci_request_resource_alignment(dev, i, align, resize);
6663 :
6664 : /*
6665 : * Need to disable bridge's resource window,
6666 : * to enable the kernel to reassign new resource
6667 : * window later on.
6668 : */
6669 0 : if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6670 0 : for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6671 0 : r = &dev->resource[i];
6672 0 : if (!(r->flags & IORESOURCE_MEM))
6673 0 : continue;
6674 0 : r->flags |= IORESOURCE_UNSET;
6675 0 : r->end = resource_size(r) - 1;
6676 0 : r->start = 0;
6677 : }
6678 0 : pci_disable_bridge_window(dev);
6679 : }
6680 : }
6681 :
6682 0 : static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6683 : {
6684 0 : size_t count = 0;
6685 :
6686 0 : spin_lock(&resource_alignment_lock);
6687 0 : if (resource_alignment_param)
6688 0 : count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6689 0 : spin_unlock(&resource_alignment_lock);
6690 :
6691 0 : return count;
6692 : }
6693 :
6694 0 : static ssize_t resource_alignment_store(struct bus_type *bus,
6695 : const char *buf, size_t count)
6696 : {
6697 : char *param, *old, *end;
6698 :
6699 0 : if (count >= (PAGE_SIZE - 1))
6700 : return -EINVAL;
6701 :
6702 0 : param = kstrndup(buf, count, GFP_KERNEL);
6703 0 : if (!param)
6704 : return -ENOMEM;
6705 :
6706 0 : end = strchr(param, '\n');
6707 0 : if (end)
6708 0 : *end = '\0';
6709 :
6710 0 : spin_lock(&resource_alignment_lock);
6711 0 : old = resource_alignment_param;
6712 0 : if (strlen(param)) {
6713 0 : resource_alignment_param = param;
6714 : } else {
6715 0 : kfree(param);
6716 0 : resource_alignment_param = NULL;
6717 : }
6718 0 : spin_unlock(&resource_alignment_lock);
6719 :
6720 0 : kfree(old);
6721 :
6722 0 : return count;
6723 : }
6724 :
6725 : static BUS_ATTR_RW(resource_alignment);
6726 :
6727 1 : static int __init pci_resource_alignment_sysfs_init(void)
6728 : {
6729 1 : return bus_create_file(&pci_bus_type,
6730 : &bus_attr_resource_alignment);
6731 : }
6732 : late_initcall(pci_resource_alignment_sysfs_init);
6733 :
6734 : static void pci_no_domains(void)
6735 : {
6736 : #ifdef CONFIG_PCI_DOMAINS
6737 : pci_domains_supported = 0;
6738 : #endif
6739 : }
6740 :
6741 : #ifdef CONFIG_PCI_DOMAINS_GENERIC
6742 : static DEFINE_IDA(pci_domain_nr_static_ida);
6743 : static DEFINE_IDA(pci_domain_nr_dynamic_ida);
6744 :
6745 : static void of_pci_reserve_static_domain_nr(void)
6746 : {
6747 : struct device_node *np;
6748 : int domain_nr;
6749 :
6750 : for_each_node_by_type(np, "pci") {
6751 : domain_nr = of_get_pci_domain_nr(np);
6752 : if (domain_nr < 0)
6753 : continue;
6754 : /*
6755 : * Permanently allocate domain_nr in dynamic_ida
6756 : * to prevent it from dynamic allocation.
6757 : */
6758 : ida_alloc_range(&pci_domain_nr_dynamic_ida,
6759 : domain_nr, domain_nr, GFP_KERNEL);
6760 : }
6761 : }
6762 :
6763 : static int of_pci_bus_find_domain_nr(struct device *parent)
6764 : {
6765 : static bool static_domains_reserved = false;
6766 : int domain_nr;
6767 :
6768 : /* On the first call scan device tree for static allocations. */
6769 : if (!static_domains_reserved) {
6770 : of_pci_reserve_static_domain_nr();
6771 : static_domains_reserved = true;
6772 : }
6773 :
6774 : if (parent) {
6775 : /*
6776 : * If domain is in DT, allocate it in static IDA. This
6777 : * prevents duplicate static allocations in case of errors
6778 : * in DT.
6779 : */
6780 : domain_nr = of_get_pci_domain_nr(parent->of_node);
6781 : if (domain_nr >= 0)
6782 : return ida_alloc_range(&pci_domain_nr_static_ida,
6783 : domain_nr, domain_nr,
6784 : GFP_KERNEL);
6785 : }
6786 :
6787 : /*
6788 : * If domain was not specified in DT, choose a free ID from dynamic
6789 : * allocations. All domain numbers from DT are permanently in
6790 : * dynamic allocations to prevent assigning them to other DT nodes
6791 : * without static domain.
6792 : */
6793 : return ida_alloc(&pci_domain_nr_dynamic_ida, GFP_KERNEL);
6794 : }
6795 :
6796 : static void of_pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
6797 : {
6798 : if (bus->domain_nr < 0)
6799 : return;
6800 :
6801 : /* Release domain from IDA where it was allocated. */
6802 : if (of_get_pci_domain_nr(parent->of_node) == bus->domain_nr)
6803 : ida_free(&pci_domain_nr_static_ida, bus->domain_nr);
6804 : else
6805 : ida_free(&pci_domain_nr_dynamic_ida, bus->domain_nr);
6806 : }
6807 :
6808 : int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6809 : {
6810 : return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6811 : acpi_pci_bus_find_domain_nr(bus);
6812 : }
6813 :
6814 : void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
6815 : {
6816 : if (!acpi_disabled)
6817 : return;
6818 : of_pci_bus_release_domain_nr(bus, parent);
6819 : }
6820 : #endif
6821 :
6822 : /**
6823 : * pci_ext_cfg_avail - can we access extended PCI config space?
6824 : *
6825 : * Returns 1 if we can access PCI extended config space (offsets
6826 : * greater than 0xff). This is the default implementation. Architecture
6827 : * implementations can override this.
6828 : */
6829 0 : int __weak pci_ext_cfg_avail(void)
6830 : {
6831 0 : return 1;
6832 : }
6833 :
6834 0 : void __weak pci_fixup_cardbus(struct pci_bus *bus)
6835 : {
6836 0 : }
6837 : EXPORT_SYMBOL(pci_fixup_cardbus);
6838 :
6839 0 : static int __init pci_setup(char *str)
6840 : {
6841 0 : while (str) {
6842 0 : char *k = strchr(str, ',');
6843 0 : if (k)
6844 0 : *k++ = 0;
6845 0 : if (*str && (str = pcibios_setup(str)) && *str) {
6846 0 : if (!strcmp(str, "nomsi")) {
6847 0 : pci_no_msi();
6848 0 : } else if (!strncmp(str, "noats", 5)) {
6849 0 : pr_info("PCIe: ATS is disabled\n");
6850 0 : pcie_ats_disabled = true;
6851 0 : } else if (!strcmp(str, "noaer")) {
6852 : pci_no_aer();
6853 0 : } else if (!strcmp(str, "earlydump")) {
6854 0 : pci_early_dump = true;
6855 0 : } else if (!strncmp(str, "realloc=", 8)) {
6856 0 : pci_realloc_get_opt(str + 8);
6857 0 : } else if (!strncmp(str, "realloc", 7)) {
6858 0 : pci_realloc_get_opt("on");
6859 0 : } else if (!strcmp(str, "nodomains")) {
6860 : pci_no_domains();
6861 0 : } else if (!strncmp(str, "noari", 5)) {
6862 0 : pcie_ari_disabled = true;
6863 0 : } else if (!strncmp(str, "cbiosize=", 9)) {
6864 0 : pci_cardbus_io_size = memparse(str + 9, &str);
6865 0 : } else if (!strncmp(str, "cbmemsize=", 10)) {
6866 0 : pci_cardbus_mem_size = memparse(str + 10, &str);
6867 0 : } else if (!strncmp(str, "resource_alignment=", 19)) {
6868 0 : resource_alignment_param = str + 19;
6869 0 : } else if (!strncmp(str, "ecrc=", 5)) {
6870 : pcie_ecrc_get_policy(str + 5);
6871 0 : } else if (!strncmp(str, "hpiosize=", 9)) {
6872 0 : pci_hotplug_io_size = memparse(str + 9, &str);
6873 0 : } else if (!strncmp(str, "hpmmiosize=", 11)) {
6874 0 : pci_hotplug_mmio_size = memparse(str + 11, &str);
6875 0 : } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6876 0 : pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6877 0 : } else if (!strncmp(str, "hpmemsize=", 10)) {
6878 0 : pci_hotplug_mmio_size = memparse(str + 10, &str);
6879 0 : pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6880 0 : } else if (!strncmp(str, "hpbussize=", 10)) {
6881 0 : pci_hotplug_bus_size =
6882 0 : simple_strtoul(str + 10, &str, 0);
6883 0 : if (pci_hotplug_bus_size > 0xff)
6884 0 : pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6885 0 : } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6886 0 : pcie_bus_config = PCIE_BUS_TUNE_OFF;
6887 0 : } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6888 0 : pcie_bus_config = PCIE_BUS_SAFE;
6889 0 : } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6890 0 : pcie_bus_config = PCIE_BUS_PERFORMANCE;
6891 0 : } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6892 0 : pcie_bus_config = PCIE_BUS_PEER2PEER;
6893 0 : } else if (!strncmp(str, "pcie_scan_all", 13)) {
6894 : pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6895 0 : } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6896 0 : disable_acs_redir_param = str + 18;
6897 : } else {
6898 0 : pr_err("PCI: Unknown option `%s'\n", str);
6899 : }
6900 : }
6901 0 : str = k;
6902 : }
6903 0 : return 0;
6904 : }
6905 : early_param("pci", pci_setup);
6906 :
6907 : /*
6908 : * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6909 : * in pci_setup(), above, to point to data in the __initdata section which
6910 : * will be freed after the init sequence is complete. We can't allocate memory
6911 : * in pci_setup() because some architectures do not have any memory allocation
6912 : * service available during an early_param() call. So we allocate memory and
6913 : * copy the variable here before the init section is freed.
6914 : *
6915 : */
6916 1 : static int __init pci_realloc_setup_params(void)
6917 : {
6918 1 : resource_alignment_param = kstrdup(resource_alignment_param,
6919 : GFP_KERNEL);
6920 1 : disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6921 :
6922 1 : return 0;
6923 : }
6924 : pure_initcall(pci_realloc_setup_params);
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