Line data Source code
1 : /* SPDX-License-Identifier: GPL-2.0 */
2 : #ifndef DRIVERS_PCI_H
3 : #define DRIVERS_PCI_H
4 :
5 : #include <linux/pci.h>
6 :
7 : /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 : #define MAX_NR_DEVFNS 256
9 :
10 : #define PCI_FIND_CAP_TTL 48
11 :
12 : #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13 :
14 : extern const unsigned char pcie_link_speed[];
15 : extern bool pci_early_dump;
16 :
17 : bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
18 : bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
19 : bool pcie_cap_has_rtctl(const struct pci_dev *dev);
20 :
21 : /* Functions internal to the PCI core code */
22 :
23 : int pci_create_sysfs_dev_files(struct pci_dev *pdev);
24 : void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
25 : void pci_cleanup_rom(struct pci_dev *dev);
26 : #ifdef CONFIG_DMI
27 : extern const struct attribute_group pci_dev_smbios_attr_group;
28 : #endif
29 :
30 : enum pci_mmap_api {
31 : PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
32 : PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
33 : };
34 : int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
35 : enum pci_mmap_api mmap_api);
36 :
37 : bool pci_reset_supported(struct pci_dev *dev);
38 : void pci_init_reset_methods(struct pci_dev *dev);
39 : int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
40 : int pci_bus_error_reset(struct pci_dev *dev);
41 :
42 : struct pci_cap_saved_data {
43 : u16 cap_nr;
44 : bool cap_extended;
45 : unsigned int size;
46 : u32 data[];
47 : };
48 :
49 : struct pci_cap_saved_state {
50 : struct hlist_node next;
51 : struct pci_cap_saved_data cap;
52 : };
53 :
54 : void pci_allocate_cap_save_buffers(struct pci_dev *dev);
55 : void pci_free_cap_save_buffers(struct pci_dev *dev);
56 : int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
57 : int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
58 : u16 cap, unsigned int size);
59 : struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
60 : struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
61 : u16 cap);
62 :
63 : #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
64 : #define PCI_PM_D3HOT_WAIT 10 /* msec */
65 : #define PCI_PM_D3COLD_WAIT 100 /* msec */
66 :
67 : /*
68 : * Following exit from Conventional Reset, devices must be ready within 1 sec
69 : * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
70 : * Reset (PCIe r6.0 sec 5.8).
71 : */
72 : #define PCI_RESET_WAIT 1000 /* msec */
73 : /*
74 : * Devices may extend the 1 sec period through Request Retry Status completions
75 : * (PCIe r6.0 sec 2.3.1). The spec does not provide an upper limit, but 60 sec
76 : * ought to be enough for any device to become responsive.
77 : */
78 : #define PCIE_RESET_READY_POLL_MS 60000 /* msec */
79 :
80 : void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
81 : void pci_refresh_power_state(struct pci_dev *dev);
82 : int pci_power_up(struct pci_dev *dev);
83 : void pci_disable_enabled_device(struct pci_dev *dev);
84 : int pci_finish_runtime_suspend(struct pci_dev *dev);
85 : void pcie_clear_device_status(struct pci_dev *dev);
86 : void pcie_clear_root_pme_status(struct pci_dev *dev);
87 : bool pci_check_pme_status(struct pci_dev *dev);
88 : void pci_pme_wakeup_bus(struct pci_bus *bus);
89 : int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
90 : void pci_pme_restore(struct pci_dev *dev);
91 : bool pci_dev_need_resume(struct pci_dev *dev);
92 : void pci_dev_adjust_pme(struct pci_dev *dev);
93 : void pci_dev_complete_resume(struct pci_dev *pci_dev);
94 : void pci_config_pm_runtime_get(struct pci_dev *dev);
95 : void pci_config_pm_runtime_put(struct pci_dev *dev);
96 : void pci_pm_init(struct pci_dev *dev);
97 : void pci_ea_init(struct pci_dev *dev);
98 : void pci_msi_init(struct pci_dev *dev);
99 : void pci_msix_init(struct pci_dev *dev);
100 : bool pci_bridge_d3_possible(struct pci_dev *dev);
101 : void pci_bridge_d3_update(struct pci_dev *dev);
102 : void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
103 : int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
104 : int timeout);
105 :
106 : static inline void pci_wakeup_event(struct pci_dev *dev)
107 : {
108 : /* Wait 100 ms before the system can be put into a sleep state. */
109 0 : pm_wakeup_event(&dev->dev, 100);
110 : }
111 :
112 : static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
113 : {
114 : return !!(pci_dev->subordinate);
115 : }
116 :
117 : static inline bool pci_power_manageable(struct pci_dev *pci_dev)
118 : {
119 : /*
120 : * Currently we allow normal PCI devices and PCI bridges transition
121 : * into D3 if their bridge_d3 is set.
122 : */
123 0 : return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
124 : }
125 :
126 : static inline bool pcie_downstream_port(const struct pci_dev *dev)
127 : {
128 0 : int type = pci_pcie_type(dev);
129 :
130 0 : return type == PCI_EXP_TYPE_ROOT_PORT ||
131 0 : type == PCI_EXP_TYPE_DOWNSTREAM ||
132 : type == PCI_EXP_TYPE_PCIE_BRIDGE;
133 : }
134 :
135 : void pci_vpd_init(struct pci_dev *dev);
136 : void pci_vpd_release(struct pci_dev *dev);
137 : extern const struct attribute_group pci_dev_vpd_attr_group;
138 :
139 : /* PCI Virtual Channel */
140 : int pci_save_vc_state(struct pci_dev *dev);
141 : void pci_restore_vc_state(struct pci_dev *dev);
142 : void pci_allocate_vc_save_buffers(struct pci_dev *dev);
143 :
144 : /* PCI /proc functions */
145 : #ifdef CONFIG_PROC_FS
146 : int pci_proc_attach_device(struct pci_dev *dev);
147 : int pci_proc_detach_device(struct pci_dev *dev);
148 : int pci_proc_detach_bus(struct pci_bus *bus);
149 : #else
150 : static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
151 : static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
152 : static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
153 : #endif
154 :
155 : /* Functions for PCI Hotplug drivers to use */
156 : int pci_hp_add_bridge(struct pci_dev *dev);
157 :
158 : #ifdef HAVE_PCI_LEGACY
159 : void pci_create_legacy_files(struct pci_bus *bus);
160 : void pci_remove_legacy_files(struct pci_bus *bus);
161 : #else
162 : static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
163 : static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
164 : #endif
165 :
166 : /* Lock for read/write access to pci device and bus lists */
167 : extern struct rw_semaphore pci_bus_sem;
168 : extern struct mutex pci_slot_mutex;
169 :
170 : extern raw_spinlock_t pci_lock;
171 :
172 : extern unsigned int pci_pm_d3hot_delay;
173 :
174 : #ifdef CONFIG_PCI_MSI
175 : void pci_no_msi(void);
176 : #else
177 : static inline void pci_no_msi(void) { }
178 : #endif
179 :
180 : void pci_realloc_get_opt(char *);
181 :
182 : static inline int pci_no_d1d2(struct pci_dev *dev)
183 : {
184 0 : unsigned int parent_dstates = 0;
185 :
186 0 : if (dev->bus->self)
187 0 : parent_dstates = dev->bus->self->no_d1d2;
188 0 : return (dev->no_d1d2 || parent_dstates);
189 :
190 : }
191 : extern const struct attribute_group *pci_dev_groups[];
192 : extern const struct attribute_group *pcibus_groups[];
193 : extern const struct device_type pci_dev_type;
194 : extern const struct attribute_group *pci_bus_groups[];
195 :
196 : extern unsigned long pci_hotplug_io_size;
197 : extern unsigned long pci_hotplug_mmio_size;
198 : extern unsigned long pci_hotplug_mmio_pref_size;
199 : extern unsigned long pci_hotplug_bus_size;
200 :
201 : /**
202 : * pci_match_one_device - Tell if a PCI device structure has a matching
203 : * PCI device id structure
204 : * @id: single PCI device id structure to match
205 : * @dev: the PCI device structure to match against
206 : *
207 : * Returns the matching pci_device_id structure or %NULL if there is no match.
208 : */
209 : static inline const struct pci_device_id *
210 0 : pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
211 : {
212 0 : if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
213 0 : (id->device == PCI_ANY_ID || id->device == dev->device) &&
214 0 : (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
215 0 : (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
216 0 : !((id->class ^ dev->class) & id->class_mask))
217 : return id;
218 0 : return NULL;
219 : }
220 :
221 : /* PCI slot sysfs helper code */
222 : #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
223 :
224 : extern struct kset *pci_slots_kset;
225 :
226 : struct pci_slot_attribute {
227 : struct attribute attr;
228 : ssize_t (*show)(struct pci_slot *, char *);
229 : ssize_t (*store)(struct pci_slot *, const char *, size_t);
230 : };
231 : #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
232 :
233 : enum pci_bar_type {
234 : pci_bar_unknown, /* Standard PCI BAR probe */
235 : pci_bar_io, /* An I/O port BAR */
236 : pci_bar_mem32, /* A 32-bit memory BAR */
237 : pci_bar_mem64, /* A 64-bit memory BAR */
238 : };
239 :
240 : struct device *pci_get_host_bridge_device(struct pci_dev *dev);
241 : void pci_put_host_bridge_device(struct device *dev);
242 :
243 : int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
244 : bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
245 : int crs_timeout);
246 : bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
247 : int crs_timeout);
248 : int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
249 :
250 : int pci_setup_device(struct pci_dev *dev);
251 : int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
252 : struct resource *res, unsigned int reg);
253 : void pci_configure_ari(struct pci_dev *dev);
254 : void __pci_bus_size_bridges(struct pci_bus *bus,
255 : struct list_head *realloc_head);
256 : void __pci_bus_assign_resources(const struct pci_bus *bus,
257 : struct list_head *realloc_head,
258 : struct list_head *fail_head);
259 : bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
260 :
261 : void pci_reassigndev_resource_alignment(struct pci_dev *dev);
262 : void pci_disable_bridge_window(struct pci_dev *dev);
263 : struct pci_bus *pci_bus_get(struct pci_bus *bus);
264 : void pci_bus_put(struct pci_bus *bus);
265 :
266 : /* PCIe link information from Link Capabilities 2 */
267 : #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
268 : ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
269 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
270 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
271 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
272 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
273 : (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
274 : PCI_SPEED_UNKNOWN)
275 :
276 : /* PCIe speed to Mb/s reduced by encoding overhead */
277 : #define PCIE_SPEED2MBS_ENC(speed) \
278 : ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
279 : (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
280 : (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
281 : (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
282 : (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
283 : (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
284 : 0)
285 :
286 : const char *pci_speed_string(enum pci_bus_speed speed);
287 : enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
288 : enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
289 : u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
290 : enum pcie_link_width *width);
291 : void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
292 : void pcie_report_downtraining(struct pci_dev *dev);
293 : void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
294 :
295 : /* Single Root I/O Virtualization */
296 : struct pci_sriov {
297 : int pos; /* Capability position */
298 : int nres; /* Number of resources */
299 : u32 cap; /* SR-IOV Capabilities */
300 : u16 ctrl; /* SR-IOV Control */
301 : u16 total_VFs; /* Total VFs associated with the PF */
302 : u16 initial_VFs; /* Initial VFs associated with the PF */
303 : u16 num_VFs; /* Number of VFs available */
304 : u16 offset; /* First VF Routing ID offset */
305 : u16 stride; /* Following VF stride */
306 : u16 vf_device; /* VF device ID */
307 : u32 pgsz; /* Page size for BAR alignment */
308 : u8 link; /* Function Dependency Link */
309 : u8 max_VF_buses; /* Max buses consumed by VFs */
310 : u16 driver_max_VFs; /* Max num VFs driver supports */
311 : struct pci_dev *dev; /* Lowest numbered PF */
312 : struct pci_dev *self; /* This PF */
313 : u32 class; /* VF device */
314 : u8 hdr_type; /* VF header type */
315 : u16 subsystem_vendor; /* VF subsystem vendor */
316 : u16 subsystem_device; /* VF subsystem device */
317 : resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
318 : bool drivers_autoprobe; /* Auto probing of VFs by driver */
319 : };
320 :
321 : /**
322 : * pci_dev_set_io_state - Set the new error state if possible.
323 : *
324 : * @dev: PCI device to set new error_state
325 : * @new: the state we want dev to be in
326 : *
327 : * If the device is experiencing perm_failure, it has to remain in that state.
328 : * Any other transition is allowed.
329 : *
330 : * Returns true if state has been changed to the requested state.
331 : */
332 : static inline bool pci_dev_set_io_state(struct pci_dev *dev,
333 : pci_channel_state_t new)
334 : {
335 : pci_channel_state_t old;
336 :
337 : switch (new) {
338 : case pci_channel_io_perm_failure:
339 : xchg(&dev->error_state, pci_channel_io_perm_failure);
340 : return true;
341 : case pci_channel_io_frozen:
342 : old = cmpxchg(&dev->error_state, pci_channel_io_normal,
343 : pci_channel_io_frozen);
344 : return old != pci_channel_io_perm_failure;
345 : case pci_channel_io_normal:
346 : old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
347 : pci_channel_io_normal);
348 : return old != pci_channel_io_perm_failure;
349 : default:
350 : return false;
351 : }
352 : }
353 :
354 : static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
355 : {
356 : pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
357 :
358 : return 0;
359 : }
360 :
361 : static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
362 : {
363 : return dev->error_state == pci_channel_io_perm_failure;
364 : }
365 :
366 : /* pci_dev priv_flags */
367 : #define PCI_DEV_ADDED 0
368 : #define PCI_DPC_RECOVERED 1
369 : #define PCI_DPC_RECOVERING 2
370 :
371 : static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
372 : {
373 0 : assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
374 : }
375 :
376 : static inline bool pci_dev_is_added(const struct pci_dev *dev)
377 : {
378 0 : return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
379 : }
380 :
381 : #ifdef CONFIG_PCIEAER
382 : #include <linux/aer.h>
383 :
384 : #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
385 :
386 : struct aer_err_info {
387 : struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
388 : int error_dev_num;
389 :
390 : unsigned int id:16;
391 :
392 : unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
393 : unsigned int __pad1:5;
394 : unsigned int multi_error_valid:1;
395 :
396 : unsigned int first_error:5;
397 : unsigned int __pad2:2;
398 : unsigned int tlp_header_valid:1;
399 :
400 : unsigned int status; /* COR/UNCOR Error Status */
401 : unsigned int mask; /* COR/UNCOR Error Mask */
402 : struct aer_header_log_regs tlp; /* TLP Header */
403 : };
404 :
405 : int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
406 : void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
407 : #endif /* CONFIG_PCIEAER */
408 :
409 : #ifdef CONFIG_PCIEPORTBUS
410 : /* Cached RCEC Endpoint Association */
411 : struct rcec_ea {
412 : u8 nextbusn;
413 : u8 lastbusn;
414 : u32 bitmap;
415 : };
416 : #endif
417 :
418 : #ifdef CONFIG_PCIE_DPC
419 : void pci_save_dpc_state(struct pci_dev *dev);
420 : void pci_restore_dpc_state(struct pci_dev *dev);
421 : void pci_dpc_init(struct pci_dev *pdev);
422 : void dpc_process_error(struct pci_dev *pdev);
423 : pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
424 : bool pci_dpc_recovered(struct pci_dev *pdev);
425 : #else
426 : static inline void pci_save_dpc_state(struct pci_dev *dev) {}
427 : static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
428 : static inline void pci_dpc_init(struct pci_dev *pdev) {}
429 : static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
430 : #endif
431 :
432 : #ifdef CONFIG_PCIEPORTBUS
433 : void pci_rcec_init(struct pci_dev *dev);
434 : void pci_rcec_exit(struct pci_dev *dev);
435 : void pcie_link_rcec(struct pci_dev *rcec);
436 : void pcie_walk_rcec(struct pci_dev *rcec,
437 : int (*cb)(struct pci_dev *, void *),
438 : void *userdata);
439 : #else
440 : static inline void pci_rcec_init(struct pci_dev *dev) {}
441 : static inline void pci_rcec_exit(struct pci_dev *dev) {}
442 : static inline void pcie_link_rcec(struct pci_dev *rcec) {}
443 : static inline void pcie_walk_rcec(struct pci_dev *rcec,
444 : int (*cb)(struct pci_dev *, void *),
445 : void *userdata) {}
446 : #endif
447 :
448 : #ifdef CONFIG_PCI_ATS
449 : /* Address Translation Service */
450 : void pci_ats_init(struct pci_dev *dev);
451 : void pci_restore_ats_state(struct pci_dev *dev);
452 : #else
453 : static inline void pci_ats_init(struct pci_dev *d) { }
454 : static inline void pci_restore_ats_state(struct pci_dev *dev) { }
455 : #endif /* CONFIG_PCI_ATS */
456 :
457 : #ifdef CONFIG_PCI_PRI
458 : void pci_pri_init(struct pci_dev *dev);
459 : void pci_restore_pri_state(struct pci_dev *pdev);
460 : #else
461 : static inline void pci_pri_init(struct pci_dev *dev) { }
462 : static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
463 : #endif
464 :
465 : #ifdef CONFIG_PCI_PASID
466 : void pci_pasid_init(struct pci_dev *dev);
467 : void pci_restore_pasid_state(struct pci_dev *pdev);
468 : #else
469 : static inline void pci_pasid_init(struct pci_dev *dev) { }
470 : static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
471 : #endif
472 :
473 : #ifdef CONFIG_PCI_IOV
474 : int pci_iov_init(struct pci_dev *dev);
475 : void pci_iov_release(struct pci_dev *dev);
476 : void pci_iov_remove(struct pci_dev *dev);
477 : void pci_iov_update_resource(struct pci_dev *dev, int resno);
478 : resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
479 : void pci_restore_iov_state(struct pci_dev *dev);
480 : int pci_iov_bus_range(struct pci_bus *bus);
481 : extern const struct attribute_group sriov_pf_dev_attr_group;
482 : extern const struct attribute_group sriov_vf_dev_attr_group;
483 : #else
484 : static inline int pci_iov_init(struct pci_dev *dev)
485 : {
486 : return -ENODEV;
487 : }
488 : static inline void pci_iov_release(struct pci_dev *dev)
489 :
490 : {
491 : }
492 : static inline void pci_iov_remove(struct pci_dev *dev)
493 : {
494 : }
495 : static inline void pci_restore_iov_state(struct pci_dev *dev)
496 : {
497 : }
498 : static inline int pci_iov_bus_range(struct pci_bus *bus)
499 : {
500 : return 0;
501 : }
502 :
503 : #endif /* CONFIG_PCI_IOV */
504 :
505 : #ifdef CONFIG_PCIE_PTM
506 : void pci_ptm_init(struct pci_dev *dev);
507 : void pci_save_ptm_state(struct pci_dev *dev);
508 : void pci_restore_ptm_state(struct pci_dev *dev);
509 : void pci_suspend_ptm(struct pci_dev *dev);
510 : void pci_resume_ptm(struct pci_dev *dev);
511 : #else
512 : static inline void pci_ptm_init(struct pci_dev *dev) { }
513 : static inline void pci_save_ptm_state(struct pci_dev *dev) { }
514 : static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
515 : static inline void pci_suspend_ptm(struct pci_dev *dev) { }
516 : static inline void pci_resume_ptm(struct pci_dev *dev) { }
517 : #endif
518 :
519 : unsigned long pci_cardbus_resource_alignment(struct resource *);
520 :
521 0 : static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
522 : struct resource *res)
523 : {
524 : #ifdef CONFIG_PCI_IOV
525 : int resno = res - dev->resource;
526 :
527 : if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
528 : return pci_sriov_resource_alignment(dev, resno);
529 : #endif
530 0 : if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
531 0 : return pci_cardbus_resource_alignment(res);
532 0 : return resource_alignment(res);
533 : }
534 :
535 : void pci_acs_init(struct pci_dev *dev);
536 : #ifdef CONFIG_PCI_QUIRKS
537 : int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
538 : int pci_dev_specific_enable_acs(struct pci_dev *dev);
539 : int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
540 : #else
541 : static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
542 : u16 acs_flags)
543 : {
544 : return -ENOTTY;
545 : }
546 : static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
547 : {
548 : return -ENOTTY;
549 : }
550 : static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
551 : {
552 : return -ENOTTY;
553 : }
554 : #endif
555 :
556 : /* PCI error reporting and recovery */
557 : pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
558 : pci_channel_state_t state,
559 : pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
560 :
561 : bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
562 : #ifdef CONFIG_PCIEASPM
563 : void pcie_aspm_init_link_state(struct pci_dev *pdev);
564 : void pcie_aspm_exit_link_state(struct pci_dev *pdev);
565 : void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
566 : #else
567 : static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
568 : static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
569 : static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
570 : #endif
571 :
572 : #ifdef CONFIG_PCIE_ECRC
573 : void pcie_set_ecrc_checking(struct pci_dev *dev);
574 : void pcie_ecrc_get_policy(char *str);
575 : #else
576 : static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
577 : static inline void pcie_ecrc_get_policy(char *str) { }
578 : #endif
579 :
580 : struct pci_dev_reset_methods {
581 : u16 vendor;
582 : u16 device;
583 : int (*reset)(struct pci_dev *dev, bool probe);
584 : };
585 :
586 : struct pci_reset_fn_method {
587 : int (*reset_fn)(struct pci_dev *pdev, bool probe);
588 : char *name;
589 : };
590 :
591 : #ifdef CONFIG_PCI_QUIRKS
592 : int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
593 : #else
594 : static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
595 : {
596 : return -ENOTTY;
597 : }
598 : #endif
599 :
600 : #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
601 : int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
602 : struct resource *res);
603 : #else
604 : static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
605 : u16 segment, struct resource *res)
606 : {
607 : return -ENODEV;
608 : }
609 : #endif
610 :
611 : int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
612 : int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
613 : static inline u64 pci_rebar_size_to_bytes(int size)
614 : {
615 0 : return 1ULL << (size + 20);
616 : }
617 :
618 : struct device_node;
619 :
620 : #ifdef CONFIG_OF
621 : int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
622 : int of_get_pci_domain_nr(struct device_node *node);
623 : int of_pci_get_max_link_speed(struct device_node *node);
624 : u32 of_pci_get_slot_power_limit(struct device_node *node,
625 : u8 *slot_power_limit_value,
626 : u8 *slot_power_limit_scale);
627 : void pci_set_of_node(struct pci_dev *dev);
628 : void pci_release_of_node(struct pci_dev *dev);
629 : void pci_set_bus_of_node(struct pci_bus *bus);
630 : void pci_release_bus_of_node(struct pci_bus *bus);
631 :
632 : int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
633 :
634 : #else
635 : static inline int
636 : of_pci_parse_bus_range(struct device_node *node, struct resource *res)
637 : {
638 : return -EINVAL;
639 : }
640 :
641 : static inline int
642 : of_get_pci_domain_nr(struct device_node *node)
643 : {
644 : return -1;
645 : }
646 :
647 : static inline int
648 : of_pci_get_max_link_speed(struct device_node *node)
649 : {
650 : return -EINVAL;
651 : }
652 :
653 : static inline u32
654 : of_pci_get_slot_power_limit(struct device_node *node,
655 : u8 *slot_power_limit_value,
656 : u8 *slot_power_limit_scale)
657 : {
658 : if (slot_power_limit_value)
659 : *slot_power_limit_value = 0;
660 : if (slot_power_limit_scale)
661 : *slot_power_limit_scale = 0;
662 : return 0;
663 : }
664 :
665 : static inline void pci_set_of_node(struct pci_dev *dev) { }
666 : static inline void pci_release_of_node(struct pci_dev *dev) { }
667 : static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
668 : static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
669 :
670 : static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
671 : {
672 : return 0;
673 : }
674 :
675 : #endif /* CONFIG_OF */
676 :
677 : #ifdef CONFIG_PCIEAER
678 : void pci_no_aer(void);
679 : void pci_aer_init(struct pci_dev *dev);
680 : void pci_aer_exit(struct pci_dev *dev);
681 : extern const struct attribute_group aer_stats_attr_group;
682 : void pci_aer_clear_fatal_status(struct pci_dev *dev);
683 : int pci_aer_clear_status(struct pci_dev *dev);
684 : int pci_aer_raw_clear_status(struct pci_dev *dev);
685 : #else
686 : static inline void pci_no_aer(void) { }
687 : static inline void pci_aer_init(struct pci_dev *d) { }
688 : static inline void pci_aer_exit(struct pci_dev *d) { }
689 : static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
690 : static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
691 : static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
692 : #endif
693 :
694 : #ifdef CONFIG_ACPI
695 : int pci_acpi_program_hp_params(struct pci_dev *dev);
696 : extern const struct attribute_group pci_dev_acpi_attr_group;
697 : void pci_set_acpi_fwnode(struct pci_dev *dev);
698 : int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
699 : bool acpi_pci_power_manageable(struct pci_dev *dev);
700 : bool acpi_pci_bridge_d3(struct pci_dev *dev);
701 : int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
702 : pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
703 : void acpi_pci_refresh_power_state(struct pci_dev *dev);
704 : int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
705 : bool acpi_pci_need_resume(struct pci_dev *dev);
706 : pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
707 : #else
708 0 : static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
709 : {
710 0 : return -ENOTTY;
711 : }
712 : static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {}
713 : static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
714 : {
715 : return -ENODEV;
716 : }
717 : static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
718 : {
719 : return false;
720 : }
721 : static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
722 : {
723 : return false;
724 : }
725 : static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
726 : {
727 : return -ENODEV;
728 : }
729 : static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
730 : {
731 : return PCI_UNKNOWN;
732 : }
733 : static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) {}
734 : static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
735 : {
736 : return -ENODEV;
737 : }
738 : static inline bool acpi_pci_need_resume(struct pci_dev *dev)
739 : {
740 : return false;
741 : }
742 : static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
743 : {
744 : return PCI_POWER_ERROR;
745 : }
746 : #endif
747 :
748 : #ifdef CONFIG_PCIEASPM
749 : extern const struct attribute_group aspm_ctrl_attr_group;
750 : #endif
751 :
752 : extern const struct attribute_group pci_dev_reset_method_attr_group;
753 :
754 : #ifdef CONFIG_X86_INTEL_MID
755 : bool pci_use_mid_pm(void);
756 : int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
757 : pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
758 : #else
759 : static inline bool pci_use_mid_pm(void)
760 : {
761 : return false;
762 : }
763 : static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
764 : {
765 : return -ENODEV;
766 : }
767 : static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
768 : {
769 : return PCI_UNKNOWN;
770 : }
771 : #endif
772 :
773 : /*
774 : * Config Address for PCI Configuration Mechanism #1
775 : *
776 : * See PCI Local Bus Specification, Revision 3.0,
777 : * Section 3.2.2.3.2, Figure 3-2, p. 50.
778 : */
779 :
780 : #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
781 : #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
782 : #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
783 :
784 : #define PCI_CONF1_BUS_MASK 0xff
785 : #define PCI_CONF1_DEV_MASK 0x1f
786 : #define PCI_CONF1_FUNC_MASK 0x7
787 : #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
788 :
789 : #define PCI_CONF1_ENABLE BIT(31)
790 : #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
791 : #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
792 : #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
793 : #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
794 :
795 : #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
796 : (PCI_CONF1_ENABLE | \
797 : PCI_CONF1_BUS(bus) | \
798 : PCI_CONF1_DEV(dev) | \
799 : PCI_CONF1_FUNC(func) | \
800 : PCI_CONF1_REG(reg))
801 :
802 : /*
803 : * Extension of PCI Config Address for accessing extended PCIe registers
804 : *
805 : * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
806 : * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
807 : * are used for specifying additional 4 high bits of PCI Express register.
808 : */
809 :
810 : #define PCI_CONF1_EXT_REG_SHIFT 16
811 : #define PCI_CONF1_EXT_REG_MASK 0xf00
812 : #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
813 :
814 : #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
815 : (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
816 : PCI_CONF1_EXT_REG(reg))
817 :
818 : #endif /* DRIVERS_PCI_H */
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