Line data Source code
1 : /*
2 : * Copyright © 2008 Keith Packard
3 : *
4 : * Permission to use, copy, modify, distribute, and sell this software and its
5 : * documentation for any purpose is hereby granted without fee, provided that
6 : * the above copyright notice appear in all copies and that both that copyright
7 : * notice and this permission notice appear in supporting documentation, and
8 : * that the name of the copyright holders not be used in advertising or
9 : * publicity pertaining to distribution of the software without specific,
10 : * written prior permission. The copyright holders make no representations
11 : * about the suitability of this software for any purpose. It is provided "as
12 : * is" without express or implied warranty.
13 : *
14 : * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 : * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 : * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 : * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 : * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 : * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 : * OF THIS SOFTWARE.
21 : */
22 :
23 : #ifndef _DRM_DP_HELPER_H_
24 : #define _DRM_DP_HELPER_H_
25 :
26 : #include <linux/delay.h>
27 : #include <linux/i2c.h>
28 :
29 : #include <drm/display/drm_dp.h>
30 : #include <drm/drm_connector.h>
31 :
32 : struct drm_device;
33 : struct drm_dp_aux;
34 : struct drm_panel;
35 :
36 : bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
37 : int lane_count);
38 : bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
39 : int lane_count);
40 : u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
41 : int lane);
42 : u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
43 : int lane);
44 : u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
45 : int lane);
46 :
47 : int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
48 : enum drm_dp_phy dp_phy, bool uhbr);
49 : int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
50 : enum drm_dp_phy dp_phy, bool uhbr);
51 :
52 : void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
53 : const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
54 : void drm_dp_lttpr_link_train_clock_recovery_delay(void);
55 : void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
56 : const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
57 : void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
58 : const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
59 :
60 : int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
61 : bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
62 : int lane_count);
63 : bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
64 : int lane_count);
65 : bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
66 : bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
67 : bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
68 :
69 : u8 drm_dp_link_rate_to_bw_code(int link_rate);
70 : int drm_dp_bw_code_to_link_rate(u8 link_bw);
71 :
72 : const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
73 :
74 : /**
75 : * struct drm_dp_vsc_sdp - drm DP VSC SDP
76 : *
77 : * This structure represents a DP VSC SDP of drm
78 : * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
79 : * [Table 2-117: VSC SDP Payload for DB16 through DB18]
80 : *
81 : * @sdp_type: secondary-data packet type
82 : * @revision: revision number
83 : * @length: number of valid data bytes
84 : * @pixelformat: pixel encoding format
85 : * @colorimetry: colorimetry format
86 : * @bpc: bit per color
87 : * @dynamic_range: dynamic range information
88 : * @content_type: CTA-861-G defines content types and expected processing by a sink device
89 : */
90 : struct drm_dp_vsc_sdp {
91 : unsigned char sdp_type;
92 : unsigned char revision;
93 : unsigned char length;
94 : enum dp_pixelformat pixelformat;
95 : enum dp_colorimetry colorimetry;
96 : int bpc;
97 : enum dp_dynamic_range dynamic_range;
98 : enum dp_content_type content_type;
99 : };
100 :
101 : void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
102 : const struct drm_dp_vsc_sdp *vsc);
103 :
104 : int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
105 :
106 : static inline int
107 : drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
108 : {
109 : return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
110 : }
111 :
112 : static inline u8
113 : drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
114 : {
115 : return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
116 : }
117 :
118 : static inline bool
119 : drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
120 : {
121 : return dpcd[DP_DPCD_REV] >= 0x11 &&
122 : (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
123 : }
124 :
125 : static inline bool
126 : drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
127 : {
128 : return dpcd[DP_DPCD_REV] >= 0x11 &&
129 : (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
130 : }
131 :
132 : static inline bool
133 : drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
134 : {
135 : return dpcd[DP_DPCD_REV] >= 0x12 &&
136 : dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
137 : }
138 :
139 : static inline bool
140 : drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
141 : {
142 : return dpcd[DP_DPCD_REV] >= 0x11 ||
143 : dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
144 : }
145 :
146 : static inline bool
147 : drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
148 : {
149 : return dpcd[DP_DPCD_REV] >= 0x14 &&
150 : dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
151 : }
152 :
153 : static inline u8
154 : drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
155 : {
156 : return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
157 : DP_TRAINING_PATTERN_MASK;
158 : }
159 :
160 : static inline bool
161 : drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
162 : {
163 0 : return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
164 : }
165 :
166 : /* DP/eDP DSC support */
167 : u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
168 : bool is_edp);
169 : u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
170 : int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
171 : u8 dsc_bpc[3]);
172 :
173 : static inline bool
174 : drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
175 : {
176 : return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
177 : DP_DSC_DECOMPRESSION_IS_SUPPORTED;
178 : }
179 :
180 : static inline u16
181 : drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
182 : {
183 : return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
184 : (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
185 : DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
186 : DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
187 : }
188 :
189 : static inline u32
190 : drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
191 : {
192 : /* Max Slicewidth = Number of Pixels * 320 */
193 : return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
194 : DP_DSC_SLICE_WIDTH_MULTIPLIER;
195 : }
196 :
197 : /* Forward Error Correction Support on DP 1.4 */
198 : static inline bool
199 : drm_dp_sink_supports_fec(const u8 fec_capable)
200 : {
201 : return fec_capable & DP_FEC_CAPABLE;
202 : }
203 :
204 : static inline bool
205 : drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
206 : {
207 : return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
208 : }
209 :
210 : static inline bool
211 : drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
212 : {
213 : return dpcd[DP_EDP_CONFIGURATION_CAP] &
214 : DP_ALTERNATE_SCRAMBLER_RESET_CAP;
215 : }
216 :
217 : /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
218 : static inline bool
219 : drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
220 : {
221 : return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
222 : DP_MSA_TIMING_PAR_IGNORED;
223 : }
224 :
225 : /**
226 : * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
227 : * @edp_dpcd: The DPCD to check
228 : *
229 : * Note that currently this function will return %false for panels which support various DPCD
230 : * backlight features but which require the brightness be set through PWM, and don't support setting
231 : * the brightness level via the DPCD.
232 : *
233 : * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
234 : * otherwise
235 : */
236 : static inline bool
237 : drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
238 : {
239 : return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
240 : }
241 :
242 : /*
243 : * DisplayPort AUX channel
244 : */
245 :
246 : /**
247 : * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
248 : * @address: address of the (first) register to access
249 : * @request: contains the type of transaction (see DP_AUX_* macros)
250 : * @reply: upon completion, contains the reply type of the transaction
251 : * @buffer: pointer to a transmission or reception buffer
252 : * @size: size of @buffer
253 : */
254 : struct drm_dp_aux_msg {
255 : unsigned int address;
256 : u8 request;
257 : u8 reply;
258 : void *buffer;
259 : size_t size;
260 : };
261 :
262 : struct cec_adapter;
263 : struct edid;
264 : struct drm_connector;
265 :
266 : /**
267 : * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
268 : * @lock: mutex protecting this struct
269 : * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
270 : * @connector: the connector this CEC adapter is associated with
271 : * @unregister_work: unregister the CEC adapter
272 : */
273 : struct drm_dp_aux_cec {
274 : struct mutex lock;
275 : struct cec_adapter *adap;
276 : struct drm_connector *connector;
277 : struct delayed_work unregister_work;
278 : };
279 :
280 : /**
281 : * struct drm_dp_aux - DisplayPort AUX channel
282 : *
283 : * An AUX channel can also be used to transport I2C messages to a sink. A
284 : * typical application of that is to access an EDID that's present in the sink
285 : * device. The @transfer() function can also be used to execute such
286 : * transactions. The drm_dp_aux_register() function registers an I2C adapter
287 : * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
288 : * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
289 : * transfers by default; if a partial response is received, the adapter will
290 : * drop down to the size given by the partial response for this transaction
291 : * only.
292 : */
293 : struct drm_dp_aux {
294 : /**
295 : * @name: user-visible name of this AUX channel and the
296 : * I2C-over-AUX adapter.
297 : *
298 : * It's also used to specify the name of the I2C adapter. If set
299 : * to %NULL, dev_name() of @dev will be used.
300 : */
301 : const char *name;
302 :
303 : /**
304 : * @ddc: I2C adapter that can be used for I2C-over-AUX
305 : * communication
306 : */
307 : struct i2c_adapter ddc;
308 :
309 : /**
310 : * @dev: pointer to struct device that is the parent for this
311 : * AUX channel.
312 : */
313 : struct device *dev;
314 :
315 : /**
316 : * @drm_dev: pointer to the &drm_device that owns this AUX channel.
317 : * Beware, this may be %NULL before drm_dp_aux_register() has been
318 : * called.
319 : *
320 : * It should be set to the &drm_device that will be using this AUX
321 : * channel as early as possible. For many graphics drivers this should
322 : * happen before drm_dp_aux_init(), however it's perfectly fine to set
323 : * this field later so long as it's assigned before calling
324 : * drm_dp_aux_register().
325 : */
326 : struct drm_device *drm_dev;
327 :
328 : /**
329 : * @crtc: backpointer to the crtc that is currently using this
330 : * AUX channel
331 : */
332 : struct drm_crtc *crtc;
333 :
334 : /**
335 : * @hw_mutex: internal mutex used for locking transfers.
336 : *
337 : * Note that if the underlying hardware is shared among multiple
338 : * channels, the driver needs to do additional locking to
339 : * prevent concurrent access.
340 : */
341 : struct mutex hw_mutex;
342 :
343 : /**
344 : * @crc_work: worker that captures CRCs for each frame
345 : */
346 : struct work_struct crc_work;
347 :
348 : /**
349 : * @crc_count: counter of captured frame CRCs
350 : */
351 : u8 crc_count;
352 :
353 : /**
354 : * @transfer: transfers a message representing a single AUX
355 : * transaction.
356 : *
357 : * This is a hardware-specific implementation of how
358 : * transactions are executed that the drivers must provide.
359 : *
360 : * A pointer to a &drm_dp_aux_msg structure describing the
361 : * transaction is passed into this function. Upon success, the
362 : * implementation should return the number of payload bytes that
363 : * were transferred, or a negative error-code on failure.
364 : *
365 : * Helpers will propagate these errors, with the exception of
366 : * the %-EBUSY error, which causes a transaction to be retried.
367 : * On a short, helpers will return %-EPROTO to make it simpler
368 : * to check for failure.
369 : *
370 : * The @transfer() function must only modify the reply field of
371 : * the &drm_dp_aux_msg structure. The retry logic and i2c
372 : * helpers assume this is the case.
373 : *
374 : * Also note that this callback can be called no matter the
375 : * state @dev is in and also no matter what state the panel is
376 : * in. It's expected:
377 : *
378 : * - If the @dev providing the AUX bus is currently unpowered then
379 : * it will power itself up for the transfer.
380 : *
381 : * - If we're on eDP (using a drm_panel) and the panel is not in a
382 : * state where it can respond (it's not powered or it's in a
383 : * low power state) then this function may return an error, but
384 : * not crash. It's up to the caller of this code to make sure that
385 : * the panel is powered on if getting an error back is not OK. If a
386 : * drm_panel driver is initiating a DP AUX transfer it may power
387 : * itself up however it wants. All other code should ensure that
388 : * the pre_enable() bridge chain (which eventually calls the
389 : * drm_panel prepare function) has powered the panel.
390 : */
391 : ssize_t (*transfer)(struct drm_dp_aux *aux,
392 : struct drm_dp_aux_msg *msg);
393 :
394 : /**
395 : * @wait_hpd_asserted: wait for HPD to be asserted
396 : *
397 : * This is mainly useful for eDP panels drivers to wait for an eDP
398 : * panel to finish powering on. This is an optional function.
399 : *
400 : * This function will efficiently wait for the HPD signal to be
401 : * asserted. The `wait_us` parameter that is passed in says that we
402 : * know that the HPD signal is expected to be asserted within `wait_us`
403 : * microseconds. This function could wait for longer than `wait_us` if
404 : * the logic in the DP controller has a long debouncing time. The
405 : * important thing is that if this function returns success that the
406 : * DP controller is ready to send AUX transactions.
407 : *
408 : * This function returns 0 if HPD was asserted or -ETIMEDOUT if time
409 : * expired and HPD wasn't asserted. This function should not print
410 : * timeout errors to the log.
411 : *
412 : * The semantics of this function are designed to match the
413 : * readx_poll_timeout() function. That means a `wait_us` of 0 means
414 : * to wait forever. Like readx_poll_timeout(), this function may sleep.
415 : *
416 : * NOTE: this function specifically reports the state of the HPD pin
417 : * that's associated with the DP AUX channel. This is different from
418 : * the HPD concept in much of the rest of DRM which is more about
419 : * physical presence of a display. For eDP, for instance, a display is
420 : * assumed always present even if the HPD pin is deasserted.
421 : */
422 : int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us);
423 :
424 : /**
425 : * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
426 : */
427 : unsigned i2c_nack_count;
428 : /**
429 : * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
430 : */
431 : unsigned i2c_defer_count;
432 : /**
433 : * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
434 : */
435 : struct drm_dp_aux_cec cec;
436 : /**
437 : * @is_remote: Is this AUX CH actually using sideband messaging.
438 : */
439 : bool is_remote;
440 : };
441 :
442 : int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
443 : ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
444 : void *buffer, size_t size);
445 : ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
446 : void *buffer, size_t size);
447 :
448 : /**
449 : * drm_dp_dpcd_readb() - read a single byte from the DPCD
450 : * @aux: DisplayPort AUX channel
451 : * @offset: address of the register to read
452 : * @valuep: location where the value of the register will be stored
453 : *
454 : * Returns the number of bytes transferred (1) on success, or a negative
455 : * error code on failure.
456 : */
457 : static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
458 : unsigned int offset, u8 *valuep)
459 : {
460 0 : return drm_dp_dpcd_read(aux, offset, valuep, 1);
461 : }
462 :
463 : /**
464 : * drm_dp_dpcd_writeb() - write a single byte to the DPCD
465 : * @aux: DisplayPort AUX channel
466 : * @offset: address of the register to write
467 : * @value: value to write to the register
468 : *
469 : * Returns the number of bytes transferred (1) on success, or a negative
470 : * error code on failure.
471 : */
472 : static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
473 : unsigned int offset, u8 value)
474 : {
475 0 : return drm_dp_dpcd_write(aux, offset, &value, 1);
476 : }
477 :
478 : int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
479 : u8 dpcd[DP_RECEIVER_CAP_SIZE]);
480 :
481 : int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
482 : u8 status[DP_LINK_STATUS_SIZE]);
483 :
484 : int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
485 : enum drm_dp_phy dp_phy,
486 : u8 link_status[DP_LINK_STATUS_SIZE]);
487 :
488 : bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
489 : u8 real_edid_checksum);
490 :
491 : int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
492 : const u8 dpcd[DP_RECEIVER_CAP_SIZE],
493 : u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
494 : bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
495 : const u8 port_cap[4], u8 type);
496 : bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
497 : const u8 port_cap[4],
498 : const struct edid *edid);
499 : int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
500 : const u8 port_cap[4]);
501 : int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
502 : const u8 port_cap[4],
503 : const struct edid *edid);
504 : int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
505 : const u8 port_cap[4],
506 : const struct edid *edid);
507 : int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
508 : const u8 port_cap[4],
509 : const struct edid *edid);
510 : bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
511 : const u8 port_cap[4]);
512 : bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
513 : const u8 port_cap[4]);
514 : struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
515 : const u8 dpcd[DP_RECEIVER_CAP_SIZE],
516 : const u8 port_cap[4]);
517 : int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
518 : void drm_dp_downstream_debug(struct seq_file *m,
519 : const u8 dpcd[DP_RECEIVER_CAP_SIZE],
520 : const u8 port_cap[4],
521 : const struct edid *edid,
522 : struct drm_dp_aux *aux);
523 : enum drm_mode_subconnector
524 : drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
525 : const u8 port_cap[4]);
526 : void drm_dp_set_subconnector_property(struct drm_connector *connector,
527 : enum drm_connector_status status,
528 : const u8 *dpcd,
529 : const u8 port_cap[4]);
530 :
531 : struct drm_dp_desc;
532 : bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
533 : const u8 dpcd[DP_RECEIVER_CAP_SIZE],
534 : const struct drm_dp_desc *desc);
535 : int drm_dp_read_sink_count(struct drm_dp_aux *aux);
536 :
537 : int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
538 : const u8 dpcd[DP_RECEIVER_CAP_SIZE],
539 : u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
540 : int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
541 : const u8 dpcd[DP_RECEIVER_CAP_SIZE],
542 : enum drm_dp_phy dp_phy,
543 : u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
544 : int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
545 : int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
546 : int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
547 : bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
548 : bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
549 :
550 : void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
551 : void drm_dp_aux_init(struct drm_dp_aux *aux);
552 : int drm_dp_aux_register(struct drm_dp_aux *aux);
553 : void drm_dp_aux_unregister(struct drm_dp_aux *aux);
554 :
555 : int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
556 : int drm_dp_stop_crc(struct drm_dp_aux *aux);
557 :
558 : struct drm_dp_dpcd_ident {
559 : u8 oui[3];
560 : u8 device_id[6];
561 : u8 hw_rev;
562 : u8 sw_major_rev;
563 : u8 sw_minor_rev;
564 : } __packed;
565 :
566 : /**
567 : * struct drm_dp_desc - DP branch/sink device descriptor
568 : * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
569 : * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
570 : */
571 : struct drm_dp_desc {
572 : struct drm_dp_dpcd_ident ident;
573 : u32 quirks;
574 : };
575 :
576 : int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
577 : bool is_branch);
578 :
579 : /**
580 : * enum drm_dp_quirk - Display Port sink/branch device specific quirks
581 : *
582 : * Display Port sink and branch devices in the wild have a variety of bugs, try
583 : * to collect them here. The quirks are shared, but it's up to the drivers to
584 : * implement workarounds for them.
585 : */
586 : enum drm_dp_quirk {
587 : /**
588 : * @DP_DPCD_QUIRK_CONSTANT_N:
589 : *
590 : * The device requires main link attributes Mvid and Nvid to be limited
591 : * to 16 bits. So will give a constant value (0x8000) for compatability.
592 : */
593 : DP_DPCD_QUIRK_CONSTANT_N,
594 : /**
595 : * @DP_DPCD_QUIRK_NO_PSR:
596 : *
597 : * The device does not support PSR even if reports that it supports or
598 : * driver still need to implement proper handling for such device.
599 : */
600 : DP_DPCD_QUIRK_NO_PSR,
601 : /**
602 : * @DP_DPCD_QUIRK_NO_SINK_COUNT:
603 : *
604 : * The device does not set SINK_COUNT to a non-zero value.
605 : * The driver should ignore SINK_COUNT during detection. Note that
606 : * drm_dp_read_sink_count_cap() automatically checks for this quirk.
607 : */
608 : DP_DPCD_QUIRK_NO_SINK_COUNT,
609 : /**
610 : * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
611 : *
612 : * The device supports MST DSC despite not supporting Virtual DPCD.
613 : * The DSC caps can be read from the physical aux instead.
614 : */
615 : DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
616 : /**
617 : * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
618 : *
619 : * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
620 : * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
621 : */
622 : DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
623 : };
624 :
625 : /**
626 : * drm_dp_has_quirk() - does the DP device have a specific quirk
627 : * @desc: Device descriptor filled by drm_dp_read_desc()
628 : * @quirk: Quirk to query for
629 : *
630 : * Return true if DP device identified by @desc has @quirk.
631 : */
632 : static inline bool
633 : drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
634 : {
635 : return desc->quirks & BIT(quirk);
636 : }
637 :
638 : /**
639 : * struct drm_edp_backlight_info - Probed eDP backlight info struct
640 : * @pwmgen_bit_count: The pwmgen bit count
641 : * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
642 : * @max: The maximum backlight level that may be set
643 : * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
644 : * @aux_enable: Does the panel support the AUX enable cap?
645 : * @aux_set: Does the panel support setting the brightness through AUX?
646 : *
647 : * This structure contains various data about an eDP backlight, which can be populated by using
648 : * drm_edp_backlight_init().
649 : */
650 : struct drm_edp_backlight_info {
651 : u8 pwmgen_bit_count;
652 : u8 pwm_freq_pre_divider;
653 : u16 max;
654 :
655 : bool lsb_reg_used : 1;
656 : bool aux_enable : 1;
657 : bool aux_set : 1;
658 : };
659 :
660 : int
661 : drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
662 : u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
663 : u16 *current_level, u8 *current_mode);
664 : int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
665 : u16 level);
666 : int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
667 : u16 level);
668 : int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
669 :
670 : #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
671 : (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
672 :
673 : int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
674 :
675 : #else
676 :
677 : static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
678 : struct drm_dp_aux *aux)
679 : {
680 : return 0;
681 : }
682 :
683 : #endif
684 :
685 : #ifdef CONFIG_DRM_DP_CEC
686 : void drm_dp_cec_irq(struct drm_dp_aux *aux);
687 : void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
688 : struct drm_connector *connector);
689 : void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
690 : void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
691 : void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
692 : #else
693 : static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
694 : {
695 : }
696 :
697 : static inline void
698 : drm_dp_cec_register_connector(struct drm_dp_aux *aux,
699 : struct drm_connector *connector)
700 : {
701 : }
702 :
703 : static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
704 : {
705 : }
706 :
707 : static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
708 : const struct edid *edid)
709 : {
710 : }
711 :
712 : static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
713 : {
714 : }
715 :
716 : #endif
717 :
718 : /**
719 : * struct drm_dp_phy_test_params - DP Phy Compliance parameters
720 : * @link_rate: Requested Link rate from DPCD 0x219
721 : * @num_lanes: Number of lanes requested by sing through DPCD 0x220
722 : * @phy_pattern: DP Phy test pattern from DPCD 0x248
723 : * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
724 : * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
725 : * @enhanced_frame_cap: flag for enhanced frame capability.
726 : */
727 : struct drm_dp_phy_test_params {
728 : int link_rate;
729 : u8 num_lanes;
730 : u8 phy_pattern;
731 : u8 hbr2_reset[2];
732 : u8 custom80[10];
733 : bool enhanced_frame_cap;
734 : };
735 :
736 : int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
737 : struct drm_dp_phy_test_params *data);
738 : int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
739 : struct drm_dp_phy_test_params *data, u8 dp_rev);
740 : int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
741 : const u8 port_cap[4]);
742 : int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
743 : bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
744 : int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
745 : u8 frl_mode);
746 : int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
747 : u8 frl_type);
748 : int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
749 : int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
750 :
751 : bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
752 : int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
753 : void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
754 : struct drm_connector *connector);
755 : bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
756 : int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
757 : int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
758 : int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
759 : int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
760 : int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
761 : int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
762 : bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
763 : const u8 port_cap[4], u8 color_spc);
764 : int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
765 :
766 : #endif /* _DRM_DP_HELPER_H_ */
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